diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash.c
index 1118ec1be5..71d1b761c3 100644
--- a/components/bootloader_support/bootloader_flash/src/bootloader_flash.c
+++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash.c
@@ -232,19 +232,20 @@ static uint32_t current_read_mapping = UINT32_MAX;
  */
 static void rom_read_api_workaround(void)
 {
-#if CONFIG_ESP32C6_REV_MIN_0
-    extern void spi_common_set_dummy_output(esp_rom_spiflash_read_mode_t mode);
-    extern void spi_dummy_len_fix(uint8_t spi, uint8_t freqdiv);
+#if CONFIG_ESP32C6_REV_MIN_FULL == 0
+    if (efuse_hal_chip_revision() == 0) {
+        extern void spi_common_set_dummy_output(esp_rom_spiflash_read_mode_t mode);
+        extern void spi_dummy_len_fix(uint8_t spi, uint8_t freqdiv);
 
-    static bool is_first_call = true;
-    if (is_first_call) {
-        uint32_t dummy_val = UINT32_MAX;
-        uint32_t dest_addr = ESP_PARTITION_TABLE_OFFSET + ESP_PARTITION_TABLE_MAX_LEN;
-        esp_rom_spiflash_write(dest_addr, &dummy_val, sizeof(dummy_val));
-        is_first_call = false;
-    }
+        static bool is_first_call = true;
+        if (is_first_call) {
+            uint32_t dummy_val = UINT32_MAX;
+            uint32_t dest_addr = ESP_PARTITION_TABLE_OFFSET + ESP_PARTITION_TABLE_MAX_LEN;
+            esp_rom_spiflash_write(dest_addr, &dummy_val, sizeof(dummy_val));
+            is_first_call = false;
+        }
 
-    uint32_t freqdiv = 0;
+        uint32_t freqdiv = 0;
 
 #if CONFIG_ESPTOOLPY_FLASHFREQ_80M
     freqdiv = 1;
@@ -265,10 +266,11 @@ static void rom_read_api_workaround(void)
     read_mode = ESP_ROM_SPIFLASH_DOUT_MODE;
 #endif
 
-    esp_rom_spiflash_config_clk(freqdiv, 1);
-    spi_dummy_len_fix(1, freqdiv);
-    esp_rom_spiflash_config_readmode(read_mode);
-    spi_common_set_dummy_output(read_mode);
+        esp_rom_spiflash_config_clk(freqdiv, 1);
+        spi_dummy_len_fix(1, freqdiv);
+        esp_rom_spiflash_config_readmode(read_mode);
+        spi_common_set_dummy_output(read_mode);
+    }
 #endif
 }
 
diff --git a/components/bt/include/esp32c3/include/esp_bt.h b/components/bt/include/esp32c3/include/esp_bt.h
index 78daf08428..48e939be06 100644
--- a/components/bt/include/esp32c3/include/esp_bt.h
+++ b/components/bt/include/esp32c3/include/esp_bt.h
@@ -175,11 +175,11 @@ typedef void (* esp_bt_hci_tl_callback_t) (void *arg, uint8_t status);
 #define BT_CTRL_AGC_RECORRECT_NEW       1
 #else
 //Check if chip target is ESP32-C3 101
-#if CONFIG_ESP32C3_REV_MIN_101
+#if CONFIG_ESP32C3_REV_MIN_FULL >= 101
 #define BT_CTRL_AGC_RECORRECT_NEW       1
 #else
 #define BT_CTRL_AGC_RECORRECT_NEW       0
-#endif // CONFIG_ESP32C3_REV_MIN_101
+#endif // CONFIG_ESP32C3_REV_MIN_FULL >= 101
 #endif // CONFIG_IDF_TARGET_ESP32S3
 
 #else
diff --git a/components/esp_psram/include/esp_private/esp_psram_mspi.h b/components/esp_psram/include/esp_private/esp_psram_mspi.h
index 7610d99c14..cf33a7afee 100644
--- a/components/esp_psram/include/esp_private/esp_psram_mspi.h
+++ b/components/esp_psram/include/esp_private/esp_psram_mspi.h
@@ -15,7 +15,7 @@
 extern "C" {
 #endif
 
-#define ESP_PSRAM_MSPI_MB_WORKAROUND    (CONFIG_IDF_TARGET_ESP32C5 && CONFIG_ESP32C5_REV_MIN_FULL < 102) || (CONFIG_IDF_TARGET_ESP32C61 && CONFIG_ESP32C61_REV_MIN_FULL < 101)
+#define ESP_PSRAM_MSPI_MB_WORKAROUND    ((CONFIG_IDF_TARGET_ESP32C5 && CONFIG_ESP32C5_REV_MIN_FULL < 102) || (CONFIG_IDF_TARGET_ESP32C61 && CONFIG_ESP32C61_REV_MIN_FULL < 101))
 
 /**
  * @brief Initialize PSRAM MSPI memory barrier
diff --git a/components/esp_rom/patches/esp_rom_sys.c b/components/esp_rom/patches/esp_rom_sys.c
index 3c231d2c29..848a552419 100644
--- a/components/esp_rom/patches/esp_rom_sys.c
+++ b/components/esp_rom/patches/esp_rom_sys.c
@@ -157,5 +157,5 @@ void __attribute__((constructor)) ets_ops_set_rom_patches(void)
     ets_ops_table_ptr = &ets_ops_patch_table_ptr;
 }
 
-#endif // CONFIG_ESP32C5_REV_MIN_100 || CONFIG_ESP32C61_REV_MIN_100
+#endif // CONFIG_ESP32C5_REV_MIN_FULL <= 100 || CONFIG_ESP32C61_REV_MIN_FULL <= 100
 #endif // ESP_ROM_DELAY_US_PATCH && CONFIG_SECURE_ENABLE_TEE && !NON_OS_BUILD