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refactor(rcc): unify the usage of clock control macros for peripherals

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- Removed conditional definitions for various RCC_ATOMIC macros across
multiple files, replacing them with a unified PERIPH_RCC_ATOMIC() macro.
- Updated instances where specific RCC_ATOMIC macros were used to ensure
consistent usage of PERIPH_RCC_ATOMIC().
- Deleted unused uart_share_hw_ctrl.h file as its functionality is now
integrated into the new structure.
This commit is contained in:
morris
2026-01-20 11:01:23 +08:00
parent 6640b5a2de
commit 0469db2f83
77 changed files with 212 additions and 551 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/esp_driver_sdmmc/include/esp_private/sd_host_private.h
-14
View File
@@ -43,20 +43,6 @@ extern "C" {
#define SD_HOST_SDMMC_DMA_ALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT | MALLOC_CAP_DMA)
#endif
#if !SOC_RCC_IS_INDEPENDENT
// Reset and Clock Control registers are mixing with other peripherals, so we need to use a critical section
#define SD_HOST_SDMMC_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
#else
#define SD_HOST_SDMMC_RCC_ATOMIC()
#endif
#if SOC_PERIPH_CLK_CTRL_SHARED
// Clock source and related clock settings are mixing with other peripherals, so we need to use a critical section
#define SD_HOST_SDMMC_CLK_SRC_ATOMIC() PERIPH_RCC_ATOMIC()
#else
#define SD_HOST_SDMMC_CLK_SRC_ATOMIC()
#endif
#define SD_HOST_SDMMC_CLOCK_UPDATE_CMD_TIMEOUT_US (1000 * 1000)
#define SD_HOST_SDMMC_START_CMD_TIMEOUT_US (1000 * 1000)
#define SD_HOST_SDMMC_RESET_TIMEOUT_US (5000 * 1000)
components/esp_driver_sdmmc/src/sd_host_sdmmc.c
+4 -4
View File
@@ -663,7 +663,7 @@ esp_err_t sd_host_set_delay_phase(sd_host_sdmmc_slot_t *slot)
delay_phase_num = 0;
break;
}
SD_HOST_SDMMC_CLK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
sdmmc_ll_set_din_delay_phase(slot->ctlr->hal.dev, phase, speed_mode);
sdmmc_ll_set_dout_delay_phase(slot->ctlr->hal.dev, phase, speed_mode);
}
@@ -753,7 +753,7 @@ static esp_err_t sd_host_claim_controller(sd_host_sdmmc_ctlr_t *controller)
if (found) {
s_platform.controllers[i] = controller;
controller->host_id = i;
SD_HOST_SDMMC_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
sdmmc_ll_enable_bus_clock(i, true);
sdmmc_ll_reset_register(i);
}
@@ -774,7 +774,7 @@ static esp_err_t sd_host_declaim_controller(sd_host_sdmmc_ctlr_t *controller)
_lock_acquire(&s_platform.mutex);
s_platform.controllers[controller->host_id] = NULL;
SD_HOST_SDMMC_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
sdmmc_ll_enable_bus_clock(0, false);
}
_lock_release(&s_platform.mutex);
@@ -980,7 +980,7 @@ static esp_err_t sd_host_reset(sd_host_sdmmc_ctlr_t *ctlr)
static void sd_host_set_clk_div(sd_host_sdmmc_ctlr_t *ctlr, soc_periph_sdmmc_clk_src_t src, int div)
{
ESP_ERROR_CHECK(esp_clk_tree_enable_src((soc_module_clk_t)src, true));
SD_HOST_SDMMC_CLK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
sdmmc_ll_set_clock_div(ctlr->hal.dev, div);
sdmmc_ll_select_clk_source(ctlr->hal.dev, src);
sdmmc_ll_init_phase_delay(ctlr->hal.dev);