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feat(i2c): support hp & lp i2c on esp32s31

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This commit is contained in:
Chen Chen
2026-03-23 10:59:32 +08:00
parent 184c60d684
commit 0e785af44f
27 changed files with 1656 additions and 424 deletions
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components/driver/test_apps/legacy_i2c_driver/README.md
+2 -2
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@@ -1,2 +1,2 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | | Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | | ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- |
components/esp_driver_i2c/test_apps/i2c_test_apps/README.md
+2 -2
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@@ -1,2 +1,2 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | | Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | | ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- |
components/esp_driver_i2c/test_apps/i2c_test_apps/main/test_i2c_common.cpp
+1 -1
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@@ -306,7 +306,7 @@ TEST_CASE("I2C master transaction non-blocking mode with large amount of transac
i2c_device_config_t dev_cfg = {}; i2c_device_config_t dev_cfg = {};
dev_cfg.dev_addr_length = I2C_ADDR_BIT_LEN_7; dev_cfg.dev_addr_length = I2C_ADDR_BIT_LEN_7;
dev_cfg.device_address = 0x58; dev_cfg.device_address = 0x58;
dev_cfg.scl_speed_hz = 400000; dev_cfg.scl_speed_hz = 200000;
dev_cfg.flags.disable_ack_check = true; dev_cfg.flags.disable_ack_check = true;
i2c_master_dev_handle_t dev_handle; i2c_master_dev_handle_t dev_handle;
components/esp_driver_i2c/test_apps/i2c_test_apps/main/test_lp_i2c.cpp
+5 -1
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Unlicense OR CC0-1.0 * SPDX-License-Identifier: Unlicense OR CC0-1.0
*/ */
@@ -80,6 +80,8 @@ TEST_CASE("LP I2C initialize with wrong IO", "[i2c]")
#endif #endif
#if !CONFIG_IDF_TARGET_ESP32S31 // LP_I2C has the same clock source as HP_I2C on ESP32S31
TEST_CASE("LP I2C initialize with wrong clock source", "[i2c]") TEST_CASE("LP I2C initialize with wrong clock source", "[i2c]")
{ {
i2c_master_bus_config_t i2c_mst_config = {}; i2c_master_bus_config_t i2c_mst_config = {};
@@ -94,6 +96,8 @@ TEST_CASE("LP I2C initialize with wrong clock source", "[i2c]")
TEST_ESP_ERR(ESP_ERR_NOT_SUPPORTED, i2c_new_master_bus(&i2c_mst_config, &bus_handle)); TEST_ESP_ERR(ESP_ERR_NOT_SUPPORTED, i2c_new_master_bus(&i2c_mst_config, &bus_handle));
} }
#endif
static void lp_i2c_master_write_test(void) static void lp_i2c_master_write_test(void)
{ {
uint8_t data_wr[DATA_LENGTH] = { 0 }; uint8_t data_wr[DATA_LENGTH] = { 0 };
components/esp_driver_i2c/test_apps/i2c_test_apps/pytest_i2c.py
+1 -1
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@@ -16,7 +16,6 @@ from pytest_embedded_idf.utils import soc_filtered_targets
indirect=True, indirect=True,
) )
@idf_parametrize('target', ['supported_targets'], indirect=['target']) @idf_parametrize('target', ['supported_targets'], indirect=['target'])
@pytest.mark.temp_skip_ci(targets=['esp32s31'], reason='s31 bringup on this module is not done')
def test_i2c(dut: Dut) -> None: def test_i2c(dut: Dut) -> None:
dut.run_all_single_board_cases() dut.run_all_single_board_cases()
@@ -32,6 +31,7 @@ def test_i2c(dut: Dut) -> None:
indirect=True, indirect=True,
) )
@idf_parametrize('target', soc_filtered_targets('SOC_I2C_SUPPORTED == 1'), indirect=['target']) @idf_parametrize('target', soc_filtered_targets('SOC_I2C_SUPPORTED == 1'), indirect=['target'])
@pytest.mark.temp_skip_ci(targets=['esp32s31'], reason='lack of s31 multi-device runner # TODO: IDFCI-10334')
def test_i2c_multi_device(case_tester) -> None: # type: ignore def test_i2c_multi_device(case_tester) -> None: # type: ignore
case_tester.run_all_multi_dev_cases(reset=True) case_tester.run_all_multi_dev_cases(reset=True)
components/esp_hal_i2c/esp32c5/i2c_periph.c
+4 -4
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -40,11 +40,11 @@ const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {
Include: I2C_SCL_LOW_PERIOD_REG / Include: I2C_SCL_LOW_PERIOD_REG /
I2C_CTR_REG / I2C_TO_REG / I2C_SLAVE_ADDR_REG / I2C_FIFO_CONF_REG I2C_CTR_REG / I2C_TO_REG / I2C_SLAVE_ADDR_REG / I2C_FIFO_CONF_REG
I2C_INT_ENA_REG / I2C_SDA_HOLD_REG / I2C_SDA_SAMPLE_REG / I2C_SCL_START_HOLD_REG I2C_INT_ENA_REG / I2C_SDA_HOLD_REG / I2C_SDA_SAMPLE_REG / I2C_SCL_START_HOLD_REG
I2C_SCL_RSTART_SETUP_REG / I2C_SCL_STOP_HOLD_REG / I2C_SCL_STOP_SETUP_REG /I2C_FILTER_CFG_REG / I2C_CLK_CONF_REG / I2C_SCL_ST_TIME_OUT_REG / I2C_SCL_MAIN_ST_TIME_OUT_REG / I2C_SCL_SP_CONF_REG / I2C_SCL_STRETCH_CONF_REG I2C_SCL_RSTART_SETUP_REG / I2C_SCL_STOP_HOLD_REG / I2C_SCL_STOP_SETUP_REG /I2C_FILTER_CFG_REG / I2C_SCL_ST_TIME_OUT_REG / I2C_SCL_MAIN_ST_TIME_OUT_REG / I2C_SCL_SP_CONF_REG / I2C_SCL_STRETCH_CONF_REG
*/ */
#define I2C0_RETENTION_REGS_CNT 18 #define I2C0_RETENTION_REGS_CNT 17
#define I2C0_RETENTION_MAP_BASE I2C_SCL_LOW_PERIOD_REG(0) #define I2C0_RETENTION_MAP_BASE I2C_SCL_LOW_PERIOD_REG(0)
static const uint32_t i2c0_regs_map[4] = {0xc03f345b, 0x3, 0, 0}; static const uint32_t i2c0_regs_map[4] = {0xc01f345b, 0x3, 0, 0};
static const regdma_entries_config_t i2c0_regs_retention[] = { static const regdma_entries_config_t i2c0_regs_retention[] = {
[0] = { [0] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_I2C_LINK(0x00), I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_REGS_CNT, 0, 0, i2c0_regs_map[0], i2c0_regs_map[1], i2c0_regs_map[2], i2c0_regs_map[3]), \ .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_I2C_LINK(0x00), I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_REGS_CNT, 0, 0, i2c0_regs_map[0], i2c0_regs_map[1], i2c0_regs_map[2], i2c0_regs_map[3]), \
components/esp_hal_i2c/esp32c6/i2c_periph.c
+4 -4
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -41,11 +41,11 @@ const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {
Include: I2C_SCL_LOW_PERIOD_REG / Include: I2C_SCL_LOW_PERIOD_REG /
I2C_CTR_REG / I2C_TO_REG / I2C_SLAVE_ADDR_REG / I2C_FIFO_CONF_REG I2C_CTR_REG / I2C_TO_REG / I2C_SLAVE_ADDR_REG / I2C_FIFO_CONF_REG
I2C_INT_ENA_REG / I2C_SDA_HOLD_REG / I2C_SDA_SAMPLE_REG / I2C_SCL_START_HOLD_REG I2C_INT_ENA_REG / I2C_SDA_HOLD_REG / I2C_SDA_SAMPLE_REG / I2C_SCL_START_HOLD_REG
I2C_SCL_RSTART_SETUP_REG / I2C_SCL_STOP_HOLD_REG / I2C_SCL_STOP_SETUP_REG /I2C_FILTER_CFG_REG / I2C_CLK_CONF_REG / I2C_SCL_ST_TIME_OUT_REG / I2C_SCL_MAIN_ST_TIME_OUT_REG / I2C_SCL_SP_CONF_REG / I2C_SCL_STRETCH_CONF_REG I2C_SCL_RSTART_SETUP_REG / I2C_SCL_STOP_HOLD_REG / I2C_SCL_STOP_SETUP_REG /I2C_FILTER_CFG_REG / I2C_SCL_ST_TIME_OUT_REG / I2C_SCL_MAIN_ST_TIME_OUT_REG / I2C_SCL_SP_CONF_REG / I2C_SCL_STRETCH_CONF_REG
*/ */
#define I2C0_RETENTION_REGS_CNT 18 #define I2C0_RETENTION_REGS_CNT 17
#define I2C0_RETENTION_MAP_BASE I2C_SCL_LOW_PERIOD_REG(0) #define I2C0_RETENTION_MAP_BASE I2C_SCL_LOW_PERIOD_REG(0)
static const uint32_t i2c0_regs_map[4] = {0xc03f345b, 0x3, 0, 0}; static const uint32_t i2c0_regs_map[4] = {0xc01f345b, 0x3, 0, 0};
static const regdma_entries_config_t i2c0_regs_retention[] = { static const regdma_entries_config_t i2c0_regs_retention[] = {
[0] = { [0] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_I2C_LINK(0x00), I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_REGS_CNT, 0, 0, i2c0_regs_map[0], i2c0_regs_map[1], i2c0_regs_map[2], i2c0_regs_map[3]), \ .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_I2C_LINK(0x00), I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_REGS_CNT, 0, 0, i2c0_regs_map[0], i2c0_regs_map[1], i2c0_regs_map[2], i2c0_regs_map[3]), \
components/esp_hal_i2c/esp32c61/i2c_periph.c
+4 -4
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -29,11 +29,11 @@ const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {
Include: I2C_SCL_LOW_PERIOD_REG / Include: I2C_SCL_LOW_PERIOD_REG /
I2C_CTR_REG / I2C_TO_REG / I2C_SLAVE_ADDR_REG / I2C_FIFO_CONF_REG I2C_CTR_REG / I2C_TO_REG / I2C_SLAVE_ADDR_REG / I2C_FIFO_CONF_REG
I2C_INT_ENA_REG / I2C_SDA_HOLD_REG / I2C_SDA_SAMPLE_REG / I2C_SCL_START_HOLD_REG I2C_INT_ENA_REG / I2C_SDA_HOLD_REG / I2C_SDA_SAMPLE_REG / I2C_SCL_START_HOLD_REG
I2C_SCL_RSTART_SETUP_REG / I2C_SCL_STOP_HOLD_REG / I2C_SCL_STOP_SETUP_REG /I2C_FILTER_CFG_REG / I2C_CLK_CONF_REG / I2C_SCL_ST_TIME_OUT_REG / I2C_SCL_MAIN_ST_TIME_OUT_REG / I2C_SCL_SP_CONF_REG / I2C_SCL_STRETCH_CONF_REG I2C_SCL_RSTART_SETUP_REG / I2C_SCL_STOP_HOLD_REG / I2C_SCL_STOP_SETUP_REG /I2C_FILTER_CFG_REG / I2C_SCL_ST_TIME_OUT_REG / I2C_SCL_MAIN_ST_TIME_OUT_REG / I2C_SCL_SP_CONF_REG / I2C_SCL_STRETCH_CONF_REG
*/ */
#define I2C0_RETENTION_REGS_CNT 18 #define I2C0_RETENTION_REGS_CNT 17
#define I2C0_RETENTION_MAP_BASE I2C_SCL_LOW_PERIOD_REG #define I2C0_RETENTION_MAP_BASE I2C_SCL_LOW_PERIOD_REG
static const uint32_t i2c0_regs_map[4] = {0xc03f345b, 0x3, 0, 0}; static const uint32_t i2c0_regs_map[4] = {0xc01f345b, 0x3, 0, 0};
static const regdma_entries_config_t i2c0_regs_retention[] = { static const regdma_entries_config_t i2c0_regs_retention[] = {
[0] = { [0] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_I2C_LINK(0x00), I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_REGS_CNT, 0, 0, i2c0_regs_map[0], i2c0_regs_map[1], i2c0_regs_map[2], i2c0_regs_map[3]), \ .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_I2C_LINK(0x00), I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_REGS_CNT, 0, 0, i2c0_regs_map[0], i2c0_regs_map[1], i2c0_regs_map[2], i2c0_regs_map[3]), \
components/esp_hal_i2c/esp32h2/i2c_periph.c
+6 -6
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -38,11 +38,11 @@ const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {
Include: I2C_SCL_LOW_PERIOD_REG / Include: I2C_SCL_LOW_PERIOD_REG /
I2C_CTR_REG / I2C_TO_REG / I2C_SLAVE_ADDR_REG / I2C_FIFO_CONF_REG I2C_CTR_REG / I2C_TO_REG / I2C_SLAVE_ADDR_REG / I2C_FIFO_CONF_REG
I2C_INT_ENA_REG / I2C_SDA_HOLD_REG / I2C_SDA_SAMPLE_REG / I2C_SCL_START_HOLD_REG I2C_INT_ENA_REG / I2C_SDA_HOLD_REG / I2C_SDA_SAMPLE_REG / I2C_SCL_START_HOLD_REG
I2C_SCL_RSTART_SETUP_REG / I2C_SCL_STOP_HOLD_REG / I2C_SCL_STOP_SETUP_REG /I2C_FILTER_CFG_REG / I2C_CLK_CONF_REG / I2C_SCL_ST_TIME_OUT_REG / I2C_SCL_MAIN_ST_TIME_OUT_REG / I2C_SCL_SP_CONF_REG / I2C_SCL_STRETCH_CONF_REG I2C_SCL_RSTART_SETUP_REG / I2C_SCL_STOP_HOLD_REG / I2C_SCL_STOP_SETUP_REG /I2C_FILTER_CFG_REG / I2C_SCL_ST_TIME_OUT_REG / I2C_SCL_MAIN_ST_TIME_OUT_REG / I2C_SCL_SP_CONF_REG / I2C_SCL_STRETCH_CONF_REG
*/ */
#define I2C0_RETENTION_REGS_CNT 18 #define I2C0_RETENTION_REGS_CNT 17
#define I2C0_RETENTION_MAP_BASE I2C_SCL_LOW_PERIOD_REG(0) #define I2C0_RETENTION_MAP_BASE I2C_SCL_LOW_PERIOD_REG(0)
static const uint32_t i2c0_regs_map[4] = {0xc03f345b, 0x3, 0, 0}; static const uint32_t i2c0_regs_map[4] = {0xc01f345b, 0x3, 0, 0};
static const regdma_entries_config_t i2c0_regs_retention[] = { static const regdma_entries_config_t i2c0_regs_retention[] = {
[0] = { [0] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_I2C_LINK(0x00), I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_REGS_CNT, 0, 0, i2c0_regs_map[0], i2c0_regs_map[1], i2c0_regs_map[2], i2c0_regs_map[3]), \ .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_I2C_LINK(0x00), I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_REGS_CNT, 0, 0, i2c0_regs_map[0], i2c0_regs_map[1], i2c0_regs_map[2], i2c0_regs_map[3]), \
@@ -66,9 +66,9 @@ static const regdma_entries_config_t i2c0_regs_retention[] = {
}, \ }, \
}; };
#define I2C1_RETENTION_REGS_CNT 18 #define I2C1_RETENTION_REGS_CNT 17
#define I2C1_RETENTION_MAP_BASE I2C_SCL_LOW_PERIOD_REG(1) #define I2C1_RETENTION_MAP_BASE I2C_SCL_LOW_PERIOD_REG(1)
static const uint32_t i2c1_regs_map[4] = {0xc03f345b, 0x3, 0, 0}; static const uint32_t i2c1_regs_map[4] = {0xc01f345b, 0x3, 0, 0};
static const regdma_entries_config_t i2c1_regs_retention[] = { static const regdma_entries_config_t i2c1_regs_retention[] = {
[0] = { [0] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_I2C_LINK(0x00), I2C1_RETENTION_MAP_BASE, I2C1_RETENTION_MAP_BASE, I2C1_RETENTION_REGS_CNT, 0, 0, i2c1_regs_map[0], i2c1_regs_map[1], i2c1_regs_map[2], i2c1_regs_map[3]), \ .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_I2C_LINK(0x00), I2C1_RETENTION_MAP_BASE, I2C1_RETENTION_MAP_BASE, I2C1_RETENTION_REGS_CNT, 0, 0, i2c1_regs_map[0], i2c1_regs_map[1], i2c1_regs_map[2], i2c1_regs_map[3]), \
components/esp_hal_i2c/esp32h4/i2c_periph.c
+6 -6
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -38,11 +38,11 @@ const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {
Include: I2C_SCL_LOW_PERIOD_REG / Include: I2C_SCL_LOW_PERIOD_REG /
I2C_CTR_REG / I2C_TO_REG / I2C_SLAVE_ADDR_REG / I2C_FIFO_CONF_REG I2C_CTR_REG / I2C_TO_REG / I2C_SLAVE_ADDR_REG / I2C_FIFO_CONF_REG
I2C_INT_ENA_REG / I2C_SDA_HOLD_REG / I2C_SDA_SAMPLE_REG / I2C_SCL_START_HOLD_REG I2C_INT_ENA_REG / I2C_SDA_HOLD_REG / I2C_SDA_SAMPLE_REG / I2C_SCL_START_HOLD_REG
I2C_SCL_RSTART_SETUP_REG / I2C_SCL_STOP_HOLD_REG / I2C_SCL_STOP_SETUP_REG /I2C_FILTER_CFG_REG / I2C_CLK_CONF_REG / I2C_SCL_ST_TIME_OUT_REG / I2C_SCL_MAIN_ST_TIME_OUT_REG / I2C_SCL_SP_CONF_REG / I2C_SCL_STRETCH_CONF_REG I2C_SCL_RSTART_SETUP_REG / I2C_SCL_STOP_HOLD_REG / I2C_SCL_STOP_SETUP_REG /I2C_FILTER_CFG_REG /I2C_SCL_ST_TIME_OUT_REG / I2C_SCL_MAIN_ST_TIME_OUT_REG / I2C_SCL_SP_CONF_REG / I2C_SCL_STRETCH_CONF_REG
*/ */
#define I2C0_RETENTION_REGS_CNT 18 #define I2C0_RETENTION_REGS_CNT 17
#define I2C0_RETENTION_MAP_BASE I2C_SCL_LOW_PERIOD_REG(0) #define I2C0_RETENTION_MAP_BASE I2C_SCL_LOW_PERIOD_REG(0)
static const uint32_t i2c0_regs_map[4] = {0xc03f345b, 0x3, 0, 0}; static const uint32_t i2c0_regs_map[4] = {0xc01f345b, 0x3, 0, 0};
static const regdma_entries_config_t i2c0_regs_retention[] = { static const regdma_entries_config_t i2c0_regs_retention[] = {
[0] = { [0] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_I2C_LINK(0x00), I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_REGS_CNT, 0, 0, i2c0_regs_map[0], i2c0_regs_map[1], i2c0_regs_map[2], i2c0_regs_map[3]), \ .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_I2C_LINK(0x00), I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_REGS_CNT, 0, 0, i2c0_regs_map[0], i2c0_regs_map[1], i2c0_regs_map[2], i2c0_regs_map[3]), \
@@ -66,9 +66,9 @@ static const regdma_entries_config_t i2c0_regs_retention[] = {
}, \ }, \
}; };
#define I2C1_RETENTION_REGS_CNT 18 #define I2C1_RETENTION_REGS_CNT 17
#define I2C1_RETENTION_MAP_BASE I2C_SCL_LOW_PERIOD_REG(1) #define I2C1_RETENTION_MAP_BASE I2C_SCL_LOW_PERIOD_REG(1)
static const uint32_t i2c1_regs_map[4] = {0xc03f345b, 0x3, 0, 0}; static const uint32_t i2c1_regs_map[4] = {0xc01f345b, 0x3, 0, 0};
static const regdma_entries_config_t i2c1_regs_retention[] = { static const regdma_entries_config_t i2c1_regs_retention[] = {
[0] = { [0] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_I2C_LINK(0x00), I2C1_RETENTION_MAP_BASE, I2C1_RETENTION_MAP_BASE, I2C1_RETENTION_REGS_CNT, 0, 0, i2c1_regs_map[0], i2c1_regs_map[1], i2c1_regs_map[2], i2c1_regs_map[3]), \ .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_I2C_LINK(0x00), I2C1_RETENTION_MAP_BASE, I2C1_RETENTION_MAP_BASE, I2C1_RETENTION_REGS_CNT, 0, 0, i2c1_regs_map[0], i2c1_regs_map[1], i2c1_regs_map[2], i2c1_regs_map[3]), \
components/esp_hal_i2c/esp32p4/i2c_periph.c
+6 -6
View File
@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -45,11 +45,11 @@ const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {
Include: I2C_SCL_LOW_PERIOD_REG / Include: I2C_SCL_LOW_PERIOD_REG /
I2C_CTR_REG / I2C_TO_REG / I2C_SLAVE_ADDR_REG / I2C_FIFO_CONF_REG I2C_CTR_REG / I2C_TO_REG / I2C_SLAVE_ADDR_REG / I2C_FIFO_CONF_REG
I2C_INT_ENA_REG / I2C_SDA_HOLD_REG / I2C_SDA_SAMPLE_REG / I2C_SCL_START_HOLD_REG I2C_INT_ENA_REG / I2C_SDA_HOLD_REG / I2C_SDA_SAMPLE_REG / I2C_SCL_START_HOLD_REG
I2C_SCL_RSTART_SETUP_REG / I2C_SCL_STOP_HOLD_REG / I2C_SCL_STOP_SETUP_REG /I2C_FILTER_CFG_REG / I2C_CLK_CONF_REG / I2C_SCL_ST_TIME_OUT_REG / I2C_SCL_MAIN_ST_TIME_OUT_REG / I2C_SCL_SP_CONF_REG / I2C_SCL_STRETCH_CONF_REG I2C_SCL_RSTART_SETUP_REG / I2C_SCL_STOP_HOLD_REG / I2C_SCL_STOP_SETUP_REG /I2C_FILTER_CFG_REG /I2C_SCL_ST_TIME_OUT_REG / I2C_SCL_MAIN_ST_TIME_OUT_REG / I2C_SCL_SP_CONF_REG / I2C_SCL_STRETCH_CONF_REG
*/ */
#define I2C0_RETENTION_REGS_CNT 18 #define I2C0_RETENTION_REGS_CNT 17
#define I2C0_RETENTION_MAP_BASE I2C_SCL_LOW_PERIOD_REG(0) #define I2C0_RETENTION_MAP_BASE I2C_SCL_LOW_PERIOD_REG(0)
static const uint32_t i2c0_regs_map[4] = {0xc03f345b, 0x3, 0, 0}; static const uint32_t i2c0_regs_map[4] = {0xc01f345b, 0x3, 0, 0};
static const regdma_entries_config_t i2c0_regs_retention[] = { static const regdma_entries_config_t i2c0_regs_retention[] = {
[0] = { [0] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_I2C_LINK(0x00), I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_REGS_CNT, 0, 0, i2c0_regs_map[0], i2c0_regs_map[1], i2c0_regs_map[2], i2c0_regs_map[3]), \ .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_I2C_LINK(0x00), I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_REGS_CNT, 0, 0, i2c0_regs_map[0], i2c0_regs_map[1], i2c0_regs_map[2], i2c0_regs_map[3]), \
@@ -73,9 +73,9 @@ static const regdma_entries_config_t i2c0_regs_retention[] = {
}, \ }, \
}; };
#define I2C1_RETENTION_REGS_CNT 18 #define I2C1_RETENTION_REGS_CNT 17
#define I2C1_RETENTION_MAP_BASE I2C_SCL_LOW_PERIOD_REG(1) #define I2C1_RETENTION_MAP_BASE I2C_SCL_LOW_PERIOD_REG(1)
static const uint32_t i2c1_regs_map[4] = {0xc03f345b, 0x3, 0, 0}; static const uint32_t i2c1_regs_map[4] = {0xc01f345b, 0x3, 0, 0};
static const regdma_entries_config_t i2c1_regs_retention[] = { static const regdma_entries_config_t i2c1_regs_retention[] = {
[0] = { [0] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_I2C_LINK(0x00), I2C1_RETENTION_MAP_BASE, I2C1_RETENTION_MAP_BASE, I2C1_RETENTION_REGS_CNT, 0, 0, i2c1_regs_map[0], i2c1_regs_map[1], i2c1_regs_map[2], i2c1_regs_map[3]), \ .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_I2C_LINK(0x00), I2C1_RETENTION_MAP_BASE, I2C1_RETENTION_MAP_BASE, I2C1_RETENTION_REGS_CNT, 0, 0, i2c1_regs_map[0], i2c1_regs_map[1], i2c1_regs_map[2], i2c1_regs_map[3]), \
components/esp_hal_i2c/esp32s31/i2c_periph.c
+107
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@@ -0,0 +1,107 @@
/*
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "hal/i2c_periph.h"
#include "soc/gpio_sig_map.h"
#include "soc/lp_gpio_sig_map.h"
#include "soc/regdma.h"
#include "soc/i2c_reg.h"
/*
Bunch of constants for every I2C peripheral: GPIO signals, irqs, hw addr of registers etc
*/
const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {
{
.module_name = "I2C0",
.sda_out_sig = I2C0_SDA_PAD_OUT_IDX,
.sda_in_sig = I2C0_SDA_PAD_IN_IDX,
.scl_out_sig = I2C0_SCL_PAD_OUT_IDX,
.scl_in_sig = I2C0_SCL_PAD_IN_IDX,
.irq = ETS_I2C0_INTR_SOURCE,
},
{
.module_name = "I2C1",
.sda_out_sig = I2C1_SDA_PAD_OUT_IDX,
.sda_in_sig = I2C1_SDA_PAD_IN_IDX,
.scl_out_sig = I2C1_SCL_PAD_OUT_IDX,
.scl_in_sig = I2C1_SCL_PAD_IN_IDX,
.irq = ETS_I2C1_INTR_SOURCE,
},
{
.module_name = "LP_I2C0",
.sda_out_sig = LP_I2C_SDA_PAD_OUT_IDX,
.sda_in_sig = LP_I2C_SDA_PAD_IN_IDX,
.scl_out_sig = LP_I2C_SCL_PAD_OUT_IDX,
.scl_in_sig = LP_I2C_SCL_PAD_IN_IDX,
.irq = ETS_LP_I2C_INTR_SOURCE,
},
};
// I2C sleep retention entries
// I2C registers require set the reg_update bit to make the configuration take effect
/* I2C Registers Context
Include: I2C_SCL_LOW_PERIOD_REG /
I2C_CTR_REG / I2C_TO_REG / I2C_SLAVE_ADDR_REG / I2C_FIFO_CONF_REG
I2C_INT_ENA_REG / I2C_SDA_HOLD_REG / I2C_SDA_SAMPLE_REG / I2C_SCL_START_HOLD_REG
I2C_SCL_RSTART_SETUP_REG / I2C_SCL_STOP_HOLD_REG / I2C_SCL_STOP_SETUP_REG /I2C_FILTER_CFG_REG / I2C_SCL_ST_TIME_OUT_REG / I2C_SCL_MAIN_ST_TIME_OUT_REG / I2C_SCL_SP_CONF_REG / I2C_SCL_STRETCH_CONF_REG
*/
#define I2C0_RETENTION_REGS_CNT 17
#define I2C0_RETENTION_MAP_BASE I2C_SCL_LOW_PERIOD_REG(0)
static const uint32_t i2c0_regs_map[4] = {0xc01f345b, 0x3, 0, 0};
static const regdma_entries_config_t i2c0_regs_retention[] = {
[0] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_I2C_LINK(0x00), I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_REGS_CNT, 0, 0, i2c0_regs_map[0], i2c0_regs_map[1], i2c0_regs_map[2], i2c0_regs_map[3]), \
.owner = ENTRY(0) | ENTRY(2)
}, \
[1] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x01), I2C_CTR_REG(0), I2C_FSM_RST, I2C_FSM_RST_M, 1, 0), \
.owner = ENTRY(0) | ENTRY(2)
}, \
[2] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x02), I2C_CTR_REG(0), 0x0, I2C_FSM_RST_M, 1, 0), \
.owner = ENTRY(0) | ENTRY(2)
}, \
[3] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x03), I2C_CTR_REG(0), I2C_CONF_UPGATE, I2C_CONF_UPGATE_M, 1, 0), \
.owner = ENTRY(0) | ENTRY(2)
}, \
[4] = {
.config = REGDMA_LINK_WAIT_INIT(REGDMA_I2C_LINK(0x04), I2C_CTR_REG(0), 0x0, I2C_CONF_UPGATE_M, 1, 0), \
.owner = ENTRY(0) | ENTRY(2)
}, \
};
#define I2C1_RETENTION_REGS_CNT 17
#define I2C1_RETENTION_MAP_BASE I2C_SCL_LOW_PERIOD_REG(1)
static const uint32_t i2c1_regs_map[4] = {0xc01f345b, 0x3, 0, 0};
static const regdma_entries_config_t i2c1_regs_retention[] = {
[0] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_I2C_LINK(0x00), I2C1_RETENTION_MAP_BASE, I2C1_RETENTION_MAP_BASE, I2C1_RETENTION_REGS_CNT, 0, 0, i2c1_regs_map[0], i2c1_regs_map[1], i2c1_regs_map[2], i2c1_regs_map[3]), \
.owner = ENTRY(0) | ENTRY(2)
}, \
[1] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x01), I2C_CTR_REG(1), I2C_FSM_RST, I2C_FSM_RST_M, 1, 0), \
.owner = ENTRY(0) | ENTRY(2)
}, \
[2] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x02), I2C_CTR_REG(1), 0x0, I2C_FSM_RST_M, 1, 0), \
.owner = ENTRY(0) | ENTRY(2)
}, \
[3] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x03), I2C_CTR_REG(1), I2C_CONF_UPGATE, I2C_CONF_UPGATE_M, 1, 0), \
.owner = ENTRY(0) | ENTRY(2)
}, \
[4] = {
.config = REGDMA_LINK_WAIT_INIT(REGDMA_I2C_LINK(0x04), I2C_CTR_REG(1), 0x0, I2C_CONF_UPGATE_M, 1, 0), \
.owner = ENTRY(0) | ENTRY(2)
}, \
};
const i2c_reg_ctx_link_t i2c_regs_retention[SOC_HP_I2C_NUM] = {
{i2c0_regs_retention, ARRAY_SIZE(i2c0_regs_retention), SLEEP_RETENTION_MODULE_I2C0},
{i2c1_regs_retention, ARRAY_SIZE(i2c1_regs_retention), SLEEP_RETENTION_MODULE_I2C1},
};
components/esp_hal_i2c/esp32s31/include/hal/i2c_ll.h
+1313
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File diff suppressed because it is too large Load Diff
components/esp_hal_i2c/test_apps/hal_i2c/README.md
+2 -2
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@@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | | Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | | ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- |
# HAL I2C test # HAL I2C test
components/esp_lcd/test_apps/i2c_lcd/README.md
+2 -2
View File
@@ -1,4 +1,4 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | | Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | | ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- |
This test app is used to test LCDs with I2C interface. This test app is used to test LCDs with I2C interface.
components/soc/esp32s31/include/soc/Kconfig.soc_caps.in
+48
View File
@@ -83,6 +83,10 @@ config SOC_LEDC_SUPPORTED
bool bool
default y default y
config SOC_I2C_SUPPORTED
bool
default y
config SOC_SYSTIMER_SUPPORTED config SOC_SYSTIMER_SUPPORTED
bool bool
default y default y
@@ -107,6 +111,10 @@ config SOC_LP_PERIPHERALS_SUPPORTED
bool bool
default y default y
config SOC_LP_I2C_SUPPORTED
bool
default y
config SOC_SPIRAM_SUPPORTED config SOC_SPIRAM_SUPPORTED
bool bool
default y default y
@@ -431,6 +439,46 @@ config SOC_RMT_SUPPORT_SLEEP_RETENTION
bool bool
default y default y
config SOC_I2C_NUM
int
default 3
config SOC_HP_I2C_NUM
int
default 2
config SOC_LP_I2C_NUM
int
default 1
config SOC_I2C_SUPPORT_XTAL
bool
default y
config SOC_I2C_SUPPORT_RTC
bool
default y
config SOC_I2C_SUPPORT_10BIT_ADDR
bool
default y
config SOC_I2C_SUPPORT_SLAVE
bool
default y
config SOC_I2C_SLAVE_SUPPORT_BROADCAST
bool
default y
config SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE
bool
default y
config SOC_I2C_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_MMU_PERIPH_NUM config SOC_MMU_PERIPH_NUM
int int
default 2 default 2
components/soc/esp32s31/include/soc/clk_tree_defs.h
+32
View File
@@ -259,6 +259,38 @@ typedef enum {
LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
} soc_periph_ledc_clk_src_legacy_t; } soc_periph_ledc_clk_src_legacy_t;
/////////////////////////////////////////////////I2C////////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of I2C
*/
#define SOC_I2C_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
/**
* @brief Type of I2C clock source.
*/
typedef enum {
I2C_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
I2C_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
I2C_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */
} soc_periph_i2c_clk_src_t;
///////////////////////////////////////////////LP_I2C///////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of LP_I2C
*/
#define SOC_LP_I2C_CLKS {SOC_MOD_CLK_RTC_FAST, SOC_MOD_CLK_XTAL}
/**
* @brief Type of LP_I2C clock source.
*/
typedef enum {
LP_I2C_SCLK_LP_FAST = SOC_MOD_CLK_RTC_FAST, /*!< LP_I2C source clock is RTC_FAST */
LP_I2C_SCLK_XTAL = SOC_MOD_CLK_XTAL, /*!< LP_I2C source clock is XTAL */
LP_I2C_SCLK_DEFAULT = SOC_MOD_CLK_RTC_FAST, /*!< LP_I2C source clock default choice is RTC_FAST */
} soc_periph_lp_i2c_clk_src_t;
/////////////////////////////////////////////////SPI//////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////SPI////////////////////////////////////////////////////////////////////
/** /**
components/soc/esp32s31/include/soc/soc_caps.h
+17 -2
View File
@@ -60,7 +60,7 @@
#define SOC_GPSPI_SUPPORTED 1 #define SOC_GPSPI_SUPPORTED 1
#define SOC_LEDC_SUPPORTED 1 #define SOC_LEDC_SUPPORTED 1
// #define SOC_ISP_SUPPORTED 1 // TODO: [ESP32S31] IDF-14769 // #define SOC_ISP_SUPPORTED 1 // TODO: [ESP32S31] IDF-14769
// #define SOC_I2C_SUPPORTED 1 // TODO: [ESP32S31] IDF-14726 #define SOC_I2C_SUPPORTED 1
#define SOC_SYSTIMER_SUPPORTED 1 // TODO: [ESP32S31] IDF-14693 #define SOC_SYSTIMER_SUPPORTED 1 // TODO: [ESP32S31] IDF-14693
// #define SOC_AES_SUPPORTED 1 // TODO: [ESP32S31] IDF-14633 // #define SOC_AES_SUPPORTED 1 // TODO: [ESP32S31] IDF-14633
// #define SOC_MPI_SUPPORTED 1 // TODO: [ESP32S31] IDF-14633 // #define SOC_MPI_SUPPORTED 1 // TODO: [ESP32S31] IDF-14633
@@ -79,7 +79,7 @@
// #define SOC_ULP_LP_UART_SUPPORTED 1 // TODO: [ESP32S31] IDF-14634 // #define SOC_ULP_LP_UART_SUPPORTED 1 // TODO: [ESP32S31] IDF-14634
#define SOC_LP_GPIO_MATRIX_SUPPORTED 1 #define SOC_LP_GPIO_MATRIX_SUPPORTED 1
#define SOC_LP_PERIPHERALS_SUPPORTED 1 #define SOC_LP_PERIPHERALS_SUPPORTED 1
// #define SOC_LP_I2C_SUPPORTED 1 // TODO: [ESP32S31] IDF-14635 #define SOC_LP_I2C_SUPPORTED 1
// #define SOC_LP_SPI_SUPPORTED 1 // TODO: [ESP32S31] IDF-14639 // #define SOC_LP_SPI_SUPPORTED 1 // TODO: [ESP32S31] IDF-14639
#define SOC_SPIRAM_SUPPORTED 1 // TODO: [ESP32S31] IDF-14718 #define SOC_SPIRAM_SUPPORTED 1 // TODO: [ESP32S31] IDF-14718
#define SOC_PSRAM_DMA_CAPABLE 1 #define SOC_PSRAM_DMA_CAPABLE 1
@@ -230,6 +230,21 @@
#define SOC_RMT_SUPPORT_DMA 1 /*!< RMT peripheral can connect to DMA channel */ #define SOC_RMT_SUPPORT_DMA 1 /*!< RMT peripheral can connect to DMA channel */
#define SOC_RMT_SUPPORT_SLEEP_RETENTION 1 /*!< The sleep retention feature can help back up RMT registers before sleep */ #define SOC_RMT_SUPPORT_SLEEP_RETENTION 1 /*!< The sleep retention feature can help back up RMT registers before sleep */
/*-------------------------- I2C CAPS ----------------------------------------*/
#define SOC_I2C_NUM (3U)
#define SOC_HP_I2C_NUM (2U)
#define SOC_LP_I2C_NUM (1U)
#define SOC_I2C_SUPPORT_XTAL (1)
#define SOC_I2C_SUPPORT_RTC (1)
#define SOC_I2C_SUPPORT_10BIT_ADDR (1)
#define SOC_I2C_SUPPORT_SLAVE (1)
#define SOC_I2C_SLAVE_SUPPORT_BROADCAST (1)
#define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE (1)
#define SOC_I2C_SUPPORT_SLEEP_RETENTION (1)
/*-------------------------- MMU CAPS ----------------------------------------*/ /*-------------------------- MMU CAPS ----------------------------------------*/
#define SOC_MMU_PERIPH_NUM (2U) #define SOC_MMU_PERIPH_NUM (2U)
#define SOC_MMU_LINEAR_ADDRESS_REGION_NUM (2U) #define SOC_MMU_LINEAR_ADDRESS_REGION_NUM (2U)
components/soc/esp32s31/register/soc/i2c_reg.h
+38 -36
View File
@@ -1,5 +1,5 @@
/** /**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 OR MIT * SPDX-License-Identifier: Apache-2.0 OR MIT
*/ */
@@ -10,10 +10,12 @@
extern "C" { extern "C" {
#endif #endif
#define REG_I2C_BASE(i) (DR_REG_I2C0_BASE + (i) * 0x1000)
/** I2C_SCL_LOW_PERIOD_REG register /** I2C_SCL_LOW_PERIOD_REG register
* Configures the low level width of the SCL Clock * Configures the low level width of the SCL Clock
*/ */
#define I2C_SCL_LOW_PERIOD_REG (DR_REG_I2C_BASE + 0x0) #define I2C_SCL_LOW_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x0)
/** I2C_SCL_LOW_PERIOD : R/W; bitpos: [8:0]; default: 0; /** I2C_SCL_LOW_PERIOD : R/W; bitpos: [8:0]; default: 0;
* Configures the low level width of the SCL Clock in Master mode. * Configures the low level width of the SCL Clock in Master mode.
* Measurement unit: I2C_SCLK * Measurement unit: I2C_SCLK
@@ -26,7 +28,7 @@ extern "C" {
/** I2C_CTR_REG register /** I2C_CTR_REG register
* Transmission setting register * Transmission setting register
*/ */
#define I2C_CTR_REG (DR_REG_I2C_BASE + 0x4) #define I2C_CTR_REG(i) (REG_I2C_BASE(i) + 0x4)
/** I2C_SDA_FORCE_OUT : R/W; bitpos: [0]; default: 0; /** I2C_SDA_FORCE_OUT : R/W; bitpos: [0]; default: 0;
* Configures the SDA output mode. * Configures the SDA output mode.
* 0: Open drain output * 0: Open drain output
@@ -166,7 +168,7 @@ extern "C" {
/** I2C_SR_REG register /** I2C_SR_REG register
* I2C working status register * I2C working status register
*/ */
#define I2C_SR_REG (DR_REG_I2C_BASE + 0x8) #define I2C_SR_REG(i) (REG_I2C_BASE(i) + 0x8)
/** I2C_RESP_REC : RO; bitpos: [0]; default: 0; /** I2C_RESP_REC : RO; bitpos: [0]; default: 0;
* Represents the received ACK value in Master mode or Slave mode. * Represents the received ACK value in Master mode or Slave mode.
* 0: ACK * 0: ACK
@@ -270,7 +272,7 @@ extern "C" {
/** I2C_TO_REG register /** I2C_TO_REG register
* Timeout control register for receiving data * Timeout control register for receiving data
*/ */
#define I2C_TO_REG (DR_REG_I2C_BASE + 0xc) #define I2C_TO_REG(i) (REG_I2C_BASE(i) + 0xc)
/** I2C_TIME_OUT_VALUE : R/W; bitpos: [4:0]; default: 16; /** I2C_TIME_OUT_VALUE : R/W; bitpos: [4:0]; default: 16;
* Configures the timeout threshold period for SCL stucking at high or low level. The * Configures the timeout threshold period for SCL stucking at high or low level. The
* actual period is 2\^{}(reg_time_out_value). * actual period is 2\^{}(reg_time_out_value).
@@ -293,7 +295,7 @@ extern "C" {
/** I2C_SLAVE_ADDR_REG register /** I2C_SLAVE_ADDR_REG register
* Local slave address setting register * Local slave address setting register
*/ */
#define I2C_SLAVE_ADDR_REG (DR_REG_I2C_BASE + 0x10) #define I2C_SLAVE_ADDR_REG(i) (REG_I2C_BASE(i) + 0x10)
/** I2C_SLAVE_ADDR : R/W; bitpos: [14:0]; default: 0; /** I2C_SLAVE_ADDR : R/W; bitpos: [14:0]; default: 0;
* Configures the slave address of the I2C slave. * Configures the slave address of the I2C slave.
*/ */
@@ -314,7 +316,7 @@ extern "C" {
/** I2C_FIFO_ST_REG register /** I2C_FIFO_ST_REG register
* FIFO status register * FIFO status register
*/ */
#define I2C_FIFO_ST_REG (DR_REG_I2C_BASE + 0x14) #define I2C_FIFO_ST_REG(i) (REG_I2C_BASE(i) + 0x14)
/** I2C_RXFIFO_RADDR : RO; bitpos: [4:0]; default: 0; /** I2C_RXFIFO_RADDR : RO; bitpos: [4:0]; default: 0;
* Represents the offset address of the APB reading from RX FIFO. * Represents the offset address of the APB reading from RX FIFO.
*/ */
@@ -355,7 +357,7 @@ extern "C" {
/** I2C_FIFO_CONF_REG register /** I2C_FIFO_CONF_REG register
* FIFO configuration register * FIFO configuration register
*/ */
#define I2C_FIFO_CONF_REG (DR_REG_I2C_BASE + 0x18) #define I2C_FIFO_CONF_REG(i) (REG_I2C_BASE(i) + 0x18)
/** I2C_RXFIFO_WM_THRHD : R/W; bitpos: [4:0]; default: 11; /** I2C_RXFIFO_WM_THRHD : R/W; bitpos: [4:0]; default: 11;
* Configures the watermark threshold of RX FIFO in non-FIFO access mode. When * Configures the watermark threshold of RX FIFO in non-FIFO access mode. When
* I2C_FIFO_PRT_EN is 1 and RX FIFO counter is bigger than I2C_RXFIFO_WM_THRHD[4:0], * I2C_FIFO_PRT_EN is 1 and RX FIFO counter is bigger than I2C_RXFIFO_WM_THRHD[4:0],
@@ -425,7 +427,7 @@ extern "C" {
/** I2C_DATA_REG register /** I2C_DATA_REG register
* Rx FIFO read data * Rx FIFO read data
*/ */
#define I2C_DATA_REG (DR_REG_I2C_BASE + 0x1c) #define I2C_DATA_REG(i) (REG_I2C_BASE(i) + 0x1c)
/** I2C_FIFO_RDATA : HRO; bitpos: [7:0]; default: 0; /** I2C_FIFO_RDATA : HRO; bitpos: [7:0]; default: 0;
* Represents the value of RXFIFO read data. * Represents the value of RXFIFO read data.
*/ */
@@ -437,7 +439,7 @@ extern "C" {
/** I2C_INT_RAW_REG register /** I2C_INT_RAW_REG register
* Raw interrupt status register * Raw interrupt status register
*/ */
#define I2C_INT_RAW_REG (DR_REG_I2C_BASE + 0x20) #define I2C_INT_RAW_REG(i) (REG_I2C_BASE(i) + 0x20)
/** I2C_RXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; /** I2C_RXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
* The raw interrupt status of I2C_RXFIFO_WM_INT. * The raw interrupt status of I2C_RXFIFO_WM_INT.
*/ */
@@ -575,7 +577,7 @@ extern "C" {
/** I2C_INT_CLR_REG register /** I2C_INT_CLR_REG register
* Interrupt clear register * Interrupt clear register
*/ */
#define I2C_INT_CLR_REG (DR_REG_I2C_BASE + 0x24) #define I2C_INT_CLR_REG(i) (REG_I2C_BASE(i) + 0x24)
/** I2C_RXFIFO_WM_INT_CLR : WT; bitpos: [0]; default: 0; /** I2C_RXFIFO_WM_INT_CLR : WT; bitpos: [0]; default: 0;
* Write 1 to clear I2C_RXFIFO_WM_INT. * Write 1 to clear I2C_RXFIFO_WM_INT.
*/ */
@@ -713,7 +715,7 @@ extern "C" {
/** I2C_INT_ENA_REG register /** I2C_INT_ENA_REG register
* Interrupt enable register * Interrupt enable register
*/ */
#define I2C_INT_ENA_REG (DR_REG_I2C_BASE + 0x28) #define I2C_INT_ENA_REG(i) (REG_I2C_BASE(i) + 0x28)
/** I2C_RXFIFO_WM_INT_ENA : R/W; bitpos: [0]; default: 0; /** I2C_RXFIFO_WM_INT_ENA : R/W; bitpos: [0]; default: 0;
* Write 1 to enable I2C_RXFIFO_WM_INT. * Write 1 to enable I2C_RXFIFO_WM_INT.
*/ */
@@ -851,7 +853,7 @@ extern "C" {
/** I2C_INT_STATUS_REG register /** I2C_INT_STATUS_REG register
* Status register of captured I2C communication events * Status register of captured I2C communication events
*/ */
#define I2C_INT_STATUS_REG (DR_REG_I2C_BASE + 0x2c) #define I2C_INT_STATUS_REG(i) (REG_I2C_BASE(i) + 0x2c)
/** I2C_RXFIFO_WM_INT_ST : RO; bitpos: [0]; default: 0; /** I2C_RXFIFO_WM_INT_ST : RO; bitpos: [0]; default: 0;
* The masked interrupt status of I2C_RXFIFO_WM_INT. * The masked interrupt status of I2C_RXFIFO_WM_INT.
*/ */
@@ -989,7 +991,7 @@ extern "C" {
/** I2C_SDA_HOLD_REG register /** I2C_SDA_HOLD_REG register
* Configures the hold time after a negative SCL edge * Configures the hold time after a negative SCL edge
*/ */
#define I2C_SDA_HOLD_REG (DR_REG_I2C_BASE + 0x30) #define I2C_SDA_HOLD_REG(i) (REG_I2C_BASE(i) + 0x30)
/** I2C_SDA_HOLD_TIME : R/W; bitpos: [8:0]; default: 0; /** I2C_SDA_HOLD_TIME : R/W; bitpos: [8:0]; default: 0;
* Configures the time to hold the data after the falling edge of SCL. * Configures the time to hold the data after the falling edge of SCL.
* Measurement unit: I2C_SCLK * Measurement unit: I2C_SCLK
@@ -1002,7 +1004,7 @@ extern "C" {
/** I2C_SDA_SAMPLE_REG register /** I2C_SDA_SAMPLE_REG register
* Configures the sample time after a positive SCL edge * Configures the sample time after a positive SCL edge
*/ */
#define I2C_SDA_SAMPLE_REG (DR_REG_I2C_BASE + 0x34) #define I2C_SDA_SAMPLE_REG(i) (REG_I2C_BASE(i) + 0x34)
/** I2C_SDA_SAMPLE_TIME : R/W; bitpos: [8:0]; default: 0; /** I2C_SDA_SAMPLE_TIME : R/W; bitpos: [8:0]; default: 0;
* Configures the time for sampling SDA. * Configures the time for sampling SDA.
* Measurement unit: I2C_SCLK * Measurement unit: I2C_SCLK
@@ -1015,7 +1017,7 @@ extern "C" {
/** I2C_SCL_HIGH_PERIOD_REG register /** I2C_SCL_HIGH_PERIOD_REG register
* Configures the high level width of SCL * Configures the high level width of SCL
*/ */
#define I2C_SCL_HIGH_PERIOD_REG (DR_REG_I2C_BASE + 0x38) #define I2C_SCL_HIGH_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x38)
/** I2C_SCL_HIGH_PERIOD : R/W; bitpos: [8:0]; default: 0; /** I2C_SCL_HIGH_PERIOD : R/W; bitpos: [8:0]; default: 0;
* Configures for how long SCL remains high in Master mode. * Configures for how long SCL remains high in Master mode.
* Measurement unit: I2C_SCLK * Measurement unit: I2C_SCLK
@@ -1036,7 +1038,7 @@ extern "C" {
/** I2C_SCL_START_HOLD_REG register /** I2C_SCL_START_HOLD_REG register
* Configures the delay between the SDA and SCL negative edge for a start condition * Configures the delay between the SDA and SCL negative edge for a start condition
*/ */
#define I2C_SCL_START_HOLD_REG (DR_REG_I2C_BASE + 0x40) #define I2C_SCL_START_HOLD_REG(i) (REG_I2C_BASE(i) + 0x40)
/** I2C_SCL_START_HOLD_TIME : R/W; bitpos: [8:0]; default: 8; /** I2C_SCL_START_HOLD_TIME : R/W; bitpos: [8:0]; default: 8;
* Configures the time between the falling edge of SDA and the falling edge of SCL for * Configures the time between the falling edge of SDA and the falling edge of SCL for
* a START condition. * a START condition.
@@ -1050,7 +1052,7 @@ extern "C" {
/** I2C_SCL_RSTART_SETUP_REG register /** I2C_SCL_RSTART_SETUP_REG register
* Configures the delay between the positive edge of SCL and the negative edge of SDA * Configures the delay between the positive edge of SCL and the negative edge of SDA
*/ */
#define I2C_SCL_RSTART_SETUP_REG (DR_REG_I2C_BASE + 0x44) #define I2C_SCL_RSTART_SETUP_REG(i) (REG_I2C_BASE(i) + 0x44)
/** I2C_SCL_RSTART_SETUP_TIME : R/W; bitpos: [8:0]; default: 8; /** I2C_SCL_RSTART_SETUP_TIME : R/W; bitpos: [8:0]; default: 8;
* Configures the time between the positive edge of SCL and the negative edge of SDA * Configures the time between the positive edge of SCL and the negative edge of SDA
* for a RESTART condition. * for a RESTART condition.
@@ -1064,7 +1066,7 @@ extern "C" {
/** I2C_SCL_STOP_HOLD_REG register /** I2C_SCL_STOP_HOLD_REG register
* Configures the delay after the SCL clock edge for a stop condition * Configures the delay after the SCL clock edge for a stop condition
*/ */
#define I2C_SCL_STOP_HOLD_REG (DR_REG_I2C_BASE + 0x48) #define I2C_SCL_STOP_HOLD_REG(i) (REG_I2C_BASE(i) + 0x48)
/** I2C_SCL_STOP_HOLD_TIME : R/W; bitpos: [8:0]; default: 8; /** I2C_SCL_STOP_HOLD_TIME : R/W; bitpos: [8:0]; default: 8;
* Configures the delay after the STOP condition. * Configures the delay after the STOP condition.
* Measurement unit: I2C_SCLK * Measurement unit: I2C_SCLK
@@ -1078,7 +1080,7 @@ extern "C" {
* Configures the delay between the SDA and SCL rising edge for a stop condition. * Configures the delay between the SDA and SCL rising edge for a stop condition.
* Measurement unit: I2C_SCLK * Measurement unit: I2C_SCLK
*/ */
#define I2C_SCL_STOP_SETUP_REG (DR_REG_I2C_BASE + 0x4c) #define I2C_SCL_STOP_SETUP_REG(i) (REG_I2C_BASE(i) + 0x4c)
/** I2C_SCL_STOP_SETUP_TIME : R/W; bitpos: [8:0]; default: 8; /** I2C_SCL_STOP_SETUP_TIME : R/W; bitpos: [8:0]; default: 8;
* Configures the time between the rising edge of SCL and the rising edge of SDA. * Configures the time between the rising edge of SCL and the rising edge of SDA.
* Measurement unit: I2C_SCLK * Measurement unit: I2C_SCLK
@@ -1091,7 +1093,7 @@ extern "C" {
/** I2C_FILTER_CFG_REG register /** I2C_FILTER_CFG_REG register
* SCL and SDA filter configuration register * SCL and SDA filter configuration register
*/ */
#define I2C_FILTER_CFG_REG (DR_REG_I2C_BASE + 0x50) #define I2C_FILTER_CFG_REG(i) (REG_I2C_BASE(i) + 0x50)
/** I2C_SCL_FILTER_THRES : R/W; bitpos: [3:0]; default: 0; /** I2C_SCL_FILTER_THRES : R/W; bitpos: [3:0]; default: 0;
* Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL * Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL
* input has smaller width than this register value, the I2C controller will ignore * input has smaller width than this register value, the I2C controller will ignore
@@ -1134,7 +1136,7 @@ extern "C" {
/** I2C_COMD0_REG register /** I2C_COMD0_REG register
* I2C command register 0 * I2C command register 0
*/ */
#define I2C_COMD0_REG (DR_REG_I2C_BASE + 0x58) #define I2C_COMD0_REG(i) (REG_I2C_BASE(i) + 0x58)
/** I2C_COMMAND0 : R/W; bitpos: [13:0]; default: 0; /** I2C_COMMAND0 : R/W; bitpos: [13:0]; default: 0;
* Configures command 0. * Configures command 0.
* It consists of three parts: * It consists of three parts:
@@ -1166,7 +1168,7 @@ extern "C" {
/** I2C_COMD1_REG register /** I2C_COMD1_REG register
* I2C command register 1 * I2C command register 1
*/ */
#define I2C_COMD1_REG (DR_REG_I2C_BASE + 0x5c) #define I2C_COMD1_REG(i) (REG_I2C_BASE(i) + 0x5c)
/** I2C_COMMAND1 : R/W; bitpos: [13:0]; default: 0; /** I2C_COMMAND1 : R/W; bitpos: [13:0]; default: 0;
* Configures command 1. See details in I2C_COMD0_REG [13:0]. * Configures command 1. See details in I2C_COMD0_REG [13:0].
*/ */
@@ -1187,7 +1189,7 @@ extern "C" {
/** I2C_COMD2_REG register /** I2C_COMD2_REG register
* I2C command register 2 * I2C command register 2
*/ */
#define I2C_COMD2_REG (DR_REG_I2C_BASE + 0x60) #define I2C_COMD2_REG(i) (REG_I2C_BASE(i) + 0x60)
/** I2C_COMMAND2 : R/W; bitpos: [13:0]; default: 0; /** I2C_COMMAND2 : R/W; bitpos: [13:0]; default: 0;
* Configures command 2. See details in I2C_COMD0_REG [13:0]. * Configures command 2. See details in I2C_COMD0_REG [13:0].
*/ */
@@ -1208,7 +1210,7 @@ extern "C" {
/** I2C_COMD3_REG register /** I2C_COMD3_REG register
* I2C command register 3 * I2C command register 3
*/ */
#define I2C_COMD3_REG (DR_REG_I2C_BASE + 0x64) #define I2C_COMD3_REG(i) (REG_I2C_BASE(i) + 0x64)
/** I2C_COMMAND3 : R/W; bitpos: [13:0]; default: 0; /** I2C_COMMAND3 : R/W; bitpos: [13:0]; default: 0;
* Configures command 3. See details in I2C_COMD0_REG [13:0]. * Configures command 3. See details in I2C_COMD0_REG [13:0].
*/ */
@@ -1229,7 +1231,7 @@ extern "C" {
/** I2C_COMD4_REG register /** I2C_COMD4_REG register
* I2C command register 4 * I2C command register 4
*/ */
#define I2C_COMD4_REG (DR_REG_I2C_BASE + 0x68) #define I2C_COMD4_REG(i) (REG_I2C_BASE(i) + 0x68)
/** I2C_COMMAND4 : R/W; bitpos: [13:0]; default: 0; /** I2C_COMMAND4 : R/W; bitpos: [13:0]; default: 0;
* Configures command 4. See details in I2C_COMD0_REG [13:0]. * Configures command 4. See details in I2C_COMD0_REG [13:0].
*/ */
@@ -1250,7 +1252,7 @@ extern "C" {
/** I2C_COMD5_REG register /** I2C_COMD5_REG register
* I2C command register 5 * I2C command register 5
*/ */
#define I2C_COMD5_REG (DR_REG_I2C_BASE + 0x6c) #define I2C_COMD5_REG(i) (REG_I2C_BASE(i) + 0x6c)
/** I2C_COMMAND5 : R/W; bitpos: [13:0]; default: 0; /** I2C_COMMAND5 : R/W; bitpos: [13:0]; default: 0;
* Configures command 5. See details in I2C_COMD0_REG [13:0]. * Configures command 5. See details in I2C_COMD0_REG [13:0].
*/ */
@@ -1271,7 +1273,7 @@ extern "C" {
/** I2C_COMD6_REG register /** I2C_COMD6_REG register
* I2C command register 6 * I2C command register 6
*/ */
#define I2C_COMD6_REG (DR_REG_I2C_BASE + 0x70) #define I2C_COMD6_REG(i) (REG_I2C_BASE(i) + 0x70)
/** I2C_COMMAND6 : R/W; bitpos: [13:0]; default: 0; /** I2C_COMMAND6 : R/W; bitpos: [13:0]; default: 0;
* Configures command 6. See details in I2C_COMD0_REG [13:0]. * Configures command 6. See details in I2C_COMD0_REG [13:0].
*/ */
@@ -1292,7 +1294,7 @@ extern "C" {
/** I2C_COMD7_REG register /** I2C_COMD7_REG register
* I2C command register 7 * I2C command register 7
*/ */
#define I2C_COMD7_REG (DR_REG_I2C_BASE + 0x74) #define I2C_COMD7_REG(i) (REG_I2C_BASE(i) + 0x74)
/** I2C_COMMAND7 : R/W; bitpos: [13:0]; default: 0; /** I2C_COMMAND7 : R/W; bitpos: [13:0]; default: 0;
* Configures command 7. See details in I2C_COMD0_REG [13:0]. * Configures command 7. See details in I2C_COMD0_REG [13:0].
*/ */
@@ -1313,7 +1315,7 @@ extern "C" {
/** I2C_SCL_ST_TIME_OUT_REG register /** I2C_SCL_ST_TIME_OUT_REG register
* SCL status timeout register * SCL status timeout register
*/ */
#define I2C_SCL_ST_TIME_OUT_REG (DR_REG_I2C_BASE + 0x78) #define I2C_SCL_ST_TIME_OUT_REG(i) (REG_I2C_BASE(i) + 0x78)
/** I2C_SCL_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16; /** I2C_SCL_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16;
* Configures the threshold value of SCL_FSM state unchanged period. It should be no * Configures the threshold value of SCL_FSM state unchanged period. It should be no
* more than 23, more than 1. * more than 23, more than 1.
@@ -1331,7 +1333,7 @@ extern "C" {
/** I2C_SCL_MAIN_ST_TIME_OUT_REG register /** I2C_SCL_MAIN_ST_TIME_OUT_REG register
* SCL main status timeout register * SCL main status timeout register
*/ */
#define I2C_SCL_MAIN_ST_TIME_OUT_REG (DR_REG_I2C_BASE + 0x7c) #define I2C_SCL_MAIN_ST_TIME_OUT_REG(i) (REG_I2C_BASE(i) + 0x7c)
/** I2C_SCL_MAIN_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16; /** I2C_SCL_MAIN_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16;
* Configures the threshold value of SCL_MAIN_FSM state unchanged period. It should be * Configures the threshold value of SCL_MAIN_FSM state unchanged period. It should be
* no more than 23. * no more than 23.
@@ -1345,7 +1347,7 @@ extern "C" {
/** I2C_SCL_SP_CONF_REG register /** I2C_SCL_SP_CONF_REG register
* Power configuration register * Power configuration register
*/ */
#define I2C_SCL_SP_CONF_REG (DR_REG_I2C_BASE + 0x80) #define I2C_SCL_SP_CONF_REG(i) (REG_I2C_BASE(i) + 0x80)
/** I2C_SCL_RST_SLV_EN : R/W/SC; bitpos: [0]; default: 0; /** I2C_SCL_RST_SLV_EN : R/W/SC; bitpos: [0]; default: 0;
* Configures whether or not to send out SCL pulses when I2C master is IDLE. The * Configures whether or not to send out SCL pulses when I2C master is IDLE. The
* number of pulses equals to I2C_SCL_RST_SLV_NUM[4:0]. * number of pulses equals to I2C_SCL_RST_SLV_NUM[4:0].
@@ -1387,7 +1389,7 @@ extern "C" {
/** I2C_SCL_STRETCH_CONF_REG register /** I2C_SCL_STRETCH_CONF_REG register
* SCL stretch setting register of I2C slave * SCL stretch setting register of I2C slave
*/ */
#define I2C_SCL_STRETCH_CONF_REG (DR_REG_I2C_BASE + 0x84) #define I2C_SCL_STRETCH_CONF_REG(i) (REG_I2C_BASE(i) + 0x84)
/** I2C_STRETCH_PROTECT_NUM : R/W; bitpos: [9:0]; default: 0; /** I2C_STRETCH_PROTECT_NUM : R/W; bitpos: [9:0]; default: 0;
* Configures the time period to release the SCL line from stretching to avoid timing * Configures the time period to release the SCL line from stretching to avoid timing
* violation. Usually it should be larger than the SDA setup time. * violation. Usually it should be larger than the SDA setup time.
@@ -1439,7 +1441,7 @@ extern "C" {
/** I2C_DATE_REG register /** I2C_DATE_REG register
* Version control register * Version control register
*/ */
#define I2C_DATE_REG (DR_REG_I2C_BASE + 0xf8) #define I2C_DATE_REG(i) (REG_I2C_BASE(i) + 0xf8)
/** I2C_DATE : R/W; bitpos: [31:0]; default: 38817888; /** I2C_DATE : R/W; bitpos: [31:0]; default: 38817888;
* Version control register. * Version control register.
*/ */
@@ -1451,7 +1453,7 @@ extern "C" {
/** I2C_TXFIFO_START_ADDR_REG register /** I2C_TXFIFO_START_ADDR_REG register
* I2C TXFIFO base address register * I2C TXFIFO base address register
*/ */
#define I2C_TXFIFO_START_ADDR_REG (DR_REG_I2C_BASE + 0x100) #define I2C_TXFIFO_START_ADDR_REG(i) (REG_I2C_BASE(i) + 0x100)
/** I2C_TXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0; /** I2C_TXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0;
* Represents the I2C TX FIFO first address. * Represents the I2C TX FIFO first address.
*/ */
@@ -1463,7 +1465,7 @@ extern "C" {
/** I2C_RXFIFO_START_ADDR_REG register /** I2C_RXFIFO_START_ADDR_REG register
* I2C RXFIFO base address register * I2C RXFIFO base address register
*/ */
#define I2C_RXFIFO_START_ADDR_REG (DR_REG_I2C_BASE + 0x180) #define I2C_RXFIFO_START_ADDR_REG(i) (REG_I2C_BASE(i) + 0x180)
/** I2C_RXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0; /** I2C_RXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0;
* Represents the I2C RX FIFO first address. * Represents the I2C RX FIFO first address.
*/ */
components/soc/esp32s31/register/soc/i2c_struct.h
+20 -166
View File
@@ -1,5 +1,5 @@
/** /**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 OR MIT * SPDX-License-Identifier: Apache-2.0 OR MIT
*/ */
@@ -965,176 +965,35 @@ typedef union {
/** Group: Command registers */ /** Group: Command registers */
/** Type of comd0 register /** Type of comd0~7 register
* I2C command register 0 * I2C command register 0~7
*/ */
typedef union { typedef union {
struct { struct {
/** command0 : R/W; bitpos: [13:0]; default: 0; /** command : R/W; bitpos: [13:0]; default: 0;
* Configures command 0. * Configures commands 0~7.
* It consists of three parts: * It consists of three parts:
* op_code is the command * op_code is the command
* 0: RSTART * 6: RSTART
* 1: WRITE * 1: WRITE
* 2: READ * 3: READ
* 3: STOP * 2: STOP
* 4: END. * 4: END.
* Byte_num represents the number of bytes that need to be sent or received. * Byte_num represents the number of bytes that need to be sent or received.
* ack_check_en, ack_exp, and ack are used to control the ACK bit. See I2C cmd * ack_check_en, ack_exp, and ack are used to control the ACK bit. See I2C cmd
* structure for more information. * structure for more information.
* "
*/ */
uint32_t command0:14; uint32_t command:14;
uint32_t reserved_14:17; uint32_t reserved_14:17;
/** command0_done : R/W/SS; bitpos: [31]; default: 0; /** command_done : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command 0 is done in I2C Master mode. * Represents whether command is done in I2C Master mode.
* 0: Not done * 0: Not done
* 1: Done * 1: Done
*/ */
uint32_t command0_done:1; uint32_t command_done:1;
}; };
uint32_t val; uint32_t val;
} i2c_comd0_reg_t; } i2c_comd_reg_t;
/** Type of comd1 register
* I2C command register 1
*/
typedef union {
struct {
/** command1 : R/W; bitpos: [13:0]; default: 0;
* Configures command 1. See details in I2C_COMD0_REG [13:0].
*/
uint32_t command1:14;
uint32_t reserved_14:17;
/** command1_done : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command 1 is done in I2C Master mode.
* 0: Not done
* 1: Done
*/
uint32_t command1_done:1;
};
uint32_t val;
} i2c_comd1_reg_t;
/** Type of comd2 register
* I2C command register 2
*/
typedef union {
struct {
/** command2 : R/W; bitpos: [13:0]; default: 0;
* Configures command 2. See details in I2C_COMD0_REG [13:0].
*/
uint32_t command2:14;
uint32_t reserved_14:17;
/** command2_done : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command 2 is done in I2C Master mode.
* 0: Not done
* 1: Done
*/
uint32_t command2_done:1;
};
uint32_t val;
} i2c_comd2_reg_t;
/** Type of comd3 register
* I2C command register 3
*/
typedef union {
struct {
/** command3 : R/W; bitpos: [13:0]; default: 0;
* Configures command 3. See details in I2C_COMD0_REG [13:0].
*/
uint32_t command3:14;
uint32_t reserved_14:17;
/** command3_done : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command 3 is done in I2C Master mode.
* 0: Not done
* 1: Done
*/
uint32_t command3_done:1;
};
uint32_t val;
} i2c_comd3_reg_t;
/** Type of comd4 register
* I2C command register 4
*/
typedef union {
struct {
/** command4 : R/W; bitpos: [13:0]; default: 0;
* Configures command 4. See details in I2C_COMD0_REG [13:0].
*/
uint32_t command4:14;
uint32_t reserved_14:17;
/** command4_done : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command 4 is done in I2C Master mode.
* 0: Not done
* 1: Done
*/
uint32_t command4_done:1;
};
uint32_t val;
} i2c_comd4_reg_t;
/** Type of comd5 register
* I2C command register 5
*/
typedef union {
struct {
/** command5 : R/W; bitpos: [13:0]; default: 0;
* Configures command 5. See details in I2C_COMD0_REG [13:0].
*/
uint32_t command5:14;
uint32_t reserved_14:17;
/** command5_done : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command 5 is done in I2C Master mode.
* 0: Not done
* 1: Done
*/
uint32_t command5_done:1;
};
uint32_t val;
} i2c_comd5_reg_t;
/** Type of comd6 register
* I2C command register 6
*/
typedef union {
struct {
/** command6 : R/W; bitpos: [13:0]; default: 0;
* Configures command 6. See details in I2C_COMD0_REG [13:0].
*/
uint32_t command6:14;
uint32_t reserved_14:17;
/** command6_done : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command 6 is done in I2C Master mode.
* 0: Not done
* 1: Done
*/
uint32_t command6_done:1;
};
uint32_t val;
} i2c_comd6_reg_t;
/** Type of comd7 register
* I2C command register 7
*/
typedef union {
struct {
/** command7 : R/W; bitpos: [13:0]; default: 0;
* Configures command 7. See details in I2C_COMD0_REG [13:0].
*/
uint32_t command7:14;
uint32_t reserved_14:17;
/** command7_done : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command 7 is done in I2C Master mode.
* 0: Not done
* 1: Done
*/
uint32_t command7_done:1;
};
uint32_t val;
} i2c_comd7_reg_t;
/** Group: Version register */ /** Group: Version register */
@@ -1203,14 +1062,7 @@ typedef struct {
volatile i2c_scl_stop_setup_reg_t scl_stop_setup; volatile i2c_scl_stop_setup_reg_t scl_stop_setup;
volatile i2c_filter_cfg_reg_t filter_cfg; volatile i2c_filter_cfg_reg_t filter_cfg;
uint32_t reserved_054; uint32_t reserved_054;
volatile i2c_comd0_reg_t comd0; volatile i2c_comd_reg_t command[8];
volatile i2c_comd1_reg_t comd1;
volatile i2c_comd2_reg_t comd2;
volatile i2c_comd3_reg_t comd3;
volatile i2c_comd4_reg_t comd4;
volatile i2c_comd5_reg_t comd5;
volatile i2c_comd6_reg_t comd6;
volatile i2c_comd7_reg_t comd7;
volatile i2c_scl_st_time_out_reg_t scl_st_time_out; volatile i2c_scl_st_time_out_reg_t scl_st_time_out;
volatile i2c_scl_main_st_time_out_reg_t scl_main_st_time_out; volatile i2c_scl_main_st_time_out_reg_t scl_main_st_time_out;
volatile i2c_scl_sp_conf_reg_t scl_sp_conf; volatile i2c_scl_sp_conf_reg_t scl_sp_conf;
@@ -1218,14 +1070,16 @@ typedef struct {
uint32_t reserved_088[28]; uint32_t reserved_088[28];
volatile i2c_date_reg_t date; volatile i2c_date_reg_t date;
uint32_t reserved_0fc; uint32_t reserved_0fc;
volatile i2c_txfifo_start_addr_reg_t txfifo_start_addr; volatile uint32_t txfifo_mem[32];
uint32_t reserved_104[31]; volatile uint32_t rxfifo_mem[32];
volatile i2c_rxfifo_start_addr_reg_t rxfifo_start_addr;
} i2c_dev_t; } i2c_dev_t;
extern i2c_dev_t I2C0;
extern i2c_dev_t I2C1;
extern i2c_dev_t LP_I2C;
#ifndef __cplusplus #ifndef __cplusplus
_Static_assert(sizeof(i2c_dev_t) == 0x184, "Invalid size of i2c_dev_t structure"); _Static_assert(sizeof(i2c_dev_t) == 0x200, "Invalid size of i2c_dev_t structure");
#endif #endif
#ifdef __cplusplus #ifdef __cplusplus
components/soc/esp32s31/register/soc/lp_i2c_ext_reg.h → components/soc/esp32s31/register/soc/lp_i2c_reg.h
View File
components/soc/esp32s31/register/soc/lp_i2c_ext_struct.h → components/soc/esp32s31/register/soc/lp_i2c_struct.h
+25 -168
View File
@@ -1,5 +1,5 @@
/** /**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 OR MIT * SPDX-License-Identifier: Apache-2.0 OR MIT
*/ */
@@ -762,173 +762,35 @@ typedef union {
/** Group: Command registers */ /** Group: Command registers */
/** Type of comd0 register /** Type of comd0~7 register
* I2C command register 0 * I2C command register 0~7
*/ */
typedef union { typedef union {
struct { struct {
/** command0 : R/W; bitpos: [13:0]; default: 0; /** command : R/W; bitpos: [13:0]; default: 0;
* This is the content of command 0. It consists of three parts: op_code is the * Configures command 0.
* command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the * It consists of three parts:
* number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are * op_code is the command
* used to control the ACK bit. See I2C cmd structure for moreInformation. * 0: RSTART
* 1: WRITE
* 2: READ
* 3: STOP
* 4: END.
* Byte_num represents the number of bytes that need to be sent or received.
* ack_check_en, ack_exp, and ack are used to control the ACK bit. See I2C cmd
* structure for more information.
*/ */
uint32_t command0:14; uint32_t command:14;
uint32_t reserved_14:17; uint32_t reserved_14:17;
/** command0_done : R/W/SS; bitpos: [31]; default: 0; /** command_done : R/W/SS; bitpos: [31]; default: 0;
* When command 0 is done in I2C Master mode, this bit changes to highlevel. * Represents whether command is done in I2C Master mode.
* 0: Not done
* 1: Done
*/ */
uint32_t command0_done:1; uint32_t command_done:1;
}; };
uint32_t val; uint32_t val;
} i2c_comd0_reg_t; } i2c_comd_reg_t;
/** Type of comd1 register
* I2C command register 1
*/
typedef union {
struct {
/** command1 : R/W; bitpos: [13:0]; default: 0;
* This is the content of command 1. It consists of three parts: op_code is the
* command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the
* number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are
* used to control the ACK bit. See I2C cmd structure for moreInformation.
*/
uint32_t command1:14;
uint32_t reserved_14:17;
/** command1_done : R/W/SS; bitpos: [31]; default: 0;
* When command 1 is done in I2C Master mode, this bit changes to highlevel.
*/
uint32_t command1_done:1;
};
uint32_t val;
} i2c_comd1_reg_t;
/** Type of comd2 register
* I2C command register 2
*/
typedef union {
struct {
/** command2 : R/W; bitpos: [13:0]; default: 0;
* This is the content of command 2. It consists of three parts: op_code is the
* command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the
* number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are
* used to control the ACK bit. See I2C cmd structure for moreInformation.
*/
uint32_t command2:14;
uint32_t reserved_14:17;
/** command2_done : R/W/SS; bitpos: [31]; default: 0;
* When command 2 is done in I2C Master mode, this bit changes to highLevel.
*/
uint32_t command2_done:1;
};
uint32_t val;
} i2c_comd2_reg_t;
/** Type of comd3 register
* I2C command register 3
*/
typedef union {
struct {
/** command3 : R/W; bitpos: [13:0]; default: 0;
* This is the content of command 3. It consists of three parts: op_code is the
* command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the
* number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are
* used to control the ACK bit. See I2C cmd structure for moreInformation.
*/
uint32_t command3:14;
uint32_t reserved_14:17;
/** command3_done : R/W/SS; bitpos: [31]; default: 0;
* When command 3 is done in I2C Master mode, this bit changes to highlevel.
*/
uint32_t command3_done:1;
};
uint32_t val;
} i2c_comd3_reg_t;
/** Type of comd4 register
* I2C command register 4
*/
typedef union {
struct {
/** command4 : R/W; bitpos: [13:0]; default: 0;
* This is the content of command 4. It consists of three parts: op_code is the
* command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the
* number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are
* used to control the ACK bit. See I2C cmd structure for moreInformation.
*/
uint32_t command4:14;
uint32_t reserved_14:17;
/** command4_done : R/W/SS; bitpos: [31]; default: 0;
* When command 4 is done in I2C Master mode, this bit changes to highlevel.
*/
uint32_t command4_done:1;
};
uint32_t val;
} i2c_comd4_reg_t;
/** Type of comd5 register
* I2C command register 5
*/
typedef union {
struct {
/** command5 : R/W; bitpos: [13:0]; default: 0;
* This is the content of command 5. It consists of three parts:op_code is the
* command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the
* number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are
* used to control the ACK bit. See I2C cmd structure for moreInformation.
*/
uint32_t command5:14;
uint32_t reserved_14:17;
/** command5_done : R/W/SS; bitpos: [31]; default: 0;
* When command 5 is done in I2C Master mode, this bit changes to high level.
*/
uint32_t command5_done:1;
};
uint32_t val;
} i2c_comd5_reg_t;
/** Type of comd6 register
* I2C command register 6
*/
typedef union {
struct {
/** command6 : R/W; bitpos: [13:0]; default: 0;
* This is the content of command 6. It consists of three parts: op_code is the
* command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the
* number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are
* used to control the ACK bit. See I2C cmd structure for moreInformation.
*/
uint32_t command6:14;
uint32_t reserved_14:17;
/** command6_done : R/W/SS; bitpos: [31]; default: 0;
* When command 6 is done in I2C Master mode, this bit changes to high level.
*/
uint32_t command6_done:1;
};
uint32_t val;
} i2c_comd6_reg_t;
/** Type of comd7 register
* I2C command register 7
*/
typedef union {
struct {
/** command7 : R/W; bitpos: [13:0]; default: 0;
* This is the content of command 7. It consists of three parts: op_code is the
* command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the
* number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are
* used to control the ACK bit. See I2C cmd structure for moreInformation.
*/
uint32_t command7:14;
uint32_t reserved_14:17;
/** command7_done : R/W/SS; bitpos: [31]; default: 0;
* When command 7 is done in I2C Master mode, this bit changes to high level.
*/
uint32_t command7_done:1;
};
uint32_t val;
} i2c_comd7_reg_t;
/** Group: Version register */ /** Group: Version register */
@@ -997,14 +859,7 @@ typedef struct {
volatile i2c_scl_stop_setup_reg_t scl_stop_setup; volatile i2c_scl_stop_setup_reg_t scl_stop_setup;
volatile i2c_filter_cfg_reg_t filter_cfg; volatile i2c_filter_cfg_reg_t filter_cfg;
volatile i2c_clk_conf_reg_t clk_conf; volatile i2c_clk_conf_reg_t clk_conf;
volatile i2c_comd0_reg_t comd0; volatile i2c_comd_reg_t command[8];
volatile i2c_comd1_reg_t comd1;
volatile i2c_comd2_reg_t comd2;
volatile i2c_comd3_reg_t comd3;
volatile i2c_comd4_reg_t comd4;
volatile i2c_comd5_reg_t comd5;
volatile i2c_comd6_reg_t comd6;
volatile i2c_comd7_reg_t comd7;
volatile i2c_scl_st_time_out_reg_t scl_st_time_out; volatile i2c_scl_st_time_out_reg_t scl_st_time_out;
volatile i2c_scl_main_st_time_out_reg_t scl_main_st_time_out; volatile i2c_scl_main_st_time_out_reg_t scl_main_st_time_out;
volatile i2c_scl_sp_conf_reg_t scl_sp_conf; volatile i2c_scl_sp_conf_reg_t scl_sp_conf;
@@ -1017,6 +872,8 @@ typedef struct {
} i2c_dev_t; } i2c_dev_t;
extern i2c_dev_t LP_I2C;
#ifndef __cplusplus #ifndef __cplusplus
_Static_assert(sizeof(i2c_dev_t) == 0x184, "Invalid size of i2c_dev_t structure"); _Static_assert(sizeof(i2c_dev_t) == 0x184, "Invalid size of i2c_dev_t structure");
#endif #endif
examples/peripherals/i2c/i2c_basic/README.md
+2 -2
View File
@@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | | Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | | ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- |
# Basic I2C Master Example # Basic I2C Master Example
examples/peripherals/i2c/i2c_eeprom/README.md
+2 -2
View File
@@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | | Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | | ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- |
# I2C EEPROM example # I2C EEPROM example
examples/peripherals/i2c/i2c_tools/README.md
+2 -2
View File
@@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | | Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | | ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- |
# I2C Tools Example # I2C Tools Example
examples/peripherals/i2c/i2c_u8g2/README.md
+2 -2
View File
@@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | | Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | | ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- |
# I2C U8G2 Display Demo # I2C U8G2 Display Demo
examples/peripherals/lcd/i2c_oled/README.md
+2 -2
View File
@@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | | Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | | ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- |
# I2C OLED example # I2C OLED example