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feat(ulp): add support for ulp on esp32s31

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This commit is contained in:
Marius Vikhammer
2026-04-01 10:43:34 +08:00
parent dfc5bbb58c
commit 10637dbf5e
51 changed files with 536 additions and 101 deletions
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examples/system/ulp/.build-test-rules.yml
+5 -3
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@@ -34,7 +34,7 @@ examples/system/ulp/lp_core/gpio_intr_pulse_counter:
examples/system/ulp/lp_core/gpio_wakeup:
enable:
- if: (SOC_LP_CORE_SUPPORTED == 1) and (SOC_RTCIO_PIN_COUNT > 0)
- if: (SOC_LP_CORE_SUPPORTED == 1) and (SOC_RTCIO_PIN_COUNT > 0) and (SOC_DEEP_SLEEP_SUPPORTED == 1)
<<: *ulp_default_depends
depends_components+:
- esp_driver_gpio
@@ -61,14 +61,16 @@ examples/system/ulp/lp_core/lp_adc:
examples/system/ulp/lp_core/lp_i2c:
enable:
- if: SOC_LP_I2C_SUPPORTED == 1 and SOC_DEEP_SLEEP_SUPPORTED == 1
- if: SOC_LP_CORE_SUPPORT_I2C == 1 and SOC_DEEP_SLEEP_SUPPORTED == 1
<<: *ulp_default_depends
depends_components+:
- esp_hal_i2c
examples/system/ulp/lp_core/lp_mailbox:
enable:
- if: SOC_LP_CORE_SUPPORTED == 1
- if: SOC_LP_CORE_SUPPORTED == 1 and IDF_TARGET not in ["esp32s31"]
temporary: true
reason: ESP32-S31 not supported yet # TODO: [ESP32S31] IDF-14637
<<: *ulp_default_depends
examples/system/ulp/lp_core/lp_spi:
examples/system/ulp/lp_core/build_system/README.md
+2 -2
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@@ -1,5 +1,5 @@
| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-P4 |
| ----------------- | -------- | -------- | -------- |
| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-P4 | ESP32-S31 |
| ----------------- | -------- | -------- | -------- | --------- |
# LP Core Build System Custom Modification Example:
examples/system/ulp/lp_core/build_system/pytest_lp_core_build_sys.py
+1 -1
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@@ -6,6 +6,6 @@ from pytest_embedded_idf.utils import idf_parametrize
@pytest.mark.generic
@idf_parametrize('target', ['esp32c5', 'esp32c6', 'esp32p4'], indirect=['target'])
@idf_parametrize('target', ['esp32c5', 'esp32c6', 'esp32p4', 'esp32s31'], indirect=['target'])
def test_lp_core_build_sys(dut: IdfDut) -> None:
dut.expect('Sum calculated by ULP using external library func: 11')
examples/system/ulp/lp_core/debugging/README.md
+2 -2
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@@ -1,5 +1,5 @@
| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-P4 |
| ----------------- | -------- | -------- | -------- |
| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-P4 | ESP32-S31 |
| ----------------- | -------- | -------- | -------- | --------- |
# LP Core Debugging Example
examples/system/ulp/lp_core/inter_cpu_critical_section/README.md
+2 -2
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@@ -1,5 +1,5 @@
| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-P4 |
| ----------------- | -------- | -------- | -------- |
| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-P4 | ESP32-S31 |
| ----------------- | -------- | -------- | -------- | --------- |
# LP Core simple example with inter-CPU critical section:
examples/system/ulp/lp_core/inter_cpu_critical_section/pytest_lp_core_critical_section.py
+1 -1
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@@ -15,7 +15,7 @@ def test_lp_core_critical_section_main_1_task(dut: Dut) -> None:
@pytest.mark.generic
@idf_parametrize('target', ['esp32p4'], indirect=['target'])
@idf_parametrize('target', ['esp32p4', 'esp32s31'], indirect=['target'])
def test_lp_core_critical_section_main_2_tasks(dut: Dut) -> None:
dut.expect("LP CPU's increment starts, shared counter = 0")
dut.expect(r'core 0 started, cnt = \d+')
examples/system/ulp/lp_core/interrupt/README.md
+2 -2
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@@ -1,5 +1,5 @@
| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-P4 |
| ----------------- | -------- | -------- | -------- |
| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-P4 | ESP32-S31 |
| ----------------- | -------- | -------- | -------- | --------- |
# LP-Core example with interrupt triggered from HP-Core:
examples/system/ulp/lp_core/interrupt/pytest_lp_core_intr.py
+1 -1
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@@ -6,6 +6,6 @@ from pytest_embedded_idf.utils import idf_parametrize
@pytest.mark.generic
@idf_parametrize('target', ['esp32c5', 'esp32c6', 'esp32p4'], indirect=['target'])
@idf_parametrize('target', ['esp32c5', 'esp32c6', 'esp32p4', 'esp32s31'], indirect=['target'])
def test_lp_core_intr(dut: Dut) -> None:
dut.expect('Triggered 10 interrupts on the LP-Core, LP-Core received 10 interrupts')
examples/system/ulp/lp_core/lp_mailbox/pytest_lp_mailbox.py
+3
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@@ -8,6 +8,9 @@ from pytest_embedded_idf.utils import soc_filtered_targets
@pytest.mark.generic
@idf_parametrize('target', soc_filtered_targets('SOC_LP_CORE_SUPPORTED == 1'), indirect=['target'])
@pytest.mark.temp_skip_ci(
targets=['esp32s31'], reason='s31 bringup on this module is not done, TODO: [ESP32S31] IDF-14637'
)
def test_lp_mailbox(dut: Dut) -> None:
# Wait for LP core to be loaded and running
dut.expect_exact('LP Mailbox initialized successfully')
examples/system/ulp/lp_core/lp_timer_interrupt/README.md
+2 -2
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@@ -1,5 +1,5 @@
| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-P4 |
| ----------------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- |
# LP-Core example with interrupt triggered from LP Timer
examples/system/ulp/ulp_fsm/ulp_adc/README.md
+1 -1
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@@ -9,7 +9,7 @@ ULP program periodically measures the input voltage on ADC_CHANNEL_6 (GPIO34 on
By default, thresholds are set to 1.35V and 1.75V, approximately.
GPIO15 is connected to ground to supress output from ROM bootloader.
GPIO15 is connected to ground to suppress output from ROM bootloader.
Average current drawn by the ESP32 in this example (with the default 4x averaging) depending on the measurement frequency is as follows:
examples/system/ulp/ulp_riscv/i2c/README.md
+2 -2
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@@ -54,7 +54,7 @@ Reading initial uncompensated temperature and pressure data ...
Uncompensated Temperature = 22865
Uncompensated Pressure = 41768
Real Temperature = 24.900000 deg celcius
Real Temperature = 24.900000 deg celsius
Real Pressure = 990.640000 hPa
Entering in deep sleep
@@ -85,7 +85,7 @@ mb = -32768
mc = -11786
md = 2746
New Real Temperature = 24.900000 deg celcius
New Real Temperature = 24.900000 deg celsius
New Real Pressure = 990.550000 hPa
Entering in deep sleep
```
examples/system/ulp/ulp_riscv/interrupts/README.md
+1 -1
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@@ -8,7 +8,7 @@ This example demonstrates how the ULP-RISC-V coprocessor can register and handle
- RTC IO triggered interrupts
The example keeps a count of the software interrupts triggered on the ULP RISC-V core and wakes up the main processor from deep sleep after a certain threshold.
Additionaly, it wakes up the main processor from deep sleep when a button is pressed and the GPIO interrupt is triggered.
Additionally, it wakes up the main processor from deep sleep when a button is pressed and the GPIO interrupt is triggered.
## How to use example