mirror of
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Merge branch 'feature/ulp_esp32s31' into 'master'
feat(ulp): add support for ulp on esp32s31 Closes IDF-14640 See merge request espressif/esp-idf!47268
This commit is contained in:
Marius Vikhammer
@@ -7,4 +7,12 @@ INPUT += \
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$(PROJECT_PATH)/components/esp_driver_touch_sens/include/driver/touch_sens.h \
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$(PROJECT_PATH)/components/esp_driver_touch_sens/include/driver/touch_sens_types.h\
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$(PROJECT_PATH)/components/esp_phy/include/esp_phy_init.h \
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$(PROJECT_PATH)/components/esp_phy/include/esp_phy_cert_test.h
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$(PROJECT_PATH)/components/esp_phy/include/esp_phy_cert_test.h \
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$(PROJECT_PATH)/components/ulp/lp_core/include/lp_core_etm.h \
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$(PROJECT_PATH)/components/ulp/lp_core/include/ulp_lp_core.h \
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$(PROJECT_PATH)/components/ulp/lp_core/shared/include/ulp_lp_core_lp_uart_shared.h \
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$(PROJECT_PATH)/components/ulp/lp_core/lp_core/include/ulp_lp_core_gpio.h \
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$(PROJECT_PATH)/components/ulp/lp_core/lp_core/include/ulp_lp_core_print.h \
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$(PROJECT_PATH)/components/ulp/lp_core/lp_core/include/ulp_lp_core_utils.h \
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$(PROJECT_PATH)/components/ulp/lp_core/lp_core/include/ulp_lp_core_interrupts.h \
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$(PROJECT_PATH)/components/ulp/ulp_common/include/ulp_common.h \
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@@ -234,8 +234,8 @@ To enhance the capabilities of the ULP LP core coprocessor, it has access to per
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.. list::
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* LP IO
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* LP I2C
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* LP UART
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:SOC_LP_CORE_SUPPORT_I2C: * LP I2C
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:SOC_ULP_LP_UART_SUPPORTED: * LP UART
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:SOC_LP_SPI_SUPPORTED: * LP SPI
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:SOC_LP_MAILBOX_SUPPORTED: * LP Mailbox
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@@ -277,7 +277,7 @@ In addition to configuring the interrupt related registers for the interrupt sou
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ULP LP Core Clock Configuration
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-------------------------------
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{IDF_TARGET_XTAL_FREQ:default="Not updated", esp32c5="48 MHz", esp32p4="40 MHz"}
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{IDF_TARGET_XTAL_FREQ:default="Not updated", esp32c5="48 MHz", esp32p4="40 MHz", esp32s31="40 MHz"}
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The ULP LP Core clock source is based on the system clock ``LP_FAST_CLK``, see `TRM <{IDF_TARGET_TRM_EN_URL}>`__ > ``Reset and Clock`` for more details.
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@@ -285,7 +285,7 @@ The ULP LP Core clock source is based on the system clock ``LP_FAST_CLK``, see `
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On {IDF_TARGET_NAME}, ``LP_FAST_CLK`` supports using the external {IDF_TARGET_XTAL_FREQ} crystal (XTAL) as its clock source. This allows the ULP LP Core to run at a higher frequency than with the default ``RTC_FAST_CLOCK``, which runs at around 20 MHz. However, there is a trade-off: this clock is normally powered down during sleep to reduce power consumption, but if XTAL is selected as the source, it will remain powered up during sleep, which increases power consumption. If you only plan to use the LP Core as a coprocessor while the HP Core is active, then selecting XTAL can enhance both the performance and frequency stability of the LP Core.
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To enable this feature, set :ref:`CONFIG_RTC_FAST_CLK_SRC` to ``CONFIG_RTC_FAST_CLK_SRC_XTAL``.
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To enable this feature, set ``CONFIG_RTC_FAST_CLK_SRC`` to ``CONFIG_RTC_FAST_CLK_SRC_XTAL``.
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Debugging ULP LP-Core Applications
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@@ -293,13 +293,17 @@ Debugging ULP LP-Core Applications
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When programming the LP core, it can sometimes be challenging to figure out why the program is not behaving as expected. Here are some strategies to help you debug your LP core program:
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* Use the LP UART to print: the LP core has access to the LP UART peripheral, which can be used for printing information independently of the main CPU sleep state. See :example:`system/ulp/lp_core/lp_uart/lp_uart_print` for an example of how to use this driver.
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.. only:: SOC_ULP_LP_UART_SUPPORTED
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* Use the LP UART to print: the LP core has access to the LP UART peripheral, which can be used for printing information independently of the main CPU sleep state. See :example:`system/ulp/lp_core/lp_uart/lp_uart_print` for an example of how to use this driver.
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* Routing :cpp:func:`lp_core_printf` to the HP-Core console UART with :ref:`CONFIG_ULP_HP_UART_CONSOLE_PRINT`. This allows you to easily print LP core information to the already connected HP-Core console UART. The drawback of this approach is that it requires the main CPU to be awake and since there is no synchronization between the LP and HP cores, the output may be interleaved.
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* Share program state through shared variables: as described in :ref:`ulp-lp-core-access-variables`, both the main CPU and the ULP core can easily access global variables in RTC memory. Writing state information to such a variable from the ULP and reading it from the main CPU can help you discern what is happening on the ULP core. The downside of this approach is that it requires the main CPU to be awake, which will not always be the case. Keeping the main CPU awake might even, in some cases, mask problems, as some issues may only occur when certain power domains are powered down.
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* Panic handler: the LP core has a panic handler that can dump the state of the LP core registers by the LP UART when an exception is detected. To enable the panic handler, set the :ref:`CONFIG_ULP_PANIC_OUTPUT_ENABLE` option to ``y``. This option can be kept disabled to reduce LP-RAM usage by the LP core application. To recover a backtrace from the panic dump, it is possible to use ``idf.py monitor``.
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.. only:: SOC_ULP_LP_UART_SUPPORTED
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* Panic handler: the LP core has a panic handler that can dump the state of the LP core registers by the LP UART when an exception is detected. To enable the panic handler, set the :ref:`CONFIG_ULP_PANIC_OUTPUT_ENABLE` option to ``y``. This option can be kept disabled to reduce LP-RAM usage by the LP core application. To recover a backtrace from the panic dump, it is possible to use ``idf.py monitor``.
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.. warning::
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@@ -358,7 +362,7 @@ LP Core Debugging Specifics
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.. list::
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#. For convenient debugging, you may need to add ``-O0`` compile option for ULP app in its ``CMakeLists.txt``. See :example:`system/ulp/lp_core/debugging/` on how to do this.
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:not esp32p4: #. LP core supports limited set of HW exceptions, so, for example, writing at address `0x0` will not cause a panic as it would be for the code running on HP core. This can be overcome to some extent by enabling undefined behavior sanitizer for LP core application, so `ubsan` can help to catch some errors. But note that it will increase code size significantly and it can happen that application won't fit into RTC RAM. To enable `ubsan` for ULP app, add ``-fsanitize=undefined -fno-sanitize=shift-base`` compile option to its ``CMakeLists.txt``. See :example:`system/ulp/lp_core/debugging/` on how to do this.
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:not esp32p4 and not esp32s31: #. LP core supports limited set of HW exceptions, so, for example, writing at address `0x0` will not cause a panic as it would be for the code running on HP core. This can be overcome to some extent by enabling undefined behavior sanitizer for LP core application, so `ubsan` can help to catch some errors. But note that it will increase code size significantly and it can happen that application won't fit into RTC RAM. To enable `ubsan` for ULP app, add ``-fsanitize=undefined -fno-sanitize=shift-base`` compile option to its ``CMakeLists.txt``. See :example:`system/ulp/lp_core/debugging/` on how to do this.
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#. To be able to debug program running on LP core, debugging information and symbols need to be loaded to GDB. It can be done via GDB command line or in ``gdbinit`` file. See section above.
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#. Upon startup, LP core application is loaded into RAM, so all SW breakpoints set before that moment will get overwritten. The best moment to set breakpoints for LP core application is to do this when LP core program reaches `main` function.
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#. When using IDEs, it may lack support for configuring breakpoint actions or commands shown in ``gdbinit`` above. Consequently, you have to preset all breakpoints before debug session start and disable all of them except for ``main``. When program stops at ``main``, enable the remaining breakpoints and resume execution manually.
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@@ -388,11 +392,11 @@ Application Examples
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.. list::
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- :example:`system/ulp/lp_core/gpio` polls GPIO while main CPU is in Deep-sleep.
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:esp32c6: - :example:`system/ulp/lp_core/lp_i2c` reads external I2C ambient light sensor (BH1750) while the main CPU is in Deep-sleep and wakes up the main CPU once a threshold is met.
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- :example:`system/ulp/lp_core/lp_uart/lp_uart_echo` reads data written to a serial console and echoes it back. This example demonstrates the usage of the LP UART driver running on the LP core.
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- :example:`system/ulp/lp_core/lp_uart/lp_uart_print` shows how to print various statements from a program running on the LP core.
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- :example:`system/ulp/lp_core/lp_uart/lp_uart_char_seq_wakeup` shows how to trigger a wakeup using the LP UART specific character sequence wakeup mode.
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- :example:`system/ulp/lp_core/lp_mailbox` shows how to use the mailbox for both synchronous and asynchronous communication between the HP and LP cores. Depending on the target, the implementation may use the hardware mailbox controller (if available) or a software-only implementation using interrupts.
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:SOC_LP_CORE_SUPPORT_I2C: - :example:`system/ulp/lp_core/lp_i2c` reads external I2C ambient light sensor (BH1750) while the main CPU is in Deep-sleep and wakes up the main CPU once a threshold is met.
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:SOC_ULP_LP_UART_SUPPORTED: - :example:`system/ulp/lp_core/lp_uart/lp_uart_echo` reads data written to a serial console and echoes it back. This example demonstrates the usage of the LP UART driver running on the LP core.
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:SOC_ULP_LP_UART_SUPPORTED: - :example:`system/ulp/lp_core/lp_uart/lp_uart_print` shows how to print various statements from a program running on the LP core.
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:SOC_ULP_LP_UART_SUPPORTED: - :example:`system/ulp/lp_core/lp_uart/lp_uart_char_seq_wakeup` shows how to trigger a wakeup using the LP UART specific character sequence wakeup mode.
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:SOC_LP_MAILBOX_SUPPORTED: - :example:`system/ulp/lp_core/lp_mailbox` shows how to use the mailbox for both synchronous and asynchronous communication between the HP and LP cores. Depending on the target, the implementation may use the hardware mailbox controller (if available) or a software-only implementation using interrupts.
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- :example:`system/ulp/lp_core/interrupt` shows how to register an interrupt handler on the LP core to receive an interrupt triggered by the main CPU.
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- :example:`system/ulp/lp_core/gpio_intr_pulse_counter` shows how to use GPIO interrupts to count pulses while the main CPU is in Deep-sleep mode.
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- :example:`system/ulp/lp_core/build_system/` demonstrates how to include custom ``CMakeLists.txt`` file for the ULP app.
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@@ -405,8 +409,14 @@ Main CPU API Reference
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~~~~~~~~~~~~~~~~~~~~~~
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.. include-build-file:: inc/ulp_lp_core.inc
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.. include-build-file:: inc/lp_core_i2c.inc
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.. include-build-file:: inc/lp_core_uart.inc
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.. only:: SOC_LP_CORE_SUPPORT_I2C
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.. include-build-file:: inc/lp_core_i2c.inc
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.. only:: SOC_ULP_LP_UART_SUPPORTED
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.. include-build-file:: inc/lp_core_uart.inc
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.. only:: SOC_LP_SPI_SUPPORTED
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@@ -423,9 +433,19 @@ LP Core API Reference
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.. include-build-file:: inc/ulp_lp_core_utils.inc
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.. include-build-file:: inc/ulp_lp_core_gpio.inc
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.. include-build-file:: inc/ulp_lp_core_i2c.inc
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.. include-build-file:: inc/ulp_lp_core_uart.inc
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.. include-build-file:: inc/ulp_lp_core_mailbox.inc
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.. only:: SOC_LP_CORE_SUPPORT_I2C
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.. include-build-file:: inc/ulp_lp_core_i2c.inc
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.. only:: SOC_ULP_LP_UART_SUPPORTED
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.. include-build-file:: inc/ulp_lp_core_uart.inc
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.. only:: SOC_LP_MAILBOX_SUPPORTED
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.. include-build-file:: inc/ulp_lp_core_mailbox.inc
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.. include-build-file:: inc/ulp_lp_core_print.inc
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.. include-build-file:: inc/ulp_lp_core_interrupts.inc
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@@ -234,8 +234,8 @@ ULP LP 内核支持的外设
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.. list::
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* LP IO
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* LP I2C
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* LP UART
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:SOC_LP_CORE_SUPPORT_I2C: * LP I2C
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:SOC_ULP_LP_UART_SUPPORTED: * LP UART
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:SOC_LP_SPI_SUPPORTED: * LP SPI
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:SOC_LP_MAILBOX_SUPPORTED: * LP 邮箱
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@@ -277,7 +277,7 @@ ULP LP 内核中断
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ULP LP 内核时钟配置
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-------------------
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{IDF_TARGET_XTAL_FREQ:default="未更新", esp32c5="48 MHz", esp32p4="40 MHz"}
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{IDF_TARGET_XTAL_FREQ:default="未更新", esp32c5="48 MHz", esp32p4="40 MHz", esp32s31="40 MHz"}
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ULP LP 内核的时钟源来自系统时钟 ``LP_FAST_CLK``，详情请参见 `技术参考手册 <{IDF_TARGET_TRM_CN_URL}>`__ > ``复位和时钟``。
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@@ -285,7 +285,7 @@ ULP LP 内核的时钟源来自系统时钟 ``LP_FAST_CLK``，详情请参见 `
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在 {IDF_TARGET_NAME} 上，``LP_FAST_CLK`` 支持使用外部 {IDF_TARGET_XTAL_FREQ} 晶振 (XTAL) 作为其时钟源。默认时钟源 ``RTC_FAST_CLOCK`` 的运行频率约为 20 MHz，使用外部晶振时钟后，ULP LP 内核将以更高的频率运行。缺点在于，``LP_FAST_CLK`` 在休眠期间通常会断电以减少功耗，而选择 XTAL 作为时钟源后，休眠期间时钟仍将保持通电，造成功耗增加。因此，如果仅希望在 HP 内核活动时将 LP 内核用作协处理器，则可以使用 XTAL 以提高 LP 内核的性能和频率稳定性。
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要启用此功能，请将 :ref:`CONFIG_RTC_FAST_CLK_SRC` 设置为 ``CONFIG_RTC_FAST_CLK_SRC_XTAL``。
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要启用此功能，请将 ``CONFIG_RTC_FAST_CLK_SRC`` 设置为 ``CONFIG_RTC_FAST_CLK_SRC_XTAL``。
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调试 ULP LP 内核应用程序
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@@ -293,13 +293,17 @@ ULP LP 内核的时钟源来自系统时钟 ``LP_FAST_CLK``，详情请参见 `
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在编程 LP 内核时，有时很难弄清楚程序未按预期运行的原因。请参考以下策略，调试 LP 内核程序：
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* 使用 LP UART 打印：LP 内核可以访问 LP UART 外设，在主 CPU 处于睡眠状态时独立打印信息。有关使用此驱动程序的示例，请参阅 :example:`system/ulp/lp_core/lp_uart/lp_uart_print`。
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.. only:: SOC_ULP_LP_UART_SUPPORTED
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* 使用 LP UART 打印：LP 内核可以访问 LP UART 外设，在主 CPU 处于睡眠状态时独立打印信息。有关使用此驱动程序的示例，请参阅 :example:`system/ulp/lp_core/lp_uart/lp_uart_print`。
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* 通过 :ref:`CONFIG_ULP_HP_UART_CONSOLE_PRINT`，将 :cpp:func:`lp_core_printf` 路由到 HP-Core 控制台 UART，可以轻松地将 LP 内核信息打印到已经连接的 HP-Core 控制台 UART。此方法的缺点是需要主 CPU 处于唤醒状态，并且由于 LP 内核与 HP 内未同步，输出可能会交错。
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* 通过共享变量共享程序状态：如 :ref:`ulp-lp-core-access-variables` 所述，主 CPU 和 ULP 内核都可以轻松访问 RTC 内存中的全局变量。若想了解 ULP 内核的运行状态，可以将状态信息从 ULP 写入变量中，并通过主 CPU 读取信息。这种方法的缺点在于它需要主 CPU 一直处于唤醒状态，而这通常很难实现。另外，若主 CPU 一直处于唤醒状态，可能会掩盖某些问题，因为部分问题只会在特定电源域断电时发生。
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* 紧急处理程序：当检测到异常时，LP 内核的紧急处理程序会把 LP 内核寄存器的状态通过 LP UART 发送出去。将 ``CONFIG_ULP_PANIC_OUTPUT_ENABLE`` 选项设置为 ``y``，可以启用紧急处理程序。禁用此选项将减少 LP 内核应用程序的 LP-RAM 使用量。若想从紧急转储中解析栈回溯，可以使用 ``idf.py monitor``。
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.. only:: SOC_ULP_LP_UART_SUPPORTED
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||||
|
||||
* 紧急处理程序：当检测到异常时，LP 内核的紧急处理程序会把 LP 内核寄存器的状态通过 LP UART 发送出去。将 ``CONFIG_ULP_PANIC_OUTPUT_ENABLE`` 选项设置为 ``y``，可以启用紧急处理程序。禁用此选项将减少 LP 内核应用程序的 LP-RAM 使用量。若想从紧急转储中解析栈回溯，可以使用 ``idf.py monitor``。
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.. warning::
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@@ -358,7 +362,7 @@ LP 内核调试特性
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||||
.. list::
|
||||
|
||||
#. 为了方便调试，请在 ULP 应用的 ``CMakeLists.txt`` 文件中添加 ``-O0`` 编译选项。具体操作步骤请参见 :example:`system/ulp/lp_core/debugging/`。
|
||||
:not esp32p4: #. LP 内核支持的硬件异常类型有限，例如，写入地址 `0x0` 不会像在 HP 内核上一样造成系统崩溃。启用 LP 内核应用程序的未定义行为检测器 (`ubsan`) 可以捕捉一些错误，从而在一定程度上弥补这一限制。但请注意，这将显著增加代码量，可能会导致应用程序超出 RTC RAM 的容量限制。要启用 `ubsan`，请在 ``CMakeLists.txt`` 文件中添加 ``-fsanitize=undefined -fno-sanitize=shift-base`` 编译选项。具体操作步骤请参见 :example:`system/ulp/lp_core/debugging/`。
|
||||
:not esp32p4 and not esp32s31: #. LP 内核支持的硬件异常类型有限，例如，写入地址 `0x0` 不会像在 HP 内核上一样造成系统崩溃。启用 LP 内核应用程序的未定义行为检测器 (`ubsan`) 可以捕捉一些错误，从而在一定程度上弥补这一限制。但请注意，这将显著增加代码量，可能会导致应用程序超出 RTC RAM 的容量限制。要启用 `ubsan`，请在 ``CMakeLists.txt`` 文件中添加 ``-fsanitize=undefined -fno-sanitize=shift-base`` 编译选项。具体操作步骤请参见 :example:`system/ulp/lp_core/debugging/`。
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||||
#. 为了调试运行在 LP 内核上的程序，需要先将调试信息和符号加载到 GDB 中。这可以通过 GDB 命令行或在 ``gdbinit`` 文件中完成。具体操作步骤请参见上文。
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||||
#. LP 内核应用程序会在启时会加载到 RAM 中，在此之前设置的所有软件断点都会被覆盖。设置 LP 内核应用断点的最佳时机是在 LP 内核程序运行至 ``main`` 函数之时。
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||||
#. 使用 IDE 时，可能无法配置上述 ``gdbinit`` 文件中的断点操作或命令。因此，请在调试会话开始前预设并禁用所有断点，只保留 ``main`` 函数处的断点。当程序在 ``main`` 处停止时，手动启用其余断点并恢复执行。
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||||
@@ -388,11 +392,11 @@ LP 内核调试特性
|
||||
.. list::
|
||||
|
||||
- :example:`system/ulp/lp_core/gpio` 展示了 ULP LP 内核协处理器在主 CPU 深度睡眠时轮询 GPIO。
|
||||
:esp32c6: - :example:`system/ulp/lp_core/lp_i2c` 展示了 ULP LP 内核协处理器在主 CPU 深度睡眠时读取外部 I2C 环境光传感器 (BH1750)，并在达到阈值时唤醒主 CPU。
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||||
- :example:`system/ulp/lp_core/lp_uart/lp_uart_echo` 展示了低功耗内核上运行的 LP UART 驱动程序如何读取并回显写入串行控制台的数据。
|
||||
- :example:`system/ulp/lp_core/lp_uart/lp_uart_print` 展示了如何在低功耗内核上使用串口打印功能。
|
||||
- :example:`system/ulp/lp_core/lp_uart/lp_uart_char_seq_wakeup` 展示了如何使用 LP UART 特定字符序列唤醒模式触发唤醒。
|
||||
- :example:`system/ulp/lp_core/lp_mailbox` 展示了如何在 HP 内核和 LP 内核之间使用邮箱进行同步和异步通信。根据目标设备的不同，示例实现可能会使用硬件邮箱控制器（如果可用），或者使用基于中断的纯软件实现。
|
||||
:SOC_LP_CORE_SUPPORT_I2C: - :example:`system/ulp/lp_core/lp_i2c` 展示了 ULP LP 内核协处理器在主 CPU 深度睡眠时读取外部 I2C 环境光传感器 (BH1750)，并在达到阈值时唤醒主 CPU。
|
||||
:SOC_ULP_LP_UART_SUPPORTED: - :example:`system/ulp/lp_core/lp_uart/lp_uart_echo` 展示了低功耗内核上运行的 LP UART 驱动程序如何读取并回显写入串行控制台的数据。
|
||||
:SOC_ULP_LP_UART_SUPPORTED: - :example:`system/ulp/lp_core/lp_uart/lp_uart_print` 展示了如何在低功耗内核上使用串口打印功能。
|
||||
:SOC_ULP_LP_UART_SUPPORTED: - :example:`system/ulp/lp_core/lp_uart/lp_uart_char_seq_wakeup` 展示了如何使用 LP UART 特定字符序列唤醒模式触发唤醒。
|
||||
:SOC_LP_MAILBOX_SUPPORTED: - :example:`system/ulp/lp_core/lp_mailbox` 展示了如何在 HP 内核和 LP 内核之间使用邮箱进行同步和异步通信。根据目标设备的不同，示例实现可能会使用硬件邮箱控制器（如果可用），或者使用基于中断的纯软件实现。
|
||||
- :example:`system/ulp/lp_core/interrupt` 展示了如何在 LP 内核上注册中断处理程序，接收由主 CPU 触发的中断。
|
||||
- :example:`system/ulp/lp_core/gpio_intr_pulse_counter` 展示了如何在主 CPU 处于 Deep-sleep 模式时，使用 GPIO 中断为脉冲计数。
|
||||
- :example:`system/ulp/lp_core/build_system/` 演示了如何为 ULP 应用程序添加自定义的 ``CMakeLists.txt`` 文件。
|
||||
@@ -405,8 +409,14 @@ API 参考
|
||||
~~~~~~~~~~~~~~~
|
||||
|
||||
.. include-build-file:: inc/ulp_lp_core.inc
|
||||
.. include-build-file:: inc/lp_core_i2c.inc
|
||||
.. include-build-file:: inc/lp_core_uart.inc
|
||||
|
||||
.. only:: SOC_LP_CORE_SUPPORT_I2C
|
||||
|
||||
.. include-build-file:: inc/lp_core_i2c.inc
|
||||
|
||||
.. only:: SOC_ULP_LP_UART_SUPPORTED
|
||||
|
||||
.. include-build-file:: inc/lp_core_uart.inc
|
||||
|
||||
.. only:: SOC_LP_SPI_SUPPORTED
|
||||
|
||||
@@ -423,9 +433,19 @@ LP 内核 API 参考
|
||||
|
||||
.. include-build-file:: inc/ulp_lp_core_utils.inc
|
||||
.. include-build-file:: inc/ulp_lp_core_gpio.inc
|
||||
.. include-build-file:: inc/ulp_lp_core_i2c.inc
|
||||
.. include-build-file:: inc/ulp_lp_core_uart.inc
|
||||
.. include-build-file:: inc/ulp_lp_core_mailbox.inc
|
||||
|
||||
.. only:: SOC_LP_CORE_SUPPORT_I2C
|
||||
|
||||
.. include-build-file:: inc/ulp_lp_core_i2c.inc
|
||||
|
||||
.. only:: SOC_ULP_LP_UART_SUPPORTED
|
||||
|
||||
.. include-build-file:: inc/ulp_lp_core_uart.inc
|
||||
|
||||
.. only:: SOC_LP_MAILBOX_SUPPORTED
|
||||
|
||||
.. include-build-file:: inc/ulp_lp_core_mailbox.inc
|
||||
|
||||
.. include-build-file:: inc/ulp_lp_core_print.inc
|
||||
.. include-build-file:: inc/ulp_lp_core_interrupts.inc
|
||||
|
||||
|
||||
Reference in New Issue
Block a user