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fix(mspi): fixed mspi dma burst timing issue

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This commit is contained in:
armando
2026-01-09 10:37:49 +08:00
parent 3a62fdba66
commit 41e854d7df
8 changed files with 71 additions and 13 deletions
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components/esp_mm/esp_cache_msync.c
+1 -1
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
components/esp_mm/include/esp_cache.h
+1 -1
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
components/esp_mm/include/esp_private/esp_cache_private.h
+1 -1
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
components/esp_psram/CMakeLists.txt
+2 -2
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@@ -15,10 +15,10 @@ if(${target} STREQUAL "esp32")
list(APPEND priv_requires bootloader_support esp_driver_spi esp_driver_gpio)
endif()
set(srcs)
set(srcs "system_layer/esp_psram_mspi.c")
if(CONFIG_SPIRAM)
list(APPEND srcs "system_layer/esp_psram.c" "system_layer/esp_psram_mspi.c")
list(APPEND srcs "system_layer/esp_psram.c")
if(${target} STREQUAL "esp32")
list(APPEND srcs "esp32/esp_psram_extram_cache.c"
components/esp_psram/include/esp_private/esp_psram_mspi.h
+16 -1
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -8,12 +8,15 @@
#include <stddef.h>
#include <stdbool.h>
#include "sdkconfig.h"
#include "esp_err.h"
#ifdef __cplusplus
extern "C" {
#endif
#define ESP_PSRAM_MSPI_MB_WORKAROUND (CONFIG_IDF_TARGET_ESP32C5 && CONFIG_ESP32C5_REV_MIN_FULL < 102) || (CONFIG_IDF_TARGET_ESP32C61 && CONFIG_ESP32C61_REV_MIN_FULL < 101)
/**
* @brief Register MSPI PSRAM interrupt
*
@@ -34,6 +37,18 @@ esp_err_t esp_psram_mspi_register_isr(void);
*/
esp_err_t esp_psram_mspi_unregister_isr(void);
/**
* @brief Initialize PSRAM MSPI memory barrier
*
* @return ESP_OK on success, otherwise an error code
*/
esp_err_t esp_psram_mspi_mb_init(void);
/**
* @brief PSRAM MSPI memory barrier
*/
void esp_psram_mspi_mb(void);
#ifdef __cplusplus
}
#endif
components/esp_psram/system_layer/esp_psram.c
+9 -3
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -129,7 +129,7 @@ ESP_SYSTEM_INIT_FN(psram_core_stage_init, CORE, BIT(0), 103)
ret = esp_psram_extram_add_to_heap_allocator();
if (ret != ESP_OK) {
ESP_EARLY_LOGE(TAG, "External RAM could not be added to heap!");
abort();
return ret;
}
#if CONFIG_SPIRAM_USE_MALLOC
heap_caps_malloc_extmem_enable(CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL);
@@ -140,7 +140,13 @@ ESP_SYSTEM_INIT_FN(psram_core_stage_init, CORE, BIT(0), 103)
ret = esp_psram_mspi_register_isr();
if (ret != ESP_OK) {
ESP_EARLY_LOGE(TAG, "Failed to register PSRAM ISR!");
abort();
return ret;
}
ret = esp_psram_mspi_mb_init();
if (ret != ESP_OK) {
ESP_EARLY_LOGE(TAG, "Failed to initialize PSRAM MSPI memory barrier!");
return ret;
}
return ret;
components/esp_psram/system_layer/esp_psram_mspi.c
+40 -3
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -13,13 +13,21 @@
#include "esp_log.h"
#include "esp_check.h"
#include "esp_intr_alloc.h"
#include "esp_cache.h"
#include "esp_heap_caps.h"
#include "hal/mspi_ll.h"
#include "hal/mspi_periph.h"
#include "esp_private/mspi_intr.h"
#include "esp_private/esp_psram_mspi.h"
#if CONFIG_SPIRAM
#if !CONFIG_IDF_TARGET_ESP32 && !CONFIG_IDF_TARGET_ESP32S2
#include "hal/psram_ctrlr_ll.h"
#endif
#endif
__attribute__((unused)) ESP_LOG_ATTR_TAG_DRAM(TAG, "psram_mspi");
#if CONFIG_SPIRAM
#if PSRAM_CTRLR_LL_INTR_EVENT_SUPPORTED
#if CONFIG_ESP_PANIC_HANDLER_IRAM
@@ -30,8 +38,6 @@
#define PSRAM_ISR_FLAGS 0
#endif
ESP_LOG_ATTR_TAG_DRAM(TAG, "psram_mspi");
static void PSRAM_ISR_ATTR mspi_psram_isr_handler(void *arg, uint32_t intr_events)
{
#if PSRAM_CTRLR_LL_PMS_INT_SUPPORTED
@@ -124,3 +130,34 @@ esp_err_t esp_psram_mspi_unregister_isr(void)
return ESP_OK;
}
#endif //#if PSRAM_CTRLR_LL_INTR_EVENT_SUPPORTED
#endif //#if CONFIG_SPIRAM
#if ESP_PSRAM_MSPI_MB_WORKAROUND
static void *s_psram_mb_dummy_cacheline; //dummy cacheline for cache memory barrier
#endif
esp_err_t esp_psram_mspi_mb_init(void)
{
#if ESP_PSRAM_MSPI_MB_WORKAROUND
s_psram_mb_dummy_cacheline = heap_caps_calloc(1, CONFIG_CACHE_L1_CACHE_LINE_SIZE, MALLOC_CAP_SPIRAM | MALLOC_CAP_CACHE_ALIGNED);
if (!s_psram_mb_dummy_cacheline) {
ESP_EARLY_LOGE(TAG, "Failed to allocate dummy cacheline for PSRAM memory barrier!");
}
#endif
return ESP_OK;
}
void IRAM_ATTR esp_psram_mspi_mb(void)
{
#if ESP_PSRAM_MSPI_MB_WORKAROUND
if (!s_psram_mb_dummy_cacheline) {
uint32_t *p = (uint32_t *)s_psram_mb_dummy_cacheline;
*p = (*p + 1) % UINT32_MAX;
__attribute__((unused)) esp_err_t ret = ESP_FAIL;
ret = esp_cache_msync(s_psram_mb_dummy_cacheline, sizeof(uint32_t), ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_UNALIGNED); //malloc is aligned, no need to writeback all
assert(ret == ESP_OK);
asm volatile("fence");
}
#endif
}
components/esp_psram/test_apps/psram/pytest_psram.py
+1 -1
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@@ -1,4 +1,4 @@
# SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
# SPDX-FileCopyrightText: 2021-2026 Espressif Systems (Shanghai) CO LTD
# SPDX-License-Identifier: CC0-1.0
import pytest
from pytest_embedded import Dut