Updates for riscv support

* Target components pull in xtensa component directly
* Use CPU HAL where applicable
* Remove unnecessary xtensa headers
* Compilation changes necessary to support non-xtensa gcc types (ie int32_t/uint32_t is no
  longer signed/unsigned int).

Changes come from internal branch commit a6723fc

Kconfig

@@ -13,6 +13,14 @@ mainmenu "Espressif IoT Development Framework Configuration"
         bool
         option env="IDF_ENV_FPGA"
 
+    config IDF_TARGET_ARCH_RISCV
+        bool
+        default "n"
+
+    config IDF_TARGET_ARCH_XTENSA
+        bool
+        default "n"
+
     config IDF_TARGET
         # This option records the IDF target when sdkconfig is generated the first time.
         # It is not updated if environment variable $IDF_TARGET changes later, and
@@ -24,15 +32,18 @@ mainmenu "Espressif IoT Development Framework Configuration"
     config IDF_TARGET_ESP32
         bool
         default "y" if IDF_TARGET="esp32"
+        select IDF_TARGET_ARCH_XTENSA
 
     config IDF_TARGET_ESP32S2
         bool
         default "y" if IDF_TARGET="esp32s2"
         select FREERTOS_UNICORE
+        select IDF_TARGET_ARCH_XTENSA
 
     config IDF_TARGET_ESP32S3
         bool
         default "y" if IDF_TARGET="esp32s3"
+        select IDF_TARGET_ARCH_XTENSA
 
     choice IDF_TARGET_ESP32S3_BETA_VERSION
         prompt "ESP32-S3 beta version"