Merge branch 'fix/fix_parlio_tx_sample_edge' into 'master'

change(parlio_tx): use shift edge instead sample edge

See merge request espressif/esp-idf!46628

docs/en/api-reference/peripherals/parlio/parlio_tx.rst

@@ -46,7 +46,7 @@ First, we need to create a TX unit instance. The following code shows how to cre
         .output_clk_freq_hz = 10 * 1000 * 1000, // Output clock frequency is 10 MHz
         .trans_queue_depth = 32,                // Transaction queue depth is 32
         .max_transfer_size = 256,               // Maximum transfer size is 256 bytes
-        .sample_edge = PARLIO_SAMPLE_EDGE_NEG,  // Sample data on the falling edge of the clock
+        .shift_edge = PARLIO_SHIFT_EDGE_NEG,    // Shift data on the falling edge of the clock
         .flags = {
             .invert_valid_out = true, // The valid signal is high by default, inverted to simulate the chip select signal CS in QPI timing
         }
@@ -74,7 +74,7 @@ The following are the configuration parameters of the :cpp:type:`parlio_tx_unit_
     -  :cpp:member:`parlio_tx_unit_config_t::trans_queue_depth` The depth of the internal transaction queue. The deeper the queue, the more transactions can be prepared in the pending queue.
     -  :cpp:member:`parlio_tx_unit_config_t::max_transfer_size` The maximum transfer size per transaction (in bytes).
     -  :cpp:member:`parlio_tx_unit_config_t::dma_burst_size` The DMA burst transfer size (in bytes), must be a power of 2.
-    -  :cpp:member:`parlio_tx_unit_config_t::sample_edge` The data sampling edge of the TX unit.
+    -  :cpp:member:`parlio_tx_unit_config_t::shift_edge` The data shift edge of the TX unit.
     -  :cpp:member:`parlio_tx_unit_config_t::bit_pack_order` Sets the order of data bits within a byte (valid only when data width < 8).
     -  :cpp:member:`parlio_tx_unit_config_t::flags` Usually used to fine-tune some behaviors of the driver, including the following options
     -  :cpp:member:`parlio_tx_unit_config_t::flags::invert_valid_out` Determines whether to invert the valid signal before sending it to the GPIO pin.
@@ -216,7 +216,7 @@ The TX unit can choose various clock sources, among which the external clock sou
         .output_clk_freq_hz = 5 * 1000 * 1000, // Output clock frequency is 5 MHz. Note that it cannot exceed the input clock frequency
         .trans_queue_depth = 32,
         .max_transfer_size = 256,
-        .sample_edge = PARLIO_SAMPLE_EDGE_NEG,  // Sample data on the falling edge of the clock
+        .shift_edge = PARLIO_SHIFT_EDGE_NEG,    // Shift data on the falling edge of the clock
     };
     // Create TX unit instance
     ESP_ERROR_CHECK(parlio_new_tx_unit(&config, &tx_unit));
@@ -273,7 +273,7 @@ The waveform of the external clock input is shown below:
             .output_clk_freq_hz = 10 * 1000 * 1000, // Output clock frequency is 10 MHz
             .trans_queue_depth = 32,
             .max_transfer_size = 256,
-            .sample_edge = PARLIO_SAMPLE_EDGE_NEG,  // Sample data on the falling edge of the clock
+            .shift_edge = PARLIO_SHIFT_EDGE_NEG,    // Shift data on the falling edge of the clock
             .flags = {
                 .invert_valid_out = true,  // The valid signal is high by default, inverted to simulate the chip select signal CS in QPI timing
             }

docs/zh_CN/api-reference/peripherals/parlio/parlio_tx.rst

@@ -46,7 +46,7 @@
         .output_clk_freq_hz = 10 * 1000 * 1000, // 输出时钟频率为 10 MHz
         .trans_queue_depth = 32,                // 待处理事务队列深度为 32
         .max_transfer_size = 256,               // 一次传输的最大传输大小为 256 字节
-        .sample_edge = PARLIO_SAMPLE_EDGE_NEG,  // 在时钟下降沿采样数据
+        .shift_edge = PARLIO_SHIFT_EDGE_NEG,    // 在时钟下降沿移位数据
         .flags = {
             .invert_valid_out = true, // 有效信号默认高电平有效，通过反转，我们用来模拟 QPI 的时序中的片选信号 CS
         }
@@ -74,7 +74,7 @@
     -  :cpp:member:`parlio_tx_unit_config_t::trans_queue_depth` 内部事务队列深度。队列越深，在待处理队列中可以准备的事务越多。
     -  :cpp:member:`parlio_tx_unit_config_t::max_transfer_size` 一次传输的最大传输大小（以字节为单位）。
     -  :cpp:member:`parlio_tx_unit_config_t::dma_burst_size` DMA 突发传输大小（以字节为单位），必须为 2 的幂次方。
-    -  :cpp:member:`parlio_tx_unit_config_t::sample_edge`  TX 单元的数据采样边缘。
+    -  :cpp:member:`parlio_tx_unit_config_t::shift_edge`  TX 单元的数据移位边缘。
     -  :cpp:member:`parlio_tx_unit_config_t::bit_pack_order` 设置字节内数据位出现的顺序（仅当数据宽度 < 8 时有效）。
     -  :cpp:member:`parlio_tx_unit_config_t::flags` 通常用来微调驱动的一些行为，包括以下选项
     -  :cpp:member:`parlio_tx_unit_config_t::flags::invert_valid_out` 决定是否在将 TX 单元有效信号发送到 GPIO 管脚前反转信号。
@@ -216,7 +216,7 @@ TX 单元可以选择各种不同的时钟源，其中外部时钟源较为特
         .output_clk_freq_hz = 5 * 1000 * 1000, // 输出时钟频率为 5 MHz。注意，不能超过输入时钟频率
         .trans_queue_depth = 32,
         .max_transfer_size = 256,
-        .sample_edge = PARLIO_SAMPLE_EDGE_NEG,  // 在时钟下降沿采样数据
+        .shift_edge = PARLIO_SHIFT_EDGE_NEG,    // 在时钟下降沿移位数据
     };
     // 创建 TX 单元实例
     ESP_ERROR_CHECK(parlio_new_tx_unit(&config, &tx_unit));
@@ -273,7 +273,7 @@ TX 单元可以选择各种不同的时钟源，其中外部时钟源较为特
             .output_clk_freq_hz = 10 * 1000 * 1000, // 输出时钟频率为 10 MHz
             .trans_queue_depth = 32,
             .max_transfer_size = 256,
-            .sample_edge = PARLIO_SAMPLE_EDGE_NEG,  // 在时钟下降沿采样数据
+            .shift_edge = PARLIO_SHIFT_EDGE_NEG,    // 在时钟下降沿移位数据
             .flags = {
                 .invert_valid_out = true,  // 有效信号默认高电平有效，通过反转，我们用来模拟 QPI 的时序中的片选信号 CS
             }