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docs(esp_eth): added test to verify A/MPLL configuration)
Updated docs to state there could be conflict between PSRAM MPLL configuration and EMAC
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@@ -167,6 +167,13 @@ The Ethernet driver is composed of two parts: MAC and PHY.
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If the RMII clock mode is configured to :cpp:enumerator:`emac_rmii_clock_mode_t::EMAC_CLK_EXT_IN`, {IDF_TARGET_SOC_REF_CLK_IN_GPIO} can be selected as input pin for the ``REF_CLK`` signal via IO_MUX.
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.. only:: esp32p4
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.. warning::
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If the RMII clock mode is configured to :cpp:enumerator:`emac_rmii_clock_mode_t::EMAC_CLK_OUT`, the EMAC derives the 50 MHz RMII reference clock from the MPLL via an integer divider. When PSRAM is also enabled, both peripherals share the MPLL, and PSRAM locks it to a frequency determined by its speed configuration. If PSRAM speed is configured to 80 MHz (:ref:`CONFIG_SPIRAM_SPEED`), the MPLL runs at 320 MHz, and no integer divisor of 320 MHz can produce 50 MHz within the required ±50 ppm tolerance (the closest candidate is 320 / 6 ≈ 53.33 MHz). EMAC initialization will fail in this configuration.
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If you must use 80 MHz PSRAM speed, provide the ``REF_CLK`` from an external source (PHY or oscillator) and configure :cpp:enumerator:`emac_rmii_clock_mode_t::EMAC_CLK_EXT_IN` instead.
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.. only:: not SOC_EMAC_RMII_CLK_OUT_INTERNAL_LOOPBACK
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.. warning::
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@@ -167,6 +167,13 @@
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如果 RMII 时钟模式配置为 :cpp:enumerator:`emac_rmii_clock_mode_t::EMAC_CLK_EXT_IN`,则可以通过 IO_MUX 将 {IDF_TARGET_SOC_REF_CLK_IN_GPIO} 选择为 ``REF_CLK`` 信号的输入管脚。
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.. only:: esp32p4
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.. warning::
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如果 RMII 时钟模式配置为 :cpp:enumerator:`emac_rmii_clock_mode_t::EMAC_CLK_OUT`,EMAC 将通过整数分频器从 MPLL 获取 50 MHz RMII 参考时钟。当同时启用 PSRAM 时,两个外设共享 MPLL,PSRAM 会将 MPLL 锁定在由其速度配置决定的频率上。如果 PSRAM 速度配置为 80 MHz (:ref:`CONFIG_SPIRAM_SPEED`),MPLL 将运行在 320 MHz,而 320 MHz 无法通过任何整数分频得到满足 ±50 ppm 容差要求的 50 MHz(最接近的候选值为 320 / 6 ≈ 53.33 MHz)。在此配置下,EMAC 初始化将失败。
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如果必须使用 80 MHz 的 PSRAM 速度,请通过外部时钟源(PHY 或振荡器)提供 ``REF_CLK``,并配置为 :cpp:enumerator:`emac_rmii_clock_mode_t::EMAC_CLK_EXT_IN`。
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.. only:: not SOC_EMAC_RMII_CLK_OUT_INTERNAL_LOOPBACK
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.. warning::
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