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refactor(clk): split clock HAL into separate component

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This commit is contained in:
Song Ruo Jing
2026-01-04 15:55:47 +08:00
parent 392dfed30b
commit 62511d61e9
83 changed files with 980 additions and 889 deletions
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components/esp_driver_sdmmc/src/sd_host_sdmmc.c
+1 -1
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@@ -984,7 +984,7 @@ static void sd_host_set_clk_div(sd_host_sdmmc_ctlr_t *ctlr, soc_periph_sdmmc_clk
sdmmc_ll_set_clock_div(ctlr->hal.dev, div);
sdmmc_ll_select_clk_source(ctlr->hal.dev, src);
sdmmc_ll_init_phase_delay(ctlr->hal.dev);
#if SOC_CLK_SDIO_PLL_SUPPORTED
#if SDMMC_LL_SDIO_PLL_SUPPORTED
if (src == SDMMC_CLK_SRC_SDIO_200M) {
sdmmc_ll_enable_sdio_pll(ctlr->hal.dev, true);
}