fix(esp32s31): fix stuck when PSRAM XIP with O0 optimization

components/esp_hal_mspi/esp32s31/include/hal/spimem_flash_ll.h

@@ -67,6 +67,7 @@ static inline void spimem_flash_ll_reset(spi_mem_dev_t *dev)
  *
  * @return true if last command is done, otherwise false.
  */
+__attribute__((always_inline))
 static inline bool spimem_flash_ll_cmd_is_done(const spi_mem_dev_t *dev)
 {
     return (dev->cmd.val == 0);
@@ -421,6 +422,7 @@ static inline void spimem_flash_ll_program_page(spi_mem_dev_t *dev, const void *
  * @param dev Beginning address of the peripheral registers.
  * @param pe_ops Is page program/erase operation or not.
  */
+__attribute__((always_inline))
 static inline void spimem_flash_ll_user_start(spi_mem_dev_t *dev, bool pe_ops)
 {
     uint32_t usr_pe = (pe_ops ? 0x60000 : 0x40000);
@@ -434,6 +436,7 @@ static inline void spimem_flash_ll_user_start(spi_mem_dev_t *dev, bool pe_ops)
  *
  * @return true if the host is idle, otherwise false
  */
+__attribute__((always_inline))
 static inline bool spimem_flash_ll_host_idle(const spi_mem_dev_t *dev)
 {
     return dev->cmd.mst_st == 0;
@@ -522,6 +525,7 @@ static inline void spimem_flash_ll_set_clock(spi_mem_dev_t *dev, spimem_flash_ll
  * @param dev Beginning address of the peripheral registers.
  * @param bitlen Length of input, in bits.
  */
+__attribute__((always_inline))
 static inline void spimem_flash_ll_set_miso_bitlen(spi_mem_dev_t *dev, uint32_t bitlen)
 {
     dev->user.usr_miso = bitlen > 0;
@@ -549,6 +553,7 @@ static inline void spimem_flash_ll_set_mosi_bitlen(spi_mem_dev_t *dev, uint32_t
  * @param command Command to send
  * @param bitlen Length of the command
  */
+__attribute__((always_inline))
 static inline void spimem_flash_ll_set_command(spi_mem_dev_t *dev, uint32_t command, uint32_t bitlen)
 {
     dev->user.usr_command = 1;
@@ -602,6 +607,7 @@ static inline void spimem_flash_ll_set_extra_address(spi_mem_dev_t *dev, uint32_
  * @param dev Beginning address of the peripheral registers.
  * @param addr Address to send
  */
+__attribute__((always_inline))
 static inline void spimem_flash_ll_set_address(spi_mem_dev_t *dev, uint32_t addr)
 {
     dev->addr = addr;
@@ -626,6 +632,7 @@ static inline void spimem_flash_ll_set_usr_address(spi_mem_dev_t *dev, uint32_t
  * @param dev Beginning address of the peripheral registers.
  * @param dummy_n Cycles of dummy phases
  */
+__attribute__((always_inline))
 static inline void spimem_flash_ll_set_dummy(spi_mem_dev_t *dev, uint32_t dummy_n)
 {
     dev->user.usr_dummy = dummy_n ? 1 : 0;
@@ -720,6 +727,7 @@ static inline uint32_t spimem_flash_ll_calculate_clock_reg(uint8_t clkdiv)
 
  * @param level 1: 1: output high, 0: output low
  */
+__attribute__((always_inline))
 static inline void spimem_flash_ll_set_wp_level(spi_mem_dev_t *dev, bool level)
 {
     dev->ctrl.wp_reg = level;
@@ -767,6 +775,7 @@ static inline void spimem_ctrlr_ll_unset_clock(uint8_t mspi_id)
 /**
  * @brief Reset whole memory spi
  */
+__attribute__((always_inline))
 static inline void spimem_flash_ll_sync_reset(void)
 {
     SPIMEM1.ctrl2.sync_reset = 0;
@@ -785,6 +794,7 @@ static inline void spimem_flash_ll_sync_reset(void)
  * @param user1_reg user1_reg
  * @param user2_reg user2_reg
  */
+__attribute__((always_inline))
 static inline void spimem_flash_ll_get_common_command_register_info(spi_mem_dev_t *dev, uint32_t *ctrl_reg, uint32_t *user_reg, uint32_t *user1_reg, uint32_t *user2_reg)
 {
     *ctrl_reg = dev->ctrl.val;
@@ -801,6 +811,7 @@ static inline void spimem_flash_ll_get_common_command_register_info(spi_mem_dev_
  * @param user1_reg user1_reg
  * @param user2_reg user2_reg
  */
+__attribute__((always_inline))
 static inline void spimem_flash_ll_set_common_command_register_info(spi_mem_dev_t *dev, uint32_t ctrl_reg, uint32_t user_reg, uint32_t user1_reg, uint32_t user2_reg)
 {
     dev->ctrl.val = ctrl_reg;

components/hal/esp32s31/include/hal/mmu_ll.h

@@ -34,6 +34,7 @@ extern "C" {
  *
  * @return linear address
  */
+__attribute__((always_inline))
 static inline uint32_t mmu_ll_vaddr_to_laddr(uint32_t vaddr)
 {
     return vaddr & SOC_MMU_LINEAR_ADDR_MASK;