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https://github.com/espressif/esp-idf.git
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idf_size.py: add support for esp32c3 and risc-v
This commit is contained in:
committed by
Angus Gratton
parent
4cc6b5571b
commit
b52c764bf3
+22
-3
@@ -128,6 +128,17 @@ class MemRegions(object):
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return sorted([
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MemRegDef(0x3FC88000, 0x8000 + 6 * 0x10000, MemRegions.DIRAM_ID, 0x40378000),
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])
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elif target == 'esp32c3':
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return sorted([
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MemRegDef(0x3FC80000, 0x60000, MemRegions.DIRAM_ID, 0x40380000),
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# MemRegDef(0x3FC80000, 0x20000, MemRegions.DIRAM_ID, 0x40380000),
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# MemRegDef(0x3FCA0000, 0x20000, MemRegions.DIRAM_ID, 0x403A0000),
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# MemRegDef(0x3FCC0000, 0x20000, MemRegions.DIRAM_ID, 0x403C0000),
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# Used by cache
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MemRegDef(0x4037C000, 0x4000, MemRegions.IRAM_ID, 0),
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])
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else:
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return None
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@@ -212,22 +223,30 @@ def load_memory_config(map_file):
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def detect_target_chip(map_file):
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''' Detect target chip based on the xtensa toolchain name in in the linker script part of the MAP file '''
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''' Detect target chip based on the target archive name in the linker script part of the MAP file '''
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scan_to_header(map_file, 'Linker script and memory map')
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RE_TARGET = re.compile(r'^LOAD .*?/xtensa-([^-]+)-elf/')
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RE_TARGET = re.compile(r'project_elf_src_(.*)\.c.obj')
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# For back-compatible with make
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RE_TARGET_MAKE = re.compile(r'^LOAD .*?/xtensa-([^-]+)-elf/')
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for line in map_file:
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m = RE_TARGET.search(line)
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if m:
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return m.group(1)
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m = RE_TARGET_MAKE.search(line)
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if m:
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return m.group(1)
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line = line.strip()
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# There could be empty line(s) between the "Linker script and memory map" header and "LOAD lines". Therefore,
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# line stripping and length is checked as well. The "LOAD lines" are between START GROUP and END GROUP for
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# older MAP files.
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if not line.startswith(('LOAD', 'START GROUP')) and len(line) > 0:
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if not line.startswith(('LOAD', 'START GROUP', 'END GROUP')) and len(line) > 0:
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# This break is a failsafe to not process anything load_sections() might want to analyze.
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break
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return None
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