80116d4e07
Merge branch 'feat/add_hmac_support_for_esp32h4' into 'master'
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feat: added support for HMAC in ESP32H4
Closes IDF-12257
See merge request espressif/esp-idf!44647
2026-04-15 15:18:03 +05:30
bfd3e191bc
feat: enable AES, SHA, RSA and ECC support for ESP32S31
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Co-authored-by: Nilesh Kale <nilesh.kale@espressif.com >
2026-04-13 10:20:44 +05:30
b3243dc6de
feat: enable HMAC peripheral support for ESP32-H4
2026-04-09 14:29:57 +05:30
876b9581bd
Merge branch 'fix/enable_key_mgr_clk_for_efuse_key_ops' into 'master'
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Enable Key Manager clock even for efuses-based key operations
See merge request espressif/esp-idf!46740
2026-03-25 21:37:53 +05:30
474d89b4c2
fix(clk): update H21 ECO1 to use 64MHz clock for mspi
2026-03-25 15:38:49 +08:00
28736a81fa
fix(esp_security): Enable Key Manager clocks even for efuse key operations
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The Key Manager holds a key usage register, thus, the Key Manager peripheral
clock must be enabled even for efuses-based key operations to route the
crypto operations to correctly to the efuses (default is Key Manager)
2026-03-25 10:38:44 +05:30
ccc48c3980
fix(esp_security): Fixes incorrect key manager configuration for ESP32-P4 rev < 3
2026-03-24 15:23:23 +05:30
398d9ea9cd
fix(esp_security): Add more validation checks
2026-03-20 11:15:23 +05:30
0db717b9ec
feat(esp_ds): Support using the AES key used by DS peripheral for encrypting params
2026-03-20 11:15:23 +05:30
5f647c0ba3
docs(key-manager): Add Key-Manager peripheral related documentation
2026-03-18 16:27:39 +05:30
51cca0a88f
feat(esp_hw_support): support clock tree management for esp32p4
2026-03-04 20:10:54 +08:00
0fd1a4c9f8
test(esp_security): re-enable crypto drivers test app for ESP32P4
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Also remove common_components dep for security-related tests
2026-02-10 17:48:55 +05:30
6964de6f45
test(esp_security): Update the Key Manager test to support ESP32-P4
2026-02-10 17:48:52 +05:30
0a6c922059
fix(esp_system): limit CPU clock to 160MHz in ESP32-C5 for flash encryption
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This reverts commit 7145fc9558
2026-01-28 11:15:30 +05:30
4c26ab876b
ci: update build-test-rules to use common_components
2026-01-23 10:14:09 +08:00
eb4a871eca
refactor(esp_hal_security): Updated esp_hal_security build and includes
2026-01-21 10:02:44 +05:30
215c9993bf
fix(clk): update H4 to use 64MHz clock for mspi
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And add pll clock ref count
2026-01-04 14:07:01 +08:00
7145fc9558
Revert "fix(esp_system): limit CPU clock to 160MHz in ESP32-C5 for flash encryption"
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This reverts commit 3c5d2e6b58
2025-12-16 17:43:58 +08:00
0c4cf75c35
feat(esp32s31): Introduce esp32s31 hello world
2025-12-02 10:44:16 +08:00
b873a82d5b
Merge branch 'feat/generic_key_mgr_key_types' into 'master'
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Store key_len field in the key_config
See merge request espressif/esp-idf!42692
2025-11-18 15:12:03 +05:30
961bd0cf78
Merge branch 'feat/introduce_esp32s31' into 'master'
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feat(esp32s31): Introduce new target esp32s31
See merge request espressif/esp-idf!43316
2025-11-18 15:55:16 +08:00
1c1bcf44be
feat(esp_security): Support ECDSA-P384 key deployment using Key Manager
2025-11-17 12:34:09 +05:30
1f2cbde525
change(esp_key_mgr): Store key_len field in the key_info
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- Update the Key Manager key types to be generic
- Define a new enum to determine the length of the keys
- Refactor the Key Manager driver support generic key types and key lengths
- Also store key deployment mode in the key recovery info
2025-11-17 12:34:09 +05:30
a90c93541c
feat(esp32s31): Introduce new target esp32s31
2025-11-17 14:48:55 +08:00
b25ba4a0c1
ci(p4): disable p4 rev3 invalid tests temporarily
2025-11-17 12:11:39 +08:00
4a53c4e651
Merge branch 'bugfix/esp32c5_encrypted_flash_write_v2' into 'master'
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fix(esp_system): limit CPU clock to 160MHz in ESP32-C5 for flash encryption
See merge request espressif/esp-idf!43301
2025-11-13 18:01:04 +05:30
0debe71b3d
Merge branch 'feat/flash_enc_using_key_manager' into 'master'
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Support Flash Encryption using Key Manager
Closes IDF-13462 and IDF-14278
See merge request espressif/esp-idf!41879
2025-11-13 07:55:15 +05:30
3c5d2e6b58
fix(esp_system): limit CPU clock to 160MHz in ESP32-C5 for flash encryption
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Encrypted flash write operation sometimes result in random corruption in
certain bytes. Root cause points to sudden current surge due to involvement of
encryption block overwhelming LDO supply. More details will be provided
in the ESP32-C5 SoC Errata document.
This fix limits the CPU clock to 160MHz for flash encryption enabled
case. Failing encrypted flash write tests could successfully pass in
this configuration. Going ahead, a dynamic clock adjustment in flash
driver will be considered to mitigate this issue.
2025-11-12 19:14:55 +05:30
619cbb85b3
Merge branch 'fix/disallow_enabling_sb_sha384_when_sb_sha256_is_enabled_p4' into 'master'
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fix(efuse): Disallow enabling SB using SHA-384 when SB using SHA-256 is enabled (ESP32-P4 ECO5)
Closes IDF-14063
See merge request espressif/esp-idf!42884
2025-11-11 17:11:47 +05:30
540c719c66
change(esp_key_mgr): Make Key Manager driver bootloader compatible
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- Independent of heap
2025-11-11 12:23:26 +05:30
8abea3c537
feat(bootloader_support): Support Flash Encryption using Key Manager
2025-11-11 12:23:25 +05:30
304bd1c77b
fix(esp_security/esp_key_mgr): Fix missed error codes and some cleanup
2025-11-11 12:22:08 +05:30
b9a503e9ec
feat(esp_tee): Support for ESP32-C61 - the rest of the components
2025-11-07 14:54:16 +05:30
3090e91e60
fix(esp_security): Set WR_DIS_SECURE_BOOT_SHA384_EN by default when
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Flash Encryption Release mode is enabled and Secure Boot P384 scheme not is enabled.
2025-11-05 08:39:55 +05:30
7168b9f7d3
fix(esp_security): Fix undefined efuse build failure in case of ESP32-P4
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- The `wr_dis` efuse bit corresponding to `SECURE_BOOT_SHA384_EN` is absent in P4
2025-11-05 08:39:55 +05:30
609d52c6bf
feat(esp32p4): Support newer Key Manager key sources for ESP32-P4 V3
2025-10-15 15:49:20 +05:30
fd7d9c9ee9
Merge branch 'fix/key_mgr_use_default_efuse_key' into 'master'
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Configure the Key Manager to use XTS-AES efuse key by-default
Closes IDFCI-3135 and IDFCI-3136
See merge request espressif/esp-idf!42032
2025-09-26 12:34:19 +05:30
8b663ebe4d
fix(esp_security): Configure the Key Manager to use XTS-AES efuse key by-default
2025-09-22 12:22:07 +05:30
5aa5366e7f
fix(bootloader_support): Reorder write disabling ECDSA_CURVE_MODE
2025-09-19 17:01:23 +05:30
d6c1184676
fix(bootloader_support): Reorder write protection bits of some shared security efuses
2025-09-19 13:02:00 +05:30
854ec3590f
fix(esp_key_mgr): Fix incorrect key manager state management
2025-09-12 11:02:45 +05:30
9d35d63651
feat(cmake): Update minimum cmake version to 3.22 (whole repository)
2025-08-19 14:44:32 +02:00
9e87b50307
change(mbedtls/ecdsa): The ECDSA module of ESP32-H2 ECO5 does not use MPI module
2025-08-11 12:08:51 +05:30
55e0730a8d
change(esp_hw_support): Move security-related modules to the esp_security component
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- Also adds support to whitelist target specific expected dependency violations
in check_dependencies.py
2025-08-04 11:43:01 +05:30
bf84ab652a
change(test_utils): moved test_utils component to tools/test_apps/components/
2025-07-21 14:05:50 +08:00
dce0925f40
fix(esp_security/esp_key_mgr): Incorrect overlapping comparisons
2025-07-03 15:05:50 +05:30
bba1448128
feat(esp_key_mgr): Support PSRAM XTS-AES key deployments using Key Manager
2025-06-27 15:15:26 +05:30
eb7c5654f6
test(esp_security): Extend the key manager tests
2025-06-27 15:15:26 +05:30
50c41c3b59
change(esp_key_mgr): Refactor Key Manager driver to reduce logs
2025-06-27 15:15:26 +05:30
a7af364112
fix(esp_security): Power up MPI memory registers when enabling MPI
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Co-authored-by: Li HongXi <lihongxi@espressif.com >
2025-06-27 15:15:26 +05:30
Mahavir Jain
Aditya Patwardhan
nilesh.kale
Harshal Patil
hebinglin
wuzhenghui
Xiao Xufeng
igor.udot
Song Ruo Jing
C.S.M
armando
Laukik Hase
Marek Fiala
Marius Vikhammer