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release/v5.3
Commit Graph

901 Commits

Author SHA1 Message Date
gaoxu ee04b19643 feat(adc): support ADC calibration on ESP32P4 2026-02-03 16:52:04 +08:00
gaoxu 9557828ef8 fix(adc): fix adc1 error after bootloader random 2026-02-03 16:52:04 +08:00
wuzhenghui 9e3aa38706 fix(esp_system): fix rom secure boot fast wake feature for c5/c6/h2/h21 2026-01-12 19:13:41 +08:00
Alexey Gerenkov bfbb48ed6a Merge branch 'esp32p4_fix_bootloader_flash_read_allow_decrypt_v5.3' into 'release/v5.3' 
fix(bootloader_flash): always invalidate FLASH_READ_VADDR before read (v5.3)

See merge request espressif/esp-idf!43959
 2025-12-11 21:05:01 +08:00
Samuel Obuch f0a44810a0 fix(bootloader_flash): invalidate FLASH_READ_VADDR before read 
Fixed address to match corresponding mmu_hal_map_region call.
MMU_BLOCK0_VADDR was invalidated by mistake in commit
ea38a2e9a4
 2025-12-03 10:08:41 +01:00
Mahavir Jain 8b4d18d27b fix(bootloader): fix signature verification skip in deep sleep scenario 
For CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP enabled and exit from
deep sleep case the secure boot signature verification must be skipped
to improve the wakeup performance.

Closes https://github.com/espressif/esp-idf/issues/15590
 2025-11-25 10:11:41 +05:30
harshal.patil b0442de937 fix(bootloader_support): Allow pre-programmed XTS-AES psuedo round level efuses 
- The API esp_flash_encryption_set_release_mode() by defualt programs
the XTS-AES pseudo round level efuse to level low but did not considered
any existing value that would have been programmed in the efuse bit.
 2025-09-30 15:19:26 +05:30
harshal.patil c3c15d240e fix(bootloader_support): Reorder write protection bits of some shared security efuses 2025-09-30 14:57:12 +05:30
Mahavir Jain ec588172ed fix(bootloader): correct encryption length for secure update without secure boot 
For secure update without secure boot case, the encryption length for
app image must consider signature block length as well. This was
correctly handled for secure boot case but not for secure update without
secure boot.
 2025-09-16 10:21:48 +05:30
nilesh.kale 19fcf0e073 feat: enabled ECDSA-P192 support for ESP32H2 2025-06-24 15:03:59 +05:30
Omar Chebib 67b64ce555 fix(esp_system): fix RTC reserved area alignment in the linker script 
Make sure the size of the RTC reserved area complies with the alignment requirement.

Closes https://github.com/espressif/esp-idf/issues/13082
 2025-06-17 16:50:10 +08:00
Aditya Patwardhan c50e49dd0f Merge branch 'bugfix/esp32_c6_rev0_ecdsa_build_v5.3' into 'release/v5.3' 
fix: Secure boot (ECDSA) build failure for C6 rev0 target (v5.3)

See merge request espressif/esp-idf!38835
 2025-05-02 10:38:03 +08:00
armando 956d74a22b fix(bootloader): fixed image cannot exceed 16MB issue 
flash 32-bit-addr is an experimental feature that has multiple
dependencies, e.g. flash chip vendor, etc.

If CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_QUAD_FLASH can be enabled
successfully and tests are passed, we can allow images to be
placed on higher-than-16MB flash addresses
 2025-04-30 10:34:55 +08:00
Mahavir Jain ffc4ceb1a5 fix: Secure boot (ECDSA) build failure for C6 rev0 target 
Closes https://github.com/espressif/esp-idf/issues/15856
 2025-04-29 18:06:08 +08:00
Guillaume Souchere 5c62675f45 fix(esp_hw_support): esp_ptr_in_rtc_iram_fast check to return false 
esp_ptr_in_rtc_iram_fast logic should be executed if
SOC_RTC_FAST_MEM_SUPPORTED is set but it should also be executed
if IRAM and DRAM region mapping is the same. Remove the
SOC_RTC_IRAM_LOW != SOC_RTC_DRAM_LOW part of the check.

Update heap component to use the modify function appropriately.
 2025-03-07 12:24:07 +01:00
Guillaume Souchere 693058a728 fix(esp_hw_support): Unused variables in memory_utils functions 2025-02-10 07:16:08 +01:00
Guillaume Souchere bee3d8ff86 fix(heap): MALLOC_CAP_EXEC does not allocate in RTC IRAM 
This commit fixes the issue when trying to allocate memory
with the MALLOC_CAP_EXEC in RTC memory. Prior to the fix,
the heap allocator was returning an address in RTC DRAM.

To fix this issue:
- modified memory_layout.c of the concerned targets to fill the iram_address
field in the rtc entry of the soc_memory_region array properly.
- modified heap component  related functions to return IRAM address when
an allocation in RTC memory with MALLOC_CAP_EXEC is requested.

Closes https://github.com/espressif/esp-idf/issues/14835
 2025-02-10 07:16:07 +01:00
harshal.patil ac0dc0d775 feat(bootloader_support): Permanently enable XTS-AES pseudo rounds when FE release mode is enabled 2025-01-23 14:06:16 +05:30
laokaiyao 2abf73d94c refactor(lpperi): improve compatibility solution 2025-01-16 10:18:02 +08:00
laokaiyao 90457a9a4e refactor(lpperi): compatible refactor for H2 ECO5 2025-01-13 14:39:33 +08:00
zlq 0e37fdd1b0 fix: fix pll low temp bug (v5.3) 2024-11-27 19:17:48 +08:00
Jiang Jiang Jian 7229ec4be9 Merge branch 'feature/check_efuse_blk_after_ota_v5.3' into 'release/v5.3' 
feat(bootloader): support to check efuse block revision (v5.3)

See merge request espressif/esp-idf!33136
 2024-10-28 12:20:05 +08:00
C.S.M 922777118b patch(spi_flash): cleanup XMC flash chip usage according to new information 2024-10-23 17:34:16 +08:00
C.S.M 8890286468 feat(spi_flash): Add new xmc chip id 2024-10-23 17:34:16 +08:00
morris 81d0122ede Merge branch 'ci/remove_c5_build' into 'release/v5.3' 
ci(esp32c5,esp32c61): stop building c5 and c61 on 5.3

See merge request espressif/esp-idf!33525
 2024-09-23 13:16:36 +08:00
Chen Jichang c9430ed953 ci(esp32c5,esp32c61): stop building c5 and c61 on 5.3 2024-09-13 19:39:29 +08:00
morris 5589d8cbf4 Merge branch 'feat/flash_32bit_support_p4_v5.3' into 'release/v5.3' 
feature(spi_flash): Add 32bit address support for esp32p4 eco1 (backport v5.3)

See merge request espressif/esp-idf!31262
 2024-09-12 11:45:14 +08:00
Aditya Patwardhan aa754d40b8 fix(security): Fixed flash encryption for esp32p4 
The flash encryption on esp32p4 was broken due to code related
    to key manager not being executed when key manager support was
    disabled on esp32p4 target.
    This commit fixes that behaviour
    Additionally, the atomic env enablement for
    key_mgr_ll_enable_peripheral_clock was fixed.
 2024-09-02 13:28:30 +05:30
laokaiyao 1ece052ce3 feat(bootloader): support to check efuse block revision 
change(bootloader): remove ignore efuse check flag (temp)

change(bootloader): use int for the minimum efuse blk rev (temp)
 2024-08-28 12:12:00 +08:00
Jiang Jiang Jian 0526c35ec3 Merge branch 'fix/esp32c5_rng_random_disable_v5.3' into 'release/v5.3' 
fix(bootloader): update random disable api for ESP32-C5/C6 (v5.3)

See merge request espressif/esp-idf!32761
 2024-08-19 11:33:01 +08:00
Mahavir Jain 3eec62f823 fix(rng): avoid clearing PMU_PERIF_I2C_RSTB in random disable API for C6 
This configuration bit is required for ADC operation as well and hence
should not be cleared in the RNG API sequence.

Ideally, the ADC driver should take care of initializing this bit but
still the RNG layer change is required because of interleaved API usage
scenario described in following linked issue.

Closes https://github.com/espressif/esp-idf/issues/14124
Closes https://github.com/espressif/esp-idf/issues/14280
 2024-08-12 10:07:28 +05:30
harshal.patil 12a2e89ac6 fix(bootloader_support): Fix encrypt image instead of the partition feature not being enabled 2024-08-06 13:44:36 +05:30
C.S.M a4fbcae397 feat(spi_flash): Adjust flash clock to real 80M clock, and support 32bit address on eco1 2024-08-01 18:12:51 +08:00
laokaiyao 951bdd70a2 fix(ci): fix the readme check of c5 mp 2024-07-30 15:40:19 +08:00
Mahavir Jain ad0cfa57e7 Merge branch 'feature/esp32p4_apm_api_v5.3' into 'release/v5.3' 
feat: add esp32p4 APM HAL/LL API (v5.3)

See merge request espressif/esp-idf!31417
 2024-07-25 16:50:18 +08:00
Jakob Hasse 083db8a169 fix(bootloader_support): Fixed pattern in RNG enable function on C6 to avoid output on IO0 2024-07-04 11:36:31 +02:00
Sachin Billore 5869850af2 feat: add esp32p4 APM HAL/LL API 2024-06-14 12:55:03 +08:00
gaoxu cfc5da167d feat(soc): rename lp_adc and ahb_dma reg base on p4 2024-06-12 18:16:48 +08:00
Song Ruo Jing bbc44b486e feat(gdma): add GDMA support for ESP32C5 MP 2024-06-12 15:28:40 +08:00
Michael (XIAO Xufeng) 98e99e712f Merge branch 'feature/esp32c5_mp_gpio_support_v5.3' into 'release/v5.3' 
Feature/esp32c5 mp gpio support (v5.3)

See merge request espressif/esp-idf!30884
 2024-06-12 00:51:06 +08:00
Michael (XIAO Xufeng) 5c618745fe Merge branch 'feat/brownout_support_p4_v5.3' into 'release/v5.3' 
feat(brownout): Add brownout detector support on esp32p4 (backport v5.3)

See merge request espressif/esp-idf!31094
 2024-06-11 21:21:10 +08:00
Michael (XIAO Xufeng) dbf8726b47 Merge branch 'feat/esp32p4_xip_psram_v5.3' into 'release/v5.3' 
psram: support xip_psram on esp32p4 (v5.3)

See merge request espressif/esp-idf!31044
 2024-06-11 21:07:41 +08:00
C.S.M 4daaa9c587 fix(bod): Disable fib in bootloader so that interrupt can be triggered properly 2024-06-07 10:38:14 +08:00
Armando 58ebdb7ae3 change(image): move image_process driver from bootloader_support to esp_system 2024-05-29 10:02:44 +08:00
Armando 48e06fafea feat(xip_psram): support xip psram feature on esp32p4 2024-05-29 10:02:44 +08:00
gaoxu bf604e91a6 feat(gpio): remove io_mux_reg array in gpio_periph.c from c5 2024-05-27 18:13:42 +08:00
Armando 687064b2f8 change(cpu_start): added note about internal ram only stage 2024-05-23 15:41:35 +08:00
harshal.patil 0c5bce6918 fix(bootloader_support): Make esp_flash_encrypt.h independent of spi_flash_mmap.h header 2024-05-20 14:40:49 +08:00
Mahavir Jain d638267741 Merge branch 'fix/fix_flash_encryption_esp32p4_v5.3' into 'release/v5.3' 
fix(bootloader_support): Fix flash encryption for esp32p4 (v5.3)

See merge request espressif/esp-idf!30921
 2024-05-20 12:29:18 +08:00
Aditya Patwardhan 3640c1ecba fix(bootloader_support): Fix flash encryption for esp32p4 2024-05-17 21:19:14 +05:30