The error messages for vPortEnterCritical and vPortExitCritical are
misleading when they're called on a multi-core target, as they seem to
imply that the call is NOT supported on a single-core target. In fact,
they are, these functions are, however, not supported on multi-core
targets, so the error message has been updated to reflect this.
Merges https://github.com/espressif/esp-idf/pull/18109
This commit deprecates xPortGetTickRateHz() from the FreeRTOS port API
as the FreeRTOS tickrate is constant for an application and can be
inferred using the CONFIG_FREERTOS_HZ config option.
This commit creates a new port layer API xPortGetRunTimeCounterValue()
in port.c files. This helps to remove inclusion of header files such as
esp_timer.h and xtensa/hal.h from portmacro.h
This commit removes support for the vPortCleanUpTCB() user hook as well
as drops support for associated Kconfig option,
CONFIG_FREERTOS_STATIC_TASK_CLEAN_UP.
The following updates have been made in this commit:
- The commit places FreeRTOS code in flash memory by default.
- CONFIG_FREERTOS_PLACE_FUNCTIONS_INTO_FLASH has been removed.
- CONFIG_FREERTOS_IN_IRAM is unhidden and can be used to restore the
previous memory placement.
- A test has been added for users to conduct performance impact testing
based on memory placement configurations.
This commit renames all registers in xtensa/specreg.h to by adding the
prefix XT_REG_. This is done to avoid naming collisions with similar
variable names. A new register file, viz., xt_specreg.h is created. The
previous names are still available to use but have been deprecated.
Closes https://github.com/espressif/esp-idf/issues/12723
Merges https://github.com/espressif/esp-idf/pull/16040
Due to old windows from the startup flow being present after
switching to running freertos tasks windowoverflow exceptions
could potentially try to save windows to the startup stack.
During this overflow they also values previously saved on the
startup stack to find earlier frames' stacks.
Since the start up stack was already recycled these values were
invalid and would cause a crash.
Closes https://github.com/espressif/esp-idf/issues/14406Y
The vTaskPlaceOnEventListRestricted() did not use the correct macro when
exiting a kernel cirtical section. This does not affect the HW targets
but on the Linux port, this caused an issue as the critical nesting
count became negative, leading to deadlocks. This commit fixes the bug
and updates the linux port to prevent the nesting count from going
negative.
This commit fixes an issue where in the FreeRTOS port layer would cause
the portASSERT_IF_IN_ISR() assert check to fail even when the system is
not in an interrupt context.
FreeRTOS tasks may now freely use the PIE coprocessor and HWLP feature.
Just like the FPU, usiing these coprocessors result in the task being pinned
to the core it is currently running on.
This commit fixes a bug where the portTRY_ENTER_CRITICAL_SAFE() for the
Xtensa and RISC-V FreeRTOS ports were broken as it did not correctly use
the timeout parameter.
Merges: https://github.com/espressif/esp-idf/pull/13022
- move .tbss to NOLOAD section
- remove xtensa-specific entities from riscv scripts
- explicit eh_frame terminator instead of "align magic"
- 80 characters line length limit
- refactor comments
- discard .rela sections (the rela data will go to relates sections)
fix(riscv): Updated RISC-V functions to set interrupt threshold for CLIC targets
Closes IDFCI-2033, IDFCI-2034, IDF-8090, and IDF-8117
See merge request espressif/esp-idf!29055
This commit introduce SOC_MEM_NON_CONTIGUOUS_SRAM flag (that enebled for
esp32p4). If SOC_MEM_NON_CONTIGUOUS_SRAM is enabled:
- LDFLAGS+=--enable-non-contiguous-regions
- ldgen.py replaces "arrays[*]" from sections.ld.in with objects under
SURROUND keyword. (e.g. from linker.lf: data -> dram0_data SURROUND(foo))
- "mapping[*]" - refers to all other data
If SOC_MEM_NON_CONTIGUOUS_SRAM, sections.ld.in file should contain at
least one block of code like this (otherwise it does not make sense):
.dram0.bss (NOLOAD) :
{
arrays[dram0_bss]
mapping[dram0_bss]
} > sram_low
.dram1.bss (NOLOAD) :
{
/* do not place here arrays[dram0_bss] because it may be splited
* between segments */
mapping[dram0_bss]
} > sram_high
This commit added the RISC-V utility functions to set the interrupt
threshold for CLIC targets by using direct register value writes.
This makes the functions more efficient during run-time.
This is done to improve the critical section enter and exit performance on esp32p4.