mirror of
https://github.com/espressif/esp-idf.git
synced 2026-04-27 19:13:21 +00:00
morris
0469db2f83
- Removed conditional definitions for various RCC_ATOMIC macros across multiple files, replacing them with a unified PERIPH_RCC_ATOMIC() macro. - Updated instances where specific RCC_ATOMIC macros were used to ensure consistent usage of PERIPH_RCC_ATOMIC(). - Deleted unused uart_share_hw_ctrl.h file as its functionality is now integrated into the new structure.
226 lines
11 KiB
C
226 lines
11 KiB
C
/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdatomic.h>
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#include <sys/queue.h>
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// SOC specific headers should be included early
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#include "soc/soc_caps.h"
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#include "sdkconfig.h"
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#if CONFIG_I3C_MASTER_ENABLE_DEBUG_LOG
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// The local log level must be defined before including esp_log.h
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// Set the maximum log level for i3c master driver
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#define LOG_LOCAL_LEVEL ESP_LOG_VERBOSE
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#endif
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#include "esp_log.h"
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// FreeRTOS headers must be included in order: FreeRTOS.h first, then others
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#include "freertos/FreeRTOS.h"
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#include "freertos/queue.h"
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#include "freertos/semphr.h"
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#include "hal/i3c_master_types.h"
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#include "hal/i3c_master_hal.h"
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#include "esp_dma_utils.h"
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#include "esp_private/gdma.h"
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#include "esp_private/gdma_link.h"
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#include "esp_private/periph_ctrl.h"
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#include "esp_intr_types.h"
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#include "driver/i3c_master_types.h"
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#include "esp_pm.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define I3C_MASTER_ALLOW_INTR_PRIORITY_MASK ESP_INTR_FLAG_LOWMED
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// interface between i3c and dma need 4 bytes aligned.
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#define I3C_MASTER_DMA_INTERFACE_ALIGNMENT (4)
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#if CONFIG_I3C_MASTER_ISR_CACHE_SAFE
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#define I3C_MASTER_MEM_ALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT)
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#else
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#define I3C_MASTER_MEM_ALLOC_CAPS (MALLOC_CAP_DEFAULT)
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#endif
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#if CONFIG_I3C_MASTER_ISR_CACHE_SAFE
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#define I3C_MASTER_INTR_ALLOC_FLAG (ESP_INTR_FLAG_IRAM | ESP_INTR_FLAG_LOWMED)
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#else
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#define I3C_MASTER_INTR_ALLOC_FLAG (ESP_INTR_FLAG_LOWMED)
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#endif
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#define I3C_ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1))
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#define I3C_BUS_BROADCAST_ADDR 0x7EU /*!< Broad cast address. */
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#define I3C_BUS_MAX_ADDR 0x7FU /*!< Maximum address allowed for address assignment. */
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#define I3C_BUS_ADDR_SLOTWIDTH 2U /*!< Address slot width used in address management in bus pool. */
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#define I3C_BUS_ADDR_SLOTDEPTH 32U /*!< Address slot depth used in address management in bus pool. */
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#define I3C_BUS_ADDR_SLOTMASK 3U /*!< Address slot mask used in address management in bus pool. */
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#define I3C_BOARDCAST_SINGLE_BIT_ERR_DETECT_ADDR1 0x3EU /*!< Broadcast address single bit error detect address. */
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#define I3C_BOARDCAST_SINGLE_BIT_ERR_DETECT_ADDR2 0x5EU /*!< Broadcast address single bit error detect address. */
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#define I3C_BOARDCAST_SINGLE_BIT_ERR_DETECT_ADDR3 0x6EU /*!< Broadcast address single bit error detect address. */
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#define I3C_BOARDCAST_SINGLE_BIT_ERR_DETECT_ADDR4 0x76U /*!< Broadcast address single bit error detect address. */
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#define I3C_BOARDCAST_SINGLE_BIT_ERR_DETECT_ADDR5 0x7AU /*!< Broadcast address single bit error detect address. */
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#define I3C_BOARDCAST_SINGLE_BIT_ERR_DETECT_ADDR6 0x7CU /*!< Broadcast address single bit error detect address. */
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#define I3C_BOARDCAST_SINGLE_BIT_ERR_DETECT_ADDR7 0x7FU /*!< Broadcast address single bit error detect address. */
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/**
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* @brief Forward declaration of the I3C master bus structure.
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*/
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typedef struct i3c_master_bus_t i3c_master_bus_t;
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/**
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* @brief Forward declaration of the I3C master I2C device structure.
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*/
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typedef struct i3c_master_i2c_dev_t i3c_master_i2c_dev_t;
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/**
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* @brief Forward declaration of the I3C master I3C device structure.
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*/
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typedef struct i3c_master_i3c_dev_t i3c_master_i3c_dev_t;
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/**
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* @brief Structure representing the base device containing common members.
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*
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* This structure contains the common members shared between I2C and I3C devices
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* on an I3C master bus.
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*/
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struct i3c_master_device_t {
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i3c_master_bus_t *bus_handle; /**< Handle to the I3C master bus managing this device. */
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};
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/**
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* @brief I3C master bus port number.
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*/
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typedef int i3c_master_bus_num_t;
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/**
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* @brief Structure representing a transaction descriptor for I3C/I2C operations.
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*/
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typedef struct {
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i3c_master_ll_device_address_descriptor_t *addr_table; /**< Pointer to the address table, mapping device addresses. */
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size_t addr_table_num; /**< Number of entries in the address table. */
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i3c_master_ll_command_descriptor_t *command_table; /**< Pointer to the command table for the transaction. */
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size_t command_table_num; /**< Number of commands in the command table. */
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uint8_t *write_buffer; /**< Pointer to the data buffer for writing. */
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uint8_t *read_buffer; /**< Pointer to the data buffer for reading. */
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uint32_t scl_freq_hz; /**< Speed of the SCL clock in Hz for the transaction. */
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i3c_master_device_handle_t dev_handle; /**< Direct storage of device handle. */
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bool i2c_trans; /**< Flag indicating whether the transaction is an I2C transaction. */
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} i3c_transaction_desc_t;
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/**
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* @brief Enumeration representing the states of the I3C transaction queue.
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*/
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enum {
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I3C_TRANS_QUEUE_READY, /**< The transaction queue is ready to accept new transactions. */
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I3C_TRANS_QUEUE_PROGRESS, /**< A transaction is currently in progress. */
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I3C_TRANS_QUEUE_COMPLETE, /**< All transactions in the queue are completed. */
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I3C_TRANS_QUEUE_MAX, /**< Placeholder for the maximum number of states (not a valid state). */
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};
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/**
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* @brief Enumeration representing the states of the I3C finite state machine (FSM).
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*/
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typedef enum {
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I3C_FSM_WAIT, /**< FSM is waiting for the I3C system to be ready. */
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I3C_FSM_ENABLE, /**< FSM is enabling the I3C system. */
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I3C_FSM_RUN, /**< FSM is in the running state, actively handling I3C operations. */
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} i3c_fsm_t;
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/**
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* @brief Function pointer type for transaction handler
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*/
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typedef esp_err_t (*i3c_transaction_handler_t)(i3c_master_bus_t *bus_handle, i3c_transaction_desc_t *trans_desc);
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/**
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* @brief Structure representing the I3C master bus.
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*
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* This structure contains all the resources and states needed for
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* managing an I3C master bus, including hardware abstraction, transaction
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* handling, and synchronization.
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*/
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struct i3c_master_bus_t {
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i3c_master_bus_num_t i3c_num; /**< I3C bus number. */
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i3c_master_hal_context_t hal; /**< HAL layer context for each port (bus). */
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i3c_master_clock_source_t clock_source; /**< Source of the I3C clock. */
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uint32_t clock_source_freq; /**< Frequency of the clock source in Hz. */
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bool dma_initialized; /**< Flag indicating whether DMA has been initialized via decorator. */
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bool use_dma_transaction; /**< Flag indicating whether DMA is used for transactions. */
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bool async_transaction; /**< Flag indicating whether asynchronous transactions are enabled. */
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QueueHandle_t event_queue; /**< Queue for handling I3C events. */
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SLIST_HEAD(i3c_i2c_device_list_head, i3c_master_i2c_dev_t) i2c_device_list; /**< List of I2C devices on the bus. */
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SLIST_HEAD(i3c_i3c_device_list_head, i3c_master_i3c_dev_t) i3c_device_list; /**< List of I3C devices on the bus. */
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i3c_transaction_desc_t *cur_trans; /**< Pointer to the current transaction descriptor. */
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i3c_transaction_desc_t *trans_desc_pool; /**< Pool of pre-allocated transaction descriptors. */
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uint32_t ops_prepare_idx; /**< Index for preparing operations. */
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bool async_memory_allocated; /**< The async transaction is allocated or not */
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i3c_master_ll_device_address_descriptor_t (*i3c_async_addr_table)[I3C_MASTER_LL_ADDRESS_TABLE_NUM]; /**< Address table for asynchronous transactions. */
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i3c_master_ll_command_descriptor_t (*i3c_async_command_table)[I3C_MASTER_LL_COMMAND_TABLE_NUM]; /**< Command table for asynchronous transactions. */
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QueueHandle_t trans_queues[I3C_TRANS_QUEUE_MAX]; /**< Array of transaction queues for different states. */
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intr_handle_t intr_handle; /**< Interrupt handle for I3C interrupts. */
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_Atomic i3c_fsm_t fsm; /**< Current state of the I3C finite state machine. */
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uint8_t num_trans_inflight; /**< Number of in-flight transactions. */
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size_t queue_depth; /**< Depth of the transaction queue. */
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SemaphoreHandle_t bus_lock_mux; /**< Semaphore for bus locking. */
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portMUX_TYPE spinlock; /**< Spinlock for protecting critical sections. */
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uint32_t addr_slots[((I3C_BUS_MAX_ADDR + 1U) * I3C_BUS_ADDR_SLOTWIDTH) / I3C_BUS_ADDR_SLOTDEPTH]; /**< Address slots. */
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uint8_t entdaa_device_num; /**< Number of devices to discover via ENTDAA. */
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#ifdef CONFIG_PM_ENABLE
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esp_pm_lock_handle_t pm_lock; /**< Power management lock handle. */
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#endif
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size_t cache_line_size; /**< Cache line size for doing C2M operation */
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uint8_t *write_fifo_buffer_pointer; /**< Pointer to the write FIFO buffer. */
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size_t write_buffer_left_size; /**< Remaining size of the write buffer. */
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uint8_t *read_fifo_buffer_pointer; /**< Pointer to the read FIFO buffer. */
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size_t read_buffer_left_size; /**< Remaining size of the read buffer. */
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gdma_channel_handle_t dma_tx_chan; /**< DMA channel handle for TX. */
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gdma_channel_handle_t dma_rx_chan; /**< DMA channel handle for RX. */
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gdma_link_list_handle_t tx_dma_link; /**< Linked list for TX DMA. */
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gdma_link_list_handle_t rx_dma_link; /**< Linked list for RX DMA. */
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size_t dma_buffer_alignment; /**< Alignment of the DMA buffer. */
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i3c_transaction_handler_t transaction_handler; /**< Function pointer for transaction handling (FIFO or DMA) */
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bool global_ibi_configured; /**< Flag indicating whether global IBI configuration has been set */
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};
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/**
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* @brief Structure representing an I2C device managed by the I3C master.
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*
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* This structure contains all the necessary information and configuration
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* required to communicate with an I2C device on an I3C master bus.
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*/
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struct i3c_master_i2c_dev_t {
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i3c_master_device_handle_t base; /**< Base device handle containing common members. */
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uint8_t address; /**< 7-bit I2C address of the device. */
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uint32_t scl_freq_hz; /**< I2C clock speed for this device, in Hz. */
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i3c_master_i2c_callback_t on_trans_done; /**< Callback function invoked upon transaction completion. */
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void *user_ctx; /**< User-defined context passed to the callback function. */
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SLIST_ENTRY(i3c_master_i2c_dev_t) next; /**< Pointer to the next device in the single-linked list. */
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};
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struct i3c_master_i3c_dev_t {
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i3c_master_device_handle_t base; /**< Base device handle containing common members. */
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SLIST_ENTRY(i3c_master_i3c_dev_t) next; /**< Pointer to the next device in the single-linked list. */
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i3c_master_i3c_callback_t on_trans_done; /**< Callback function invoked upon transaction completion. */
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i3c_master_ibi_callback_t on_ibi; /**< Callback function invoked upon IBI. */
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void *user_ctx; /**< User-defined context passed to the callback function. */
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uint8_t dynamic_addr; /**< Dynamic address of the device. */
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uint8_t static_addr; /**< Static address of the device. */
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uint8_t bcr; /**< Bus Characteristics Register (BCR) value reported by the device. */
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uint8_t dcr; /**< Device Characteristics Register (DCR) value reported by the device. */
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uint64_t pid; /**< Provisional ID (PID). Lower 48 bits are valid as per spec. */
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};
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struct i3c_master_i3c_device_table_t {
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i3c_master_i3c_device_handle_t *devices; /**< Array of I3C device handles */
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size_t device_count; /**< Number of devices in the table */
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i3c_master_bus_handle_t bus_handle; /**< Bus handle that owns these devices, internal resource management */
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};
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#ifdef __cplusplus
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}
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#endif
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