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9ab7d5eb03
Add ESP32-S31 USB DWC/UTMI LL headers, SoC register structures, peripheral descriptors, capabilities, and linker mappings so the HS OTG controller and UTMI PHY can be built in esp_hal_usb. Introduce SOC_USB_FSLS_PHY_NUM on USB-OTG targets to separate FSLS USB_WRAP support from OTG/UTMI support. Use it to gate usb_wrap, the USB PHY driver, docs, and example build rules on targets without an FSLS PHY. Also add UTMI data pulldown control to the HAL, clear the boot-time DWC suspend state on ESP32-S31, alias the legacy internal PHY target to UTMI for backward compatibility, and extend usb_phy tests for UTMI-only targets.
35 lines
843 B
C
35 lines
843 B
C
/*
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* SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "hal/usb_wrap_hal.h"
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void _usb_wrap_hal_init(usb_wrap_hal_context_t *hal)
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{
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hal->dev = &USB_WRAP;
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_usb_wrap_ll_enable_bus_clock(true);
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_usb_wrap_ll_reset_register();
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#if !USB_WRAP_LL_EXT_PHY_SUPPORTED
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usb_wrap_ll_phy_set_defaults(hal->dev);
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#endif
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}
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void _usb_wrap_hal_disable(void)
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{
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_usb_wrap_ll_enable_bus_clock(false);
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}
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#if USB_WRAP_LL_EXT_PHY_SUPPORTED
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void usb_wrap_hal_phy_set_external(usb_wrap_hal_context_t *hal, bool external)
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{
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if (external) {
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usb_wrap_ll_phy_enable_external(hal->dev, true);
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} else {
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usb_wrap_ll_phy_enable_external(hal->dev, false);
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usb_wrap_ll_phy_enable_pad(hal->dev, true);
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}
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}
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#endif // USB_WRAP_LL_EXT_PHY_SUPPORTED
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