mirror of
https://github.com/espressif/esp-idf.git
synced 2026-04-27 11:03:11 +00:00
wuzhenghui
6f1bea6a5d
1. introduce reconfigure_ticks function for wdt configuration 2. move esp32eco3 cache livelock workaround code out from int_wdt.c
190 lines
6.8 KiB
C
190 lines
6.8 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include <stdio.h>
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#include <stdbool.h>
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#include "sdkconfig.h"
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#include "soc/soc_caps.h"
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#include "hal/mwdt_periph.h"
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#include "hal/wdt_hal.h"
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#include "soc/system_intr.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/portmacro.h"
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#include "esp_cpu.h"
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#include "esp_check.h"
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#include "esp_err.h"
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#include "esp_private/esp_system_attr.h"
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#include "esp_log.h"
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#include "esp_intr_alloc.h"
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#include "esp_chip_info.h"
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#include "esp_freertos_hooks.h"
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#include "esp_private/periph_ctrl.h"
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#include "esp_private/esp_int_wdt.h"
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#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && SOC_MWDT_SUPPORT_SLEEP_RETENTION
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#include "esp_private/sleep_retention.h"
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#endif
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#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
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#include "esp_private/eco3_livelock_workaround.h"
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#endif
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#if TIMG_LL_GET(INST_NUM) > 1
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/* If we have two hardware timer groups, use the second one for interrupt watchdog. */
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#define WDT_LEVEL_INTR_SOURCE SYS_TG1_WDT_INTR_SOURCE
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#define IWDT_PRESCALER MWDT_LL_DEFAULT_CLK_PRESCALER // Tick period of 500us if WDT source clock is 80MHz
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#define IWDT_INSTANCE WDT_MWDT1
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#define IWDT_PERIPH PERIPH_TIMG1_MODULE
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#define IWDT_TIMER_GROUP 1
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#else
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#define WDT_LEVEL_INTR_SOURCE SYS_TG0_WDT_INTR_SOURCE
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#define IWDT_PRESCALER MWDT_LL_DEFAULT_CLK_PRESCALER // Tick period of 500us if WDT source clock is 80MHz
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#define IWDT_INSTANCE WDT_MWDT0
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#define IWDT_PERIPH PERIPH_TIMG0_MODULE
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#define IWDT_TIMER_GROUP 0
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#endif // TIMG_LL_GET(INST_NUM) > 1
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#if CONFIG_ESP_INT_WDT
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#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && SOC_MWDT_SUPPORT_SLEEP_RETENTION
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ESP_LOG_ATTR_TAG(TAG, "int_wdt");
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static esp_err_t sleep_int_wdt_retention_init(void *arg)
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{
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uint32_t group_id = *(uint32_t *)arg;
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esp_err_t err = sleep_retention_entries_create(tg_wdt_regs_retention[group_id].link_list,
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tg_wdt_regs_retention[group_id].link_num,
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REGDMA_LINK_PRI_SYS_PERIPH_LOW,
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(group_id == 0) ? SLEEP_RETENTION_MODULE_TG0_WDT : SLEEP_RETENTION_MODULE_TG1_WDT);
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if (err == ESP_OK) {
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ESP_LOGD(TAG, "Interrupt watchdog timer retention initialization");
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}
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ESP_RETURN_ON_ERROR(err, TAG, "Failed to create sleep retention linked list for interrupt watchdog timer");
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return err;
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}
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static esp_err_t esp_int_wdt_retention_enable(uint32_t group_id)
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{
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sleep_retention_module_init_param_t init_param = {
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.cbs = { .create = { .handle = sleep_int_wdt_retention_init, .arg = &group_id } },
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.depends = RETENTION_MODULE_BITMAP_INIT(CLOCK_SYSTEM)
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};
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esp_err_t err = sleep_retention_module_init((group_id == 0) ? SLEEP_RETENTION_MODULE_TG0_WDT : SLEEP_RETENTION_MODULE_TG1_WDT, &init_param);
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if (err == ESP_OK) {
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err = sleep_retention_module_allocate((group_id == 0) ? SLEEP_RETENTION_MODULE_TG0_WDT : SLEEP_RETENTION_MODULE_TG1_WDT);
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if (err != ESP_OK) {
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ESP_LOGW(TAG, "Failed to allocate sleep retention linked list for interrupt watchdog timer retention");
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}
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}
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return err;
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}
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#endif
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static wdt_hal_context_t iwdt_context;
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static portMUX_TYPE s_iwdt_configure_lock = portMUX_INITIALIZER_UNLOCKED;
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static void ESP_SYSTEM_IRAM_ATTR reconfigure_ticks(uint32_t stage0_ticks, uint32_t stage1_ticks)
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{
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portENTER_CRITICAL_SAFE(&s_iwdt_configure_lock);
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wdt_hal_write_protect_disable(&iwdt_context);
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wdt_hal_config_stage(&iwdt_context, WDT_STAGE0, stage0_ticks, WDT_STAGE_ACTION_INT);
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wdt_hal_config_stage(&iwdt_context, WDT_STAGE1, stage1_ticks, WDT_STAGE_ACTION_RESET_SYSTEM);
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wdt_hal_feed(&iwdt_context);
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wdt_hal_write_protect_enable(&iwdt_context);
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portEXIT_CRITICAL_SAFE(&s_iwdt_configure_lock);
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}
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#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
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void ESP_SYSTEM_IRAM_ATTR esp_int_wdt_reconfigure_ticks(uint32_t stage0_ticks, uint32_t stage1_ticks)
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{
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reconfigure_ticks(stage0_ticks, stage1_ticks);
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}
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#endif
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#if CONFIG_ESP_INT_WDT_CHECK_CPU1
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volatile bool int_wdt_cpu1_ticked = false;
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#endif
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static void ESP_SYSTEM_IRAM_ATTR tick_hook(void)
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{
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if (esp_cpu_get_core_id() != 0) {
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#if CONFIG_ESP_INT_WDT_CHECK_CPU1
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int_wdt_cpu1_ticked = true;
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#endif
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return;
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}
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#if CONFIG_ESP_INT_WDT_CHECK_CPU1
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if (int_wdt_cpu1_ticked) {
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int_wdt_cpu1_ticked = false;
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} else {
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return;
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}
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#endif
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#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
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esp_int_wdt_set_livelock_params(CONFIG_ESP_INT_WDT_TIMEOUT_MS);
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reconfigure_ticks(esp_int_wdt_livelock_get_feed_stage0_ticks(), IWDT_STAGE1_TIMEOUT_US);
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#else
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reconfigure_ticks(IWDT_STAGE0_TIMEOUT_US, IWDT_STAGE1_TIMEOUT_US);
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#endif
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}
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void esp_int_wdt_init(void)
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{
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PERIPH_RCC_ACQUIRE_ATOMIC(IWDT_PERIPH, ref_count) {
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if (ref_count == 0) {
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timg_ll_enable_bus_clock(IWDT_TIMER_GROUP, true);
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timg_ll_reset_register(IWDT_TIMER_GROUP);
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}
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}
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/*
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* Initialize the WDT timeout stages. Note that the initial timeout is set to 5 seconds as variable startup times of
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* each CPU can lead to a timeout. The tick hooks will set the WDT timers to the actual timeout.
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* Todo: Fix this
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*/
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wdt_hal_init(&iwdt_context, IWDT_INSTANCE, IWDT_PRESCALER, true);
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reconfigure_ticks(IWDT_INITIAL_TIMEOUT_US, IWDT_INITIAL_TIMEOUT_US);
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wdt_hal_write_protect_disable(&iwdt_context);
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wdt_hal_enable(&iwdt_context);
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wdt_hal_write_protect_enable(&iwdt_context);
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#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && SOC_MWDT_SUPPORT_SLEEP_RETENTION
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esp_int_wdt_retention_enable(IWDT_TIMER_GROUP);
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#endif
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#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
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/*
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* This is a workaround for issue WDT-3.15 in "ESP32 ECO and workarounds for
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* Bugs" document.
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*/
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esp_int_wdt_init_for_livelock_fix();
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esp_int_wdt_set_livelock_params(CONFIG_ESP_INT_WDT_TIMEOUT_MS);
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#endif
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}
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void esp_int_wdt_cpu_init(void)
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{
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assert((CONFIG_ESP_INT_WDT_TIMEOUT_MS >= (portTICK_PERIOD_MS << 1)) && "Interrupt watchdog timeout needs to be at least twice the RTOS tick period!");
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// Register tick hook for current CPU to feed the INT WDT
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esp_register_freertos_tick_hook_for_cpu(tick_hook, esp_cpu_get_core_id());
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/*
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* Register INT WDT interrupt for current CPU. We do this manually as the timeout interrupt should call an assembly
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* panic handler (see riscv/vector.S and xtensa_vectors.S).
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*/
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esp_intr_disable_source(ETS_INT_WDT_INUM);
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esp_rom_route_intr_matrix(esp_cpu_get_core_id(), WDT_LEVEL_INTR_SOURCE, ETS_INT_WDT_INUM);
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#if SOC_CPU_HAS_FLEXIBLE_INTC
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esp_cpu_intr_set_type(ETS_INT_WDT_INUM, INTR_TYPE_LEVEL);
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esp_cpu_intr_set_priority(ETS_INT_WDT_INUM, SOC_INTERRUPT_LEVEL_MEDIUM);
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#endif
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esp_intr_enable_source(ETS_INT_WDT_INUM);
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}
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#endif // CONFIG_ESP_INT_WDT
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