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Konstantin Kondrashov b40aae66e3 fix(esp32): Fix access to MALLOC_CAP_IRAM_8BIT byte array in loop 
The Xtensa load/store handler did not properly handle 8/16-bit
memory access to IRAM regions configured with MALLOC_CAP_IRAM_8BIT
(and CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY=y) from a loop
(LBEG/LEND/LCOUNT) context. This caused the loop to exit after
the first access, instead of continuing to iterate as intended.

Closes https://github.com/espressif/esp-idf/issues/14127
2026-02-13 16:12:58 +02:00
..
baremetal
…
deprecated_include
change(xtensa): Deprecate ".../xtensa_timer.h" include path
2023-11-30 21:58:52 +08:00
esp32
fix(gdbstub): xtensa: fix FPU registers read and write
2026-02-02 10:49:16 +07:00
esp32s2
refactor(xtensa): Rename specreg.h register macros
2025-06-17 15:37:33 +02:00
esp32s3
fix(gdbstub): xtensa: fix FPU registers read and write
2026-02-02 10:49:16 +07:00
include
fix(esp32): Fix access to MALLOC_CAP_IRAM_8BIT byte array in loop
2026-02-13 16:12:58 +02:00
test_apps/include
refactor: Remove idf_test component
2026-01-01 02:26:42 +08:00
trax
feat: Update esptool to v5
2025-09-30 15:28:55 +02:00
CMakeLists.txt
change(xtensa): use add_prebuilt_library to add blobs
2025-07-17 09:33:21 +08:00
eri.c
feat(license): Dual-license source files built by OpenOCD stub flasher
2024-01-15 23:45:23 +01:00
linker.lf
…
project_include.cmake
fix(xtensa/cmake): do not include project_include.cmake if the architecture is not xtensa
2025-10-30 17:17:49 +08:00
xt_trax.c
…
xtensa_context.S
refactor(xtensa): Rename specreg.h register macros
2025-06-17 15:37:33 +02:00
xtensa_intr_asm.S
refactor(xtensa): Rename specreg.h register macros
2025-06-17 15:37:33 +02:00
xtensa_intr.c
change(app_trace): move sysview to component registry
2025-11-10 15:55:41 +08:00
xtensa_loadstore_handler.S
fix(esp32): Fix access to MALLOC_CAP_IRAM_8BIT byte array in loop
2026-02-13 16:12:58 +02:00
xtensa_vectors.S
fix(esp32): Fix access to MALLOC_CAP_IRAM_8BIT byte array in loop
2026-02-13 16:12:58 +02:00