mirror of
https://github.com/espressif/esp-idf.git
synced 2026-04-28 19:34:59 +00:00
nilesh.kale
a6a2696972
PMP entry 3 (SOC_DROM_MASK_HIGH, TOR mode) in the memprot path was incorrectly granted RW permission on esp32h21 and esp32c61. The mask ROM data region is inherently read-only; remove the W bit. Also added necessary tests to check voilations and re-enabled tests for ESP32P4
92 lines
2.3 KiB
C
92 lines
2.3 KiB
C
/*
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* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include "sdkconfig.h"
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#include "soc/soc_caps.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
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#define SOC_DCACHE_SUPPORTED (1)
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#endif
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/* Functions testing memprot peripheral: memory regions and illegal operations on them */
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void test_dcache_read_violation(void);
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void test_dcache_write_violation(void);
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void test_iram_reg1_write_violation(void);
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void test_iram_reg2_write_violation(void);
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void test_iram_reg3_write_violation(void);
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#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
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void test_non_cache_iram_reg1_write_violation(void);
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void test_non_cache_iram_reg2_write_violation(void);
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void test_non_cache_iram_reg3_write_violation(void);
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void test_non_cache_iram_reg4_write_violation(void);
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#endif
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void test_iram_reg4_write_violation(void);
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void test_dram_reg1_execute_violation(void);
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void test_dram_reg2_execute_violation(void);
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#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
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void test_non_cache_dram_reg1_execute_violation(void);
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void test_non_cache_dram_reg2_execute_violation(void);
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#endif
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void test_rtc_fast_reg1_execute_violation(void);
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void test_rtc_fast_reg2_execute_violation(void);
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void test_rtc_fast_reg3_execute_violation(void);
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void test_rtc_slow_reg1_execute_violation(void);
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void test_rtc_slow_reg2_execute_violation(void);
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void test_irom_reg_write_violation(void);
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void test_spiram_xip_irom_alignment_reg_execute_violation(void);
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void test_spiram_xip_drom_alignment_reg_execute_violation(void);
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void test_irom_mask_reg_write_violation(void);
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#ifdef SOC_DROM_MASK_HIGH
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void test_drom_mask_reg_write_violation(void);
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#endif
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void test_drom_reg_write_violation(void);
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void test_drom_reg_execute_violation(void);
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#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
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void test_non_cache_irom_reg_write_violation(void);
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void test_non_cache_drom_reg_write_violation(void);
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void test_non_cache_drom_reg_execute_violation(void);
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void test_non_cache_spiram_xip_irom_alignment_reg_execute_violation(void);
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void test_non_cache_spiram_xip_drom_alignment_reg_execute_violation(void);
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#endif
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void test_invalid_memory_region_write_violation(void);
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void test_invalid_memory_region_execute_violation(void);
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#ifdef __cplusplus
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}
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#endif
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