mirror of
https://github.com/espressif/esp-idf.git
synced 2026-04-27 19:13:21 +00:00
Ma Jing Jing
357 lines
10 KiB
C
357 lines
10 KiB
C
/*
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* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdbool.h>
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#include "soc/asrc_struct.h"
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#include "soc/pcr_struct.h"
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#include "hal/assert.h"
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#include "hal/asrc_periph.h"
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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#define ASRC_LL_GET_HW() (&ASRC)
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#define ASRC_LL_STREAM_NUM (2)
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/**
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* @brief ASRC interrupt types
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*/
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typedef enum {
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ASRC_LL_INTR_OUTCNT_EOF = (1 << 0), /**< Output counter EOF interrupt */
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} asrc_ll_intr_type_t;
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/**
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* @brief Convert sample rate to table index
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*
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* @param[in] rate Sample rate in Hz (8000/16000/24000/32000/44100/48000)
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*
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* @return
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* - Table index
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* - -1 if rate not supported
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*/
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static inline int8_t asrc_ll_get_rate_index(uint32_t rate)
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{
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int32_t idx = rate / 8000;
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if (idx == 5) {
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return (rate == 44100) ? 4 : -1;
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}
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if (idx && rate == idx * 8000 && idx <= 6) {
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return idx - 1;
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}
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return -1;
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}
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/**
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* @brief Reset ASRC module
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*
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* @param[in] hw Peripheral ASRC hardware instance address
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*/
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static inline void asrc_ll_reset_asrc_module(asrc_dev_t *hw)
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{
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PCR.asrc_func_clk_conf.asrc_rst_en = 1;
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PCR.asrc_func_clk_conf.asrc_rst_en = 0;
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}
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/**
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* @brief Enable the bus clock for the ASRC module
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*
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* @param[in] enable Enable the bus clock
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*/
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static inline void asrc_ll_enable_asrc_module(bool enable)
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{
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PCR.asrc_func_clk_conf.asrc_apb_clk_en = enable;
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PCR.asrc_func_clk_conf.asrc_func_clk_en = enable;
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}
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/**
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* @brief Force enable the register clock for the ASRC module
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*
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* @param[in] hw Peripheral ASRC hardware instance address
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* @param[in] enable Enable the register clock
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*/
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static inline void asrc_ll_force_enable_reg_clock(asrc_dev_t *hw, bool enable)
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{
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hw->sys.clk_en = enable;
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}
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/**
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* @brief Reset specific ASRC stream
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*
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* @param[in] hw Peripheral ASRC hardware instance address
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* @param[in] asrc_idx ASRC stream index
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*/
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static inline void asrc_ll_reset_stream(asrc_dev_t *hw, uint8_t asrc_idx)
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{
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hw->asrc_para[asrc_idx].cfg3.reset = 1;
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hw->asrc_para[asrc_idx].cfg3.reset = 0;
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}
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/**
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* @brief Start ASRC processing
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*
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* @param[in] hw Peripheral ASRC hardware instance address
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* @param[in] asrc_idx ASRC stream index
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*/
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static inline void asrc_ll_start_stream(asrc_dev_t *hw, uint8_t asrc_idx)
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{
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hw->asrc_para[asrc_idx].cfg4.start = 1;
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}
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/**
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* @brief Stop ASRC processing
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*
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* @param[in] hw Peripheral ASRC hardware instance address
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* @param[in] asrc_idx ASRC stream index
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*/
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static inline void asrc_ll_stop_stream(asrc_dev_t *hw, uint8_t asrc_idx)
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{
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hw->asrc_para[asrc_idx].cfg4.start = 0;
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}
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/**
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* @brief Set ASRC rate register
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*
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* @param[in] hw Peripheral ASRC hardware instance address
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* @param[in] asrc_idx ASRC stream index
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* @param[in] src_rate Source sample rate
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* @param[in] dest_rate Destination sample rate
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*/
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static inline void asrc_ll_set_rate_reg(asrc_dev_t *hw, uint8_t asrc_idx, uint32_t src_rate, uint32_t dest_rate)
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{
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int8_t src_idx = asrc_ll_get_rate_index(src_rate);
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int8_t dest_idx = asrc_ll_get_rate_index(dest_rate);
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HAL_ASSERT(src_idx != -1 && dest_idx != -1);
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const asrc_periph_rate_config_t *config = &asrc_periph_rate_table[src_idx][dest_idx];
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hw->asrc_para[asrc_idx].cfg0.rs2_stg0_bypass = config->stg0_bypass;
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hw->asrc_para[asrc_idx].cfg0.rs2_stg1_bypass = config->stg1_bypass;
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hw->asrc_para[asrc_idx].cfg0.rs2_stg0_mode = config->stg0_mode;
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hw->asrc_para[asrc_idx].cfg0.rs2_stg1_mode = config->stg1_mode;
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hw->asrc_para[asrc_idx].cfg0.frac_bypass = config->frac_bypass;
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hw->asrc_para[asrc_idx].cfg0.frac_ahead = config->frac_ahead;
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hw->asrc_para[asrc_idx].cfg1.frac_m = config->frac_m;
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hw->asrc_para[asrc_idx].cfg1.frac_l = config->frac_l;
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hw->asrc_para[asrc_idx].cfg2.frac_recipl = config->frac_recipl;
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}
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/**
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* @brief Set ASRC channel mode configuration
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*
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* @param[in] hw Peripheral ASRC hardware instance address
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* @param[in] asrc_idx ASRC stream index
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* @param[in] src_ch Source channel number
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* @param[in] dest_ch Destination channel number
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* @param[in] weight Weight array
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* @param[in] weight_len Weight array length
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*/
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static inline void asrc_ll_set_channel_mode(asrc_dev_t *hw, uint8_t asrc_idx, uint8_t src_ch,
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uint8_t dest_ch, float *weight, uint8_t weight_len)
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{
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if (src_ch == 1 && dest_ch == 1) {
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// Mode 0: Mono to Mono (1 channel -> 1 channel)
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hw->asrc_para[asrc_idx].cfg0.mode = 0;
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} else if (src_ch == 1 && dest_ch == 2) {
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// Mode 2: Mono to Dual (1 channel -> 2 channels, duplicate mono channel to both outputs)
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hw->asrc_para[asrc_idx].cfg0.mode = 2;
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} else if (src_ch == 2 && dest_ch == 1) {
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// Mode 3: Dual to Mono (2 channels -> 1 channel)
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// ch_sel determines channel selection: 0 = select channel 0 only, 1 = mix both channels
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HAL_ASSERT(weight_len == 2);
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uint32_t ch_sel = (weight[0] == 1.0f && weight[1] == 0.0f) ? 0 : 1;
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hw->asrc_para[asrc_idx].cfg0.mode = 3;
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hw->asrc_para[asrc_idx].cfg0.sel = ch_sel;
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} else {
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// Mode 1: Dual to Dual (2 channels -> 2 channels)
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hw->asrc_para[asrc_idx].cfg0.mode = 1;
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}
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}
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/**
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* @brief Clear input samples counter register
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*
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* @param[in] hw Peripheral ASRC hardware instance address
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* @param[in] asrc_idx ASRC stream index
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*/
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static inline void asrc_ll_clear_incnt_counter(asrc_dev_t *hw, uint8_t asrc_idx)
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{
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hw->asrc_para[asrc_idx].cfg5.in_cnt_clr = 1;
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}
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/**
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* @brief Enable input samples counter register
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*
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* @param[in] hw Peripheral ASRC hardware instance address
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* @param[in] asrc_idx ASRC stream index
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*/
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static inline void asrc_ll_enable_incnt_counter(asrc_dev_t *hw, uint8_t asrc_idx)
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{
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hw->asrc_para[asrc_idx].cfg5.in_cnt_ena = 1;
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}
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/**
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* @brief Set expected input samples count register
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*
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* @param[in] hw Peripheral ASRC hardware instance address
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* @param[in] asrc_idx ASRC stream index
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* @param[in] in_bytes_num Number of input samples expected
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*/
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static inline void asrc_ll_set_in_bytes_num(asrc_dev_t *hw, uint8_t asrc_idx, uint32_t in_bytes_num)
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{
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hw->asrc_para[asrc_idx].cfg5.in_samples = in_bytes_num;
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}
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/**
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* @brief Clear output samples counter register
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*
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* @param[in] hw Peripheral ASRC hardware instance address
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* @param[in] asrc_idx ASRC stream index
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*/
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static inline void asrc_ll_clear_outcnt_counter(asrc_dev_t *hw, uint8_t asrc_idx)
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{
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hw->asrc_para[asrc_idx].cfg6.out_cnt_clr = 1;
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}
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/**
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* @brief Enable output samples counter register
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*
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* @param[in] hw Peripheral ASRC hardware instance address
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* @param[in] asrc_idx ASRC stream index
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*/
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static inline void asrc_ll_enable_outcnt_counter(asrc_dev_t *hw, uint8_t asrc_idx)
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{
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hw->asrc_para[asrc_idx].cfg6.out_cnt_ena = 1;
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}
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/**
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* @brief Enable output samples counter compensation register
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*
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* @param[in] hw Peripheral ASRC hardware instance address
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* @param[in] asrc_idx ASRC stream index
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*/
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static inline void asrc_ll_enable_outsample_comp(asrc_dev_t *hw, uint8_t asrc_idx)
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{
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hw->asrc_para[asrc_idx].cfg6.out_samples_comp = 1;
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}
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/**
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* @brief Set expected output sample count register
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*
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* @param[in] hw Peripheral ASRC hardware instance address
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* @param[in] asrc_idx ASRC stream index
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* @param[in] out_bytes_num Number of output samples expected
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*/
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static inline void asrc_ll_set_out_bytes_num(asrc_dev_t *hw, uint8_t asrc_idx, uint32_t out_bytes_num)
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{
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hw->asrc_para[asrc_idx].cfg6.out_samples = out_bytes_num;
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}
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/**
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* @brief Set EOF (End of Frame) generation mode
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*
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* @param[in] hw Peripheral ASRC hardware instance address
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* @param[in] asrc_idx ASRC stream index
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* @param[in] eof_mode EOF generation mode
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*/
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static inline void asrc_ll_set_eof_mode(asrc_dev_t *hw, uint8_t asrc_idx, uint32_t eof_mode)
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{
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hw->asrc_para[asrc_idx].cfg6.out_eof_gen_mode = eof_mode;
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}
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/**
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* @brief Reset input fifo
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*
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* @param[in] hw Peripheral ASRC hardware instance address
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* @param[in] asrc_idx ASRC stream index
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*/
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static inline void asrc_ll_reset_input_fifo(asrc_dev_t *hw, uint8_t asrc_idx)
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{
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hw->asrc_para[asrc_idx].fifo_ctrl.infifo_reset = 1;
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hw->asrc_para[asrc_idx].fifo_ctrl.infifo_reset = 0;
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}
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/**
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* @brief Reset output fifo
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*
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* @param[in] hw Peripheral ASRC hardware instance address
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* @param[in] asrc_idx ASRC stream index
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*/
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static inline void asrc_ll_reset_output_fifo(asrc_dev_t *hw, uint8_t asrc_idx)
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{
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hw->asrc_para[asrc_idx].fifo_ctrl.outfifo_reset = 1;
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hw->asrc_para[asrc_idx].fifo_ctrl.outfifo_reset = 0;
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}
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/**
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* @brief Enable ASRC interrupt
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*
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* @param[in] hw Pointer to ASRC hardware.
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* @param[in] asrc_idx ASRC stream index
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* @param[in] mask Interrupt mask to enable
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*/
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static inline void asrc_ll_enable_intr_mask(asrc_dev_t *hw, uint8_t asrc_idx, uint32_t mask)
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{
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hw->asrc_para[asrc_idx].int_ena.val |= mask;
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}
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/**
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* @brief Clear ASRC interrupt
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*
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* @param[in] hw Pointer to ASRC hardware.
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* @param[in] asrc_idx ASRC stream index
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* @param[in] mask Interrupt mask to clear
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*/
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static inline void asrc_ll_clear_intr_mask(asrc_dev_t *hw, uint8_t asrc_idx, uint32_t mask)
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{
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hw->asrc_para[asrc_idx].int_clr.val = mask;
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}
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/**
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* @brief Disable ASRC interrupt
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*
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* @param[in] hw Pointer to ASRC hardware.
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* @param[in] asrc_idx ASRC stream index
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* @param[in] mask Interrupt mask to disable
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*/
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static inline void asrc_ll_disable_intr_mask(asrc_dev_t *hw, uint8_t asrc_idx, uint32_t mask)
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{
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hw->asrc_para[asrc_idx].int_ena.val &= (~mask);
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}
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/**
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* @brief Get ASRC interrupt status
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*
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* @param[in] hw Pointer to ASRC hardware.
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* @param[in] asrc_idx ASRC stream index
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*
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* @return
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* - Interrupt status (masked)
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*/
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static inline uint32_t asrc_ll_get_intr_status(asrc_dev_t *hw, uint8_t asrc_idx)
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{
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return hw->asrc_para[asrc_idx].int_st.val;
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}
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/**
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* @brief Get current output sample count
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*
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* @param[in] hw Peripheral ASRC hardware instance address
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* @param[in] asrc_idx ASRC stream index
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*
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* @return
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* - Current output samples count
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*/
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static inline uint32_t asrc_ll_get_outbytes_cnt(asrc_dev_t *hw, uint8_t asrc_idx)
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{
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uint32_t out_cnt = hw->asrc_para[asrc_idx].out_cnt.out_cnt;
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return out_cnt;
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}
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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