mirror of
https://github.com/espressif/esp-idf.git
synced 2026-04-27 19:13:21 +00:00
Song Ruo Jing
125 lines
3.6 KiB
C
125 lines
3.6 KiB
C
/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* Background
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*
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* This file is for the MSPI related, but not Flash driver related registers, these registers:
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* - may influence both Flash and PSRAM
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* - not related or directly related to Flash controller driver
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*
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* Some hints for naming convention:
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* - For MSPI timing tuning related registers, the LL should start with `mspi_timing_ll_`
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* - For others, the LL should start with `mspi_ll_`
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*/
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#pragma once
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#include <stdint.h>
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#include <stdbool.h>
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#include "soc/soc.h"
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#include "soc/clk_tree_defs.h"
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#include "soc/pcr_struct.h"
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#include "soc/spi_mem_struct.h"
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#include "hal/misc.h"
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#include "hal/assert.h"
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#define MSPI_LL_ADDR_INT_SUPPORTED 1
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#define MSPI_LL_PMS_INT_SUPPORTED 1
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#define MSPI_LL_ECC_INT_SUPPORTED 1
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#define MSPI_LL_PERIPH_NUM 2
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#define MSPI_TIMING_LL_MSPI_ID_0 0
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#define MSPI_TIMING_LL_MSPI_ID_1 1
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#define MSPI_LL_EVENT_SLV_ST_END (1<<3)
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#define MSPI_LL_EVENT_MST_ST_END (1<<4)
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#define MSPI_LL_EVENT_ECC_ERR (1<<5)
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#define MSPI_LL_EVENT_PMS_REJECT (1<<6)
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#define MSPI_LL_EVENT_AXI_RADDR_ERR (1<<7)
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#define MSPI_LL_EVENT_AXI_WR_FLASH_ERR (1<<8)
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#define MSPI_LL_EVENT_AXI_WADDR_ERR (1<<9)
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#define MSPI_LL_EVENT_MASK (MSPI_LL_EVENT_ECC_ERR | MSPI_LL_EVENT_PMS_REJECT | MSPI_LL_EVENT_AXI_RADDR_ERR | \
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MSPI_LL_EVENT_AXI_WR_FLASH_ERR | MSPI_LL_EVENT_AXI_WADDR_ERR)
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#define MSPI_LL_INTR_EVENT_SUPPORTED 1
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#define MSPI_LL_INTR_SHARED 1
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#ifdef __cplusplus
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extern "C" {
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#endif
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/************************** MSPI pll clock configurations **************************/
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/*
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* @brief Select FLASH clock source
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*
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* @param mspi_id mspi_id
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* @param clk_src clock source, see valid sources in type `soc_periph_flash_clk_src_t`
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*/
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__attribute__((always_inline))
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static inline void _mspi_timing_ll_set_flash_clk_src(uint32_t mspi_id, soc_periph_flash_clk_src_t clk_src)
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{
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HAL_ASSERT(mspi_id == 0);
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switch (clk_src) {
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case FLASH_CLK_SRC_XTAL:
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PCR.mspi_clk_conf.mspi_func_clk_sel = 0;
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break;
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case FLASH_CLK_SRC_RC_FAST:
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PCR.mspi_clk_conf.mspi_func_clk_sel = 1;
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break;
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case FLASH_CLK_SRC_REF_F64M:
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PCR.mspi_clk_conf.mspi_func_clk_sel = 2;
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break;
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case FLASH_CLK_SRC_PLL_F48M:
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PCR.mspi_clk_conf.mspi_func_clk_sel = 3;
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break;
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default:
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HAL_ASSERT(false);
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}
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}
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/**
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* @brief Enable/Disable MSPI controller interrupt
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*
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* @param mspi_id mspi_id
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* @param intr_mask interrupt mask
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* @param enable enable / disable
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*/
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__attribute__((always_inline))
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static inline void mspi_ll_enable_intr(uint8_t spi_num, uint32_t intr_mask, bool enable)
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{
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if (enable) {
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SPIMEM0.int_ena.val |= intr_mask;
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} else {
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SPIMEM0.int_ena.val &= ~intr_mask;
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}
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}
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/**
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* @brief Clear MSPI controller interrupt
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*
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* @param mspi_id mspi_id
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* @param intr_mask interrupt mask
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*/
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__attribute__((always_inline))
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static inline void mspi_ll_clear_intr(uint8_t spi_num, uint32_t intr_mask)
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{
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SPIMEM0.int_clr.val = intr_mask;
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}
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/**
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* @brief Get MSPI controller interrupt raw
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*
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* @param mspi_id mspi_id
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*/
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__attribute__((always_inline))
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static inline uint32_t mspi_ll_get_intr_raw(uint8_t spi_num)
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{
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return SPIMEM0.int_raw.val;
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}
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#ifdef __cplusplus
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}
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#endif
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