Jiang Jiang Jian dfa5e5d53a Merge branch 'bugfix/esp_idf_s3_deepsleep_dead_v6.0' into 'release/v6.0' ...

fix(hal): fix the issue of dual-core contention for RTC_CNTL regs(v6.0)

See merge request espressif/esp-idf!46180

2026-03-20 10:15:14 +08:00

..

cmake

refactor(uart): split UART HAL into separate component

2026-01-04 16:02:57 +08:00

ld

fix(lp-core): fixed rtc mem conflict on p4 eco5 between app and ULP

2025-11-25 13:35:50 +05:30

lp_core

change(lp_adc): Cleanup LP ADC driver and example

2026-02-09 12:36:04 +01:00

test_apps

Merge branch 'fix/lp_core_wake_stub_pmu_sw_int_v6.0' into 'release/v6.0'

2026-03-20 09:20:50 +08:00

ulp_common

feat(ulp): Allow usage oof ADC unit 2 on RISCV co processor

2025-09-22 12:38:37 +02:00

ulp_fsm

fix(hal): fix the issue of dual-core contention for RTC_CNTL regs

2026-03-02 14:29:08 +08:00

ulp_riscv

fix(hal): fix the issue of dual-core contention for RTC_CNTL regs

2026-03-02 14:29:08 +08:00

CMakeLists.txt

refactor(clk): split clock HAL into separate component

2026-01-31 22:32:37 +08:00

component_ulp_common.cmake

ulp: added basic support for building and running a binary in the lp core

2023-03-09 10:12:23 +08:00

esp32ulp_mapgen.py

feat(esp_libc): make picolibc default libc

2025-12-06 00:08:35 +07:00

Kconfig

feat(ulp): added lp-core exception as wake-up source

2025-09-18 11:14:02 +08:00

project_include.cmake

fix(ulp): Add support for multiple ULP program embedding without name collision

2025-01-08 14:55:58 +08:00

sdkconfig.rename.esp32

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sdkconfig.rename.esp32s2

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