mirror of
https://github.com/espressif/esp-idf.git
synced 2026-04-27 19:13:21 +00:00
Chen Jichang
84 lines
2.8 KiB
C
84 lines
2.8 KiB
C
/*
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* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include "sdkconfig.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* Target-specific regi2c test configuration
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*
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* For ESP32: test with the APLL regi2c block (I2C_APLL)
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* For other targets: test with the SAR ADC calibration regi2c block (I2C_SAR_ADC / I2C_SARADC)
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*
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* Each target configuration selects:
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* - A full 8-bit register for testing read/write
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* - A partial bit-field register for testing read_mask/write_mask
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*/
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#if CONFIG_IDF_TARGET_ESP32
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#include "soc/regi2c_apll.h"
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#define TEST_BLOCK I2C_APLL
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#define TEST_HOST_ID I2C_APLL_HOSTID
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/* I2C_APLL_DSDM0: register 9, bits [7:0] — full 8-bit SDM parameter */
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#define TEST_REG_FULL I2C_APLL_DSDM0
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/* I2C_APLL_OC_DVDD: register 6, bits [4:0] — 5-bit output voltage divider */
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#define TEST_REG_MASK I2C_APLL_OC_DVDD
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#define TEST_REG_MASK_MSB I2C_APLL_OC_DVDD_MSB
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#define TEST_REG_MASK_LSB I2C_APLL_OC_DVDD_LSB
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#elif CONFIG_IDF_TARGET_ESP32H4 || CONFIG_IDF_TARGET_ESP32S31
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#include "soc/regi2c_saradc.h"
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#define TEST_BLOCK I2C_SARADC
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#define TEST_HOST_ID I2C_SARADC_HOSTID
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/* I2C_SARADC_SAR1_INIT_CODE_LSB: register 0, bits [7:0] — full 8-bit */
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#define TEST_REG_FULL I2C_SARADC_SAR1_INIT_CODE_LSB
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/* I2C_SARADC_SAR1_INIT_CODE_MSB: register 1, bits [3:0] — 4-bit field */
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#define TEST_REG_MASK I2C_SARADC_SAR1_INIT_CODE_MSB
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#define TEST_REG_MASK_MSB I2C_SARADC_SAR1_INIT_CODE_MSB_MSB
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#define TEST_REG_MASK_LSB I2C_SARADC_SAR1_INIT_CODE_MSB_LSB
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#elif CONFIG_IDF_TARGET_ESP32H21 // TODO: IDF-11590 Replace with standard SARADC register field macros once they are defined in esp32h21/regi2c_saradc.h
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#include "soc/regi2c_saradc.h"
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#define TEST_BLOCK I2C_SAR_ADC
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#define TEST_HOST_ID I2C_SAR_ADC_HOSTID
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/*
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* ESP32-H21 regi2c_saradc.h only defines block and host ID without individual
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* register field macros. Use the standard SARADC register layout directly:
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* register 0 bits [7:0] = SAR1 initial code low byte
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* register 1 bits [3:0] = SAR1 initial code high nibble
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*/
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#define TEST_REG_FULL 0
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#define TEST_REG_MASK 1
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#define TEST_REG_MASK_MSB 3
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#define TEST_REG_MASK_LSB 0
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#else
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/* Standard SARADC register naming */
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#include "soc/regi2c_saradc.h"
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#define TEST_BLOCK I2C_SAR_ADC
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#define TEST_HOST_ID I2C_SAR_ADC_HOSTID
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/* ADC_SAR1_INITIAL_CODE_LOW_ADDR: register 0x0, bits [7:0] — full 8-bit */
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#define TEST_REG_FULL ADC_SAR1_INITIAL_CODE_LOW_ADDR
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/* ADC_SAR1_DREF_ADDR: register 0x2, bits [6:4] — 3-bit reference voltage */
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#define TEST_REG_MASK ADC_SAR1_DREF_ADDR
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#define TEST_REG_MASK_MSB ADC_SAR1_DREF_ADDR_MSB
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#define TEST_REG_MASK_LSB ADC_SAR1_DREF_ADDR_LSB
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#endif
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#ifdef __cplusplus
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}
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#endif
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