mirror of
https://github.com/espressif/esp-idf.git
synced 2026-04-29 11:55:00 +00:00
wuzhenghui
177 lines
7.0 KiB
Plaintext
177 lines
7.0 KiB
Plaintext
/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* ESP32-C6 Linker Script Memory Layout
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* This file describes the memory layout (memory blocks) by virtual memory addresses.
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* This linker script is passed through the C preprocessor to include configuration options.
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* Please use preprocessor features sparingly!
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* Restrict to simple macros with numeric values, and/or #if/#endif blocks.
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*/
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#include "sdkconfig.h"
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#include "ld.common"
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#if !CONFIG_SECURE_ENABLE_TEE
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#define SRAM_SEG_START (0x40800000)
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#else
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#define SRAM_SEG_START (0x40800000 + CONFIG_SECURE_TEE_IRAM_SIZE + CONFIG_SECURE_TEE_DRAM_SIZE)
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#define FLASH_SEG_OFFSET (CONFIG_SECURE_TEE_IROM_SIZE + CONFIG_SECURE_TEE_DROM_SIZE)
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#endif // CONFIG_SECURE_ENABLE_TEE
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#define SRAM_SEG_END 0x4086E610 /* 2nd stage bootloader iram_loader_seg start address */
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#define SRAM_SEG_SIZE SRAM_SEG_END - SRAM_SEG_START
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#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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/*
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* IDRAM0_2_SEG_SIZE_DEFAULT is used when page size is 64KB
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*/
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#define IDRAM0_2_SEG_SIZE (CONFIG_MMU_PAGE_SIZE << 8)
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#endif
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MEMORY
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{
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/**
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* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
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* of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
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* are connected to the data port of the CPU and eg allow byte-wise access.
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*/
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#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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#if CONFIG_SECURE_ENABLE_TEE
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/* Flash mapped instruction data */
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irom_seg (RX) : org = 0x42000020 + FLASH_SEG_OFFSET,
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len = IDRAM0_2_SEG_SIZE - FLASH_SEG_OFFSET - 0x20
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#else
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/* Flash mapped instruction data */
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irom_seg (RX) : org = 0x42000020, len = IDRAM0_2_SEG_SIZE - 0x20
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#endif
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/**
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* (0x20 offset above is a convenience for the app binary image generation.
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* Flash cache has 64KB pages. The .bin file which is flashed to the chip
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* has a 0x18 byte file header, and each segment has a 0x08 byte segment
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* header. Setting this offset makes it simple to meet the flash cache MMU's
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* constraint that (paddr % 64KB == vaddr % 64KB).)
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*/
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#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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/**
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* Shared data RAM, excluding memory reserved for ROM bss/data/stack.
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* Enabling Bluetooth & Trace Memory features in menuconfig will decrease the amount of RAM available.
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*/
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sram_seg (RWX) : org = SRAM_SEG_START, len = SRAM_SEG_SIZE
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#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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#if CONFIG_SECURE_ENABLE_TEE
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/* Flash mapped constant data */
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drom_seg (R) : org = 0x42000020 + FLASH_SEG_OFFSET,
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len = IDRAM0_2_SEG_SIZE - FLASH_SEG_OFFSET - 0x20
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#else
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/* Flash mapped instruction data */
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drom_seg (R) : org = 0x42000020, len = IDRAM0_2_SEG_SIZE - 0x20
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#endif
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/* (See irom_seg for meaning of 0x20 offset in the above.) */
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#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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/**
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* LP RAM (RTC Memory) Layout for ESP32-C6
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* Total Size: 16KB (0x4000)
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* Address Range: 0x50000000 - 0x50004000
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*
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* The LP RAM persists over deep sleep and is used for:
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* - ULP coprocessor code and data (optional)
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* - RTC wake stub code and data
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* - Data that needs to survive deep sleep
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* - Bootloader retain memory (for reboot counter, OTA info, etc.)
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*
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* +-----------------------------+ 0x50004000 (LP RAM end)
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* | Secure Boot Image Digest |
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* | for fast wake secure boot. | ( For ROM using, must keep it at the end 32 bytes of LP RAM)
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* |(only if CONFIG_SECURE_BOOT) |
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* |- - - - - - - - - - - - - - -|
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* | bootloader_data_rtc_mem |
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* | (ESP_BOOTLOADER_RESERVE_RTC)| lp_reserved_seg (RESERVE_RTC_MEM)
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* |- - - - - - - - - - - - - - -|
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* | rtc_timer_data_in_rtc_mem |
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* | (RTC_TIMER_RESERVE_RTC=24B) |
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* +-----------------------------+ 0x50004000 - RESERVE_RTC_MEM
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* | .rtc.force_slow |
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* | .rtc_noinit (NOLOAD) |
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* | .rtc.bss (NOLOAD) |
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* | .rtc.data | lp_ram_seg (= rtc_iram_seg = rtc_data_seg = rtc_slow_seg)
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* | .rtc.force_fast |
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* |- - - - - - - - - - - - - - -|
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* | .rtc.text | RTC wake stub code
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* +-----------------------------+ 0x50000000 + CONFIG_ULP_COPROC_RESERVE_MEM (if ULP enabled)
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* | ULP Coprocessor Reserve | (Optional, CONFIG_ULP_COPROC_RESERVE_MEM)
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* | (code + data) |
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* +-----------------------------+ 0x50000000 (LP RAM start)
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*/
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/**
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* lp ram memory (RWX). Persists over deep sleep. // TODO: IDF-5667
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*/
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#if CONFIG_ULP_COPROC_ENABLED
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lp_ram_seg(RW) : org = 0x50000000 + CONFIG_ULP_COPROC_RESERVE_MEM,
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len = 0x4000 - CONFIG_ULP_COPROC_RESERVE_MEM - RESERVE_RTC_MEM
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#else
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lp_ram_seg(RW) : org = 0x50000000, len = 0x4000 - RESERVE_RTC_MEM
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#endif // CONFIG_ULP_COPROC_ENABLED
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/* We reduced the size of lp_ram_seg by RESERVE_RTC_MEM value.
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It reserves the amount of LP memory that we use for this memory segment.
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This segment is intended for keeping:
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- (lower addr) rtc timer data (s_rtc_timer_retain_mem, see esp_clk.c files).
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- (higher addr) bootloader rtc data (s_bootloader_retain_mem, when a Kconfig option is on).
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The aim of this is to keep data that will not be moved around and have a fixed address.
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*/
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lp_reserved_seg(RW) : org = 0x50000000 + 0x4000 - RESERVE_RTC_MEM, len = RESERVE_RTC_MEM
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}
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/* Heap ends at top of sram_seg */
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_heap_end = 0x40000000;
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_data_seg_org = ORIGIN(rtc_data_seg);
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/**
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* The lines below define location alias for .rtc.data section
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* C6 has no distinguished LP(RTC) fast and slow memory sections, instead, there is a unified LP_RAM section
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* Thus, the following region segments are not configurable like on other targets
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*/
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REGION_ALIAS("rtc_iram_seg", lp_ram_seg );
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REGION_ALIAS("rtc_data_seg", rtc_iram_seg );
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REGION_ALIAS("rtc_slow_seg", rtc_iram_seg );
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REGION_ALIAS("rtc_data_location", rtc_iram_seg );
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REGION_ALIAS("rtc_reserved_seg", lp_reserved_seg );
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#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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REGION_ALIAS("default_code_seg", irom_seg);
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#else
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REGION_ALIAS("default_code_seg", sram_seg);
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#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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REGION_ALIAS("default_rodata_seg", drom_seg);
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#else
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REGION_ALIAS("default_rodata_seg", sram_seg);
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#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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/**
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* If rodata default segment is placed in `drom_seg`, then flash's first rodata section must
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* also be first in the segment.
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*/
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#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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ASSERT(_flash_rodata_dummy_start == ORIGIN(default_rodata_seg),
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".flash_rodata_dummy section must be placed at the beginning of the rodata segment.")
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#endif
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#if CONFIG_ESP_SYSTEM_USE_EH_FRAME
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ASSERT ((__eh_frame_end > __eh_frame), "Error: eh_frame size is null!");
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ASSERT ((__eh_frame_hdr_end > __eh_frame_hdr), "Error: eh_frame_hdr size is null!");
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#endif
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