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esp-idf/components/esp_system/ld/esp32s2/memory.ld.in
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/*
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ESP32S2 Linker Script Memory Layout
This file describes the memory layout (memory blocks) by virtual memory addresses.
This linker script is passed through the C preprocessor to include configuration options.
Please use preprocessor features sparingly!
Restrict to simple macros with numeric values, and/or #if/#endif blocks.
*/
#include "sdkconfig.h"
#include "ld.common"
#define RAM_IRAM_START 0x40020000
#define RAM_DRAM_START 0x3FFB0000
#define DATA_RAM_END 0x3FFDE000 /* 2nd stage bootloader iram_loader_seg starts at end of block 13 (reclaimed after app boots) */
#define IRAM_ORG (RAM_IRAM_START + CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE \
+ CONFIG_ESP32S2_DATA_CACHE_SIZE)
#define DRAM_ORG (RAM_DRAM_START + CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE \
+ CONFIG_ESP32S2_DATA_CACHE_SIZE)
#define I_D_RAM_SIZE DATA_RAM_END - DRAM_ORG
#if CONFIG_ESP32S2_USE_FIXED_STATIC_RAM_SIZE
ASSERT((CONFIG_ESP32S2_FIXED_STATIC_RAM_SIZE <= I_D_RAM_SIZE), "Fixed static ram data does not fit.")
#define DRAM0_0_SEG_LEN CONFIG_ESP32S2_FIXED_STATIC_RAM_SIZE
#else
#define DRAM0_0_SEG_LEN I_D_RAM_SIZE
#endif // CONFIG_ESP32S2_USE_FIXED_STATIC_RAM_SIZE
MEMORY
{
/* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
are connected to the data port of the CPU and eg allow bytewise access. */
/* IRAM for CPU.*/
iram0_0_seg (RX) : org = IRAM_ORG, len = I_D_RAM_SIZE
#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
/* Even though the segment name is iram, it is actually mapped to flash
*/
iram0_2_seg (RX) : org = 0x40080020, len = 0x780000-0x20
/*
(0x20 offset above is a convenience for the app binary image generation.
Flash cache has 64KB pages. The .bin file which is flashed to the chip
has a 0x18 byte file header, and each segment has a 0x08 byte segment
header. Setting this offset makes it simple to meet the flash cache MMU's
constraint that (paddr % 64KB == vaddr % 64KB).)
*/
#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
/* Shared data RAM, excluding memory reserved for bootloader and ROM bss/data/stack. */
dram0_0_seg (RW) : org = DRAM_ORG, len = DRAM0_0_SEG_LEN
#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
/* Flash mapped constant data */
drom0_0_seg (R) : org = 0x3F000020, len = 0x3f0000-0x20
/* (See iram0_2_seg for meaning of 0x20 offset in the above.) */
#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
/**
* RTC Memory Layout for ESP32-S2
*
* ESP32-S2 has two separate RTC memory regions:
* 1. RTC FAST Memory: 8KB, used for RTC code and data
* 2. RTC SLOW Memory: 8KB, used for ULP coprocessor
*
* ==================== RTC FAST Memory ====================
* Size: 8KB (0x2000)
* IRAM View: 0x40070000 - 0x40072000 (executable)
* DRAM View: 0x3FF9E000 - 0x3FFA0000 (data access)
*
* +-----------------------------+ 0x40072000 / 0x3FFA0000 (RTC FAST memory end)
* | rtc_reserved_seg |
* | (RESERVE_RTC_MEM) |
* |- - - - - - - - - - - - - - -|
* | bootloader_data_rtc_mem | s_bootloader_retain_mem
* | (ESP_BOOTLOADER_RESERVE_RTC)|
* |- - - - - - - - - - - - - - -|
* | rtc_timer_data_in_rtc_mem | s_rtc_timer_retain_mem (24 bytes)
* | (RTC_TIMER_RESERVE_RTC) |
* +-----------------------------+ 0x40072000 - RESERVE_RTC_MEM
* | rtc_iram_seg / |
* | rtc_data_seg |
* |- - - - - - - - - - - - - - -|
* | .rtc.text | RTC wake stub code
* |- - - - - - - - - - - - - - -|
* | .rtc.data / .rtc.rodata | (when CONFIG_ESP32S2_RTCDATA_IN_FAST_MEM)
* |- - - - - - - - - - - - - - -|
* | .rtc.bss |
* +-----------------------------+ 0x40070000 / 0x3FF9E000 (RTC FAST memory start)
*
* ==================== RTC SLOW Memory ====================
* Size: 8KB (0x2000)
* Address: 0x50000000 - 0x50002000
*
* +-----------------------------+ 0x50002000 (RTC SLOW memory end)
* | rtc_slow_seg |
* |- - - - - - - - - - - - - - -|
* | .rtc.data / .rtc.rodata | (when !CONFIG_ESP32S2_RTCDATA_IN_FAST_MEM)
* |- - - - - - - - - - - - - - -|
* | .rtc.bss |
* +-----------------------------+ 0x50000000 + CONFIG_ULP_COPROC_RESERVE_MEM (if ULP enabled)
* | ULP Coprocessor Reserve | (Optional, CONFIG_ULP_COPROC_RESERVE_MEM)
* | (code + data) |
* +-----------------------------+ 0x50000000 (RTC SLOW memory start)
*
* RESERVE_RTC_MEM calculation:
* - RTC_TIMER_RESERVE_RTC = 24 bytes
* - ESP_BOOTLOADER_RESERVE_RTC = ALIGN_UP(CONFIG_BOOTLOADER_RESERVE_RTC_SIZE, 8)
*
* Note: RTC data can be placed in either FAST or SLOW memory based on
* CONFIG_ESP32S2_RTCDATA_IN_FAST_MEM configuration option.
*/
/* RTC fast memory (executable). Persists over deep sleep.
*/
rtc_iram_seg(RWX) : org = 0x40070000, len = 0x2000 - RESERVE_RTC_MEM
/* RTC slow memory (data accessible). Persists over deep sleep.
Start of RTC slow memory is reserved for ULP co-processor code + data, if enabled.
*/
#if CONFIG_ULP_COPROC_ENABLED
rtc_slow_seg(RW) : org = 0x50000000 + CONFIG_ULP_COPROC_RESERVE_MEM,
len = 0x2000 - CONFIG_ULP_COPROC_RESERVE_MEM
#else
rtc_slow_seg(RW) : org = 0x50000000, len = 0x2000
#endif // CONFIG_ULP_COPROC_ENABLED
/* RTC fast memory (same block as above, rtc_iram_seg), viewed from data bus */
rtc_data_seg(RW) : org = 0x3ff9e000, len = 0x2000 - RESERVE_RTC_MEM
/* We reduced the size of rtc_data_seg and rtc_iram_seg by RESERVE_RTC_MEM value.
It reserves the amount of RTC fast memory that we use for this memory segment.
This segment is intended for keeping:
- (lower addr) rtc timer data (s_rtc_timer_retain_mem, see esp_clk.c files).
- (higher addr) bootloader rtc data (s_bootloader_retain_mem, when a Kconfig option is on).
The aim of this is to keep data that will not be moved around and have a fixed address.
*/
rtc_reserved_seg(RW) : org = 0x3ff9e000 + 0x2000 - RESERVE_RTC_MEM, len = RESERVE_RTC_MEM
/* external memory, covers the dport, dram0, dram1 cacheable address space */
extern_ram_seg(RWX) : org = 0x3F800000,
len = 0x780000
}
#if defined(CONFIG_ESP32S2_USE_FIXED_STATIC_RAM_SIZE)
/* static data ends at defined address */
_heap_start = DRAM_ORG + DRAM0_0_SEG_LEN;
#else
_heap_start = _heap_low_start;
#endif
_heap_end = 0x40000000;
_data_seg_org = ORIGIN(rtc_data_seg);
/* The lines below define location alias for .rtc.data section based on Kconfig option.
When the option is not defined then use slow memory segment
else the data will be placed in fast memory segment */
#ifndef CONFIG_ESP32S2_RTCDATA_IN_FAST_MEM
REGION_ALIAS("rtc_data_location", rtc_slow_seg );
#else
REGION_ALIAS("rtc_data_location", rtc_data_seg );
#endif
#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
REGION_ALIAS("default_code_seg", iram0_2_seg);
#else
REGION_ALIAS("default_code_seg", iram0_0_seg);
#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
REGION_ALIAS("default_rodata_seg", drom0_0_seg);
#else
REGION_ALIAS("default_rodata_seg", dram0_0_seg);
#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
/**
* If rodata default segment is placed in `drom0_0_seg`, then flash's first rodata section must
* also be first in the segment.
*/
#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
ASSERT(_rodata_reserved_start == ORIGIN(default_rodata_seg),
".flash.appdesc section must be placed at the beginning of the rodata segment.")
#endif
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