mirror of
https://github.com/espressif/esp-idf.git
synced 2026-04-29 20:05:09 +00:00
Alexey Lapshin
236 lines
7.1 KiB
C
236 lines
7.1 KiB
C
/*
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* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include "sdkconfig.h"
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#include <stdint.h>
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#include <assert.h>
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#include "soc/soc.h"
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#include "soc/soc_caps.h"
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#include "esp_attr.h"
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#include "riscv/csr.h"
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#include "riscv/csr_clic.h"
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#if SOC_INT_CLIC_SUPPORTED
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#include "soc/clic_reg.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if CONFIG_SECURE_ENABLE_TEE
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#define IS_PRV_M_MODE() (RV_READ_CSR(CSR_PRV_MODE) == PRV_M)
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#else
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#define IS_PRV_M_MODE() (1UL)
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#endif
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FORCE_INLINE_ATTR void assert_valid_rv_int_num(int rv_int_num)
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{
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assert(rv_int_num < RV_EXTERNAL_INT_COUNT && "Invalid CPU interrupt number");
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}
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/* -------------------------------------------------------------------------- */
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/* Interrupt Configuration part of rv_utils */
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/* -------------------------------------------------------------------------- */
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/**
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* @brief Get the current CPU threshold level
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*/
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FORCE_INLINE_ATTR uint32_t rv_utils_get_interrupt_threshold(void)
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{
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#if INTTHRESH_STANDARD
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uint32_t threshold;
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if (IS_PRV_M_MODE()) {
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threshold = RV_READ_CSR(MINTTHRESH_CSR);
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} else {
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threshold = RV_READ_CSR(UINTTHRESH_CSR);
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}
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#else
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uint32_t threshold = REG_READ(CLIC_INT_THRESH_REG);
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#endif
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return CLIC_THRESH_TO_INT(threshold);
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}
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/**
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* @brief Set the MTVT CSR value, used as a base address for the interrupt jump table
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*/
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FORCE_INLINE_ATTR void rv_utils_set_mtvt(uint32_t mtvt_val)
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{
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RV_WRITE_CSR(MTVT_CSR, mtvt_val);
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}
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/**
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* @brief Set the XTVT CSR value (based on the current privilege mode),
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* used as a base address for the interrupt jump table
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*/
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FORCE_INLINE_ATTR void rv_utils_set_xtvt(uint32_t xtvt_val)
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{
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if (IS_PRV_M_MODE()) {
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RV_WRITE_CSR(MTVT_CSR, xtvt_val);
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} else {
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RV_WRITE_CSR(UTVT_CSR, xtvt_val);
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}
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}
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#if SOC_CPU_SUPPORT_WFE
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/**
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* @brief Set the MEXSTATUS_WFFEN value, used to enable/disable wait for event mode.
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*/
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FORCE_INLINE_ATTR void rv_utils_wfe_mode_enable(bool en)
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{
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if (en) {
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RV_SET_CSR(MEXSTATUS, MEXSTATUS_WFFEN);
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} else {
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RV_CLEAR_CSR(MEXSTATUS, MEXSTATUS_WFFEN);
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}
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}
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#endif
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/**
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* @brief Get the current CPU raw interrupt level
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*/
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FORCE_INLINE_ATTR uint32_t rv_utils_get_interrupt_level_regval(void)
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{
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if (IS_PRV_M_MODE()) {
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return RV_READ_CSR(MINTSTATUS_CSR);
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} else {
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return RV_READ_CSR(UINTSTATUS_CSR);
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}
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}
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/**
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* @brief Get the current CPU interrupt level, between 0 and 2^NLBITS - 1
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*/
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FORCE_INLINE_ATTR uint32_t rv_utils_get_interrupt_level(void)
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{
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uint32_t xintstatus;
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if (IS_PRV_M_MODE()) {
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xintstatus = RV_READ_CSR(MINTSTATUS_CSR);
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} else {
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xintstatus = RV_READ_CSR(UINTSTATUS_CSR);
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}
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/* Extract the level from this field */
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return CLIC_STATUS_TO_INT(xintstatus);
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}
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/**
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* @brief Restore the CPU interrupt level to the value returned by `rv_utils_set_intlevel_regval`.
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*
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* @note This function doesn't process its parameter, it is therefore faster than its counterpart, `rv_utils_restore_intlevel`, and should be used in places where speed is important (spinlocks, critical sections, ...)
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*
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* @param restoreval Former raw interrupt level, it is NOT necessarily a value between 0 and 7, this is hardware and configuration dependent.
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*/
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FORCE_INLINE_ATTR void rv_utils_restore_intlevel_regval(uint32_t restoreval)
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{
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#if INTTHRESH_STANDARD
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if (IS_PRV_M_MODE()) {
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RV_WRITE_CSR(MINTTHRESH_CSR, restoreval);
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} else {
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RV_WRITE_CSR(UINTTHRESH_CSR, restoreval);
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}
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#else
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REG_WRITE(CLIC_INT_THRESH_REG, restoreval);
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/**
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* After writing the threshold register, the new threshold is not directly taken into account by the CPU.
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* By executing ~8 nop instructions, or by performing a memory load right now, the previous memory write
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* operations is forced, making the new threshold active. It is then safe to re-enable MIE bit in mstatus.
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*/
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REG_READ(CLIC_INT_THRESH_REG);
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#endif
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}
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/**
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* @brief Restore the CPU interrupt level to the given priority.
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*
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* @note On the CLIC, the interrupt level mask is inclusive, so this function would mask all interrupts between 0 and `restoreval`.
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*/
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FORCE_INLINE_ATTR void rv_utils_restore_intlevel(uint32_t restoreval)
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{
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rv_utils_restore_intlevel_regval(CLIC_INT_THRESH(restoreval));
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}
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/**
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* @brief Set the interrupt threshold to `intlevel` while getting the current level.
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*
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* @note This function doesn't process its parameter nor the returned value, it is therefore faster than its counterpart, `rv_utils_set_intlevel`, and should be used in places where speed is important (spinlocks, critical sections, ...)
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*
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* @param intlevel New raw interrupt level, it is NOT necessarily a value between 0 and 7, this is hardware and configuration dependent.
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*
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* @return Current raw interrupt level, can be restored by calling `rv_utils_restore_intlevel_regval`.
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*/
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FORCE_INLINE_ATTR uint32_t rv_utils_set_intlevel_regval(uint32_t intlevel)
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{
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#if INTTHRESH_STANDARD
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if (IS_PRV_M_MODE()) {
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return RV_SWAP_CSR(MINTTHRESH_CSR, intlevel);
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} else {
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return RV_SWAP_CSR(UINTTHRESH_CSR, intlevel);
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}
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#else // !INTTHRESH_STANDARD
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uint32_t old_mstatus = RV_CLEAR_CSR(mstatus, MSTATUS_MIE);
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uint32_t old_thresh = REG_READ(CLIC_INT_THRESH_REG);
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/* This function expects the interrupt level to be available in the format needed for mintthresh reg.
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* Providing an absolute interrupt level will result in incorrect behavior.
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* See CLIC_INT_THRESH() macro for details of how the interrupt level must be provided. */
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rv_utils_restore_intlevel_regval(intlevel);
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RV_SET_CSR(mstatus, old_mstatus & MSTATUS_MIE);
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/* We return the mintthresh register value and NOT the absolute interrupt threshold level.
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* This is done to avoid extra bit manipulations during critical sections. */
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return old_thresh;
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#endif // INTTHRESH_STANDARD
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}
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FORCE_INLINE_ATTR uint32_t rv_utils_set_intlevel(uint32_t intlevel)
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{
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const uint32_t former = rv_utils_set_intlevel_regval(CLIC_INT_THRESH(intlevel));
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return CLIC_THRESH_TO_INT(former);
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}
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FORCE_INLINE_ATTR uint32_t rv_utils_mask_int_level_lower_than(uint32_t intlevel)
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{
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/* CLIC's set interrupt level is inclusive, i.e. it DOES mask the level set.
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* For example, if we want to mask interrupt level lower than 3, we have to set the intlevel to 2. */
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return rv_utils_set_intlevel(intlevel - 1);
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}
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/**
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* @brief Get the enabled interrupts on the current CPU.
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*
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* @return Bit mask of the enabled interrupts
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*/
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FORCE_INLINE_ATTR uint32_t rv_utils_intr_get_enabled_mask(void)
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{
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unsigned intr_ena_mask = 0;
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unsigned intr_num;
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for (intr_num = 0; intr_num < 32; intr_num++) {
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if (REG_GET_BIT(CLIC_INT_CTRL_REG(intr_num + CLIC_EXT_INTR_NUM_OFFSET), CLIC_INT_IE))
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intr_ena_mask |= BIT(intr_num);
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}
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return intr_ena_mask;
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}
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/**
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* @brief Acknowledge an edge interrupt
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*
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* @param intr_num Interrupt number (from 0 to 31)
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*/
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FORCE_INLINE_ATTR void rv_utils_intr_edge_ack(uint32_t intr_num)
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{
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REG_SET_BIT(CLIC_INT_CTRL_REG(intr_num + CLIC_EXT_INTR_NUM_OFFSET) , CLIC_INT_IP);
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* SOC_INT_CLIC_SUPPORTED */
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