mirror of
https://github.com/espressif/esp-idf.git
synced 2026-04-28 11:28:43 +00:00
Xiao Xufeng
230ee88d99
This commit implements a workaround that allows ESP32-C5 to run at 240MHz CPU frequency normally, while automatically reducing CPU frequency during encrypted flash writes to ensure correct operation. The frequency limit is chip revision dependent: - v1.2 and above: limited to 160MHz during encrypted writes - v1.0 and below: limited to 80MHz during encrypted writes Key implementation details: - Frequency limiting is triggered automatically when esp_flash_write_encrypted() is called - Uses start() flags (ESP_FLASH_START_FLAG_LIMIT_CPU_FREQ) to integrate with OS layer - Works with both PM enabled and disabled configurations - Frequency is automatically restored after encrypted write completes - For ESP32-C5 with 120MHz flash, Flash clock and timing registers are adjusted when CPU frequency is reduced to 80MHz - SPI1 timing registers are configured during frequency switching since encrypted writes use SPI1 and must work correctly at reduced CPU frequencies Code improvements: - Use SOC_MSPI_FREQ_AXI_CONSTRAINED capability macro instead of hardcoded chip checks - Control workaround via Kconfig (CONFIG_PM_WORKAROUND_FREQ_LIMIT_ENABLED) instead of hardcoded macros - Add comprehensive test cases covering various PM configurations and edge cases This workaround enables ESP32-C5 applications to benefit from 240MHz CPU performance while maintaining reliable encrypted flash write functionality.
186 lines
6.7 KiB
C
186 lines
6.7 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include "hal/spi_flash_hal.h"
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/** Default configuration for the memspi (high speed version) */
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#define ESP_FLASH_DEFAULT_HOST_DRIVER() (spi_flash_host_driver_t) { \
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.dev_config = spi_flash_hal_device_config, \
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.common_command = spi_flash_hal_common_command, \
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.read_id = memspi_host_read_id_hs, \
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.erase_chip = spi_flash_hal_erase_chip, \
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.erase_sector = spi_flash_hal_erase_sector, \
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.erase_block = spi_flash_hal_erase_block, \
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.read_status = memspi_host_read_status_hs, \
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.set_write_protect = spi_flash_hal_set_write_protect, \
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.supports_direct_write = spi_flash_hal_supports_direct_write, \
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.supports_direct_read = spi_flash_hal_supports_direct_read, \
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.program_page = spi_flash_hal_program_page, \
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.write_data_slicer = memspi_host_write_data_slicer, \
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.read = spi_flash_hal_read, \
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.read_data_slicer = memspi_host_read_data_slicer, \
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.host_status = spi_flash_hal_check_status, \
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.configure_host_io_mode = spi_flash_hal_configure_host_io_mode, \
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.poll_cmd_done = spi_flash_hal_poll_cmd_done, \
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.flush_cache = memspi_host_flush_cache, \
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.check_suspend = NULL, \
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.resume = spi_flash_hal_resume, \
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.suspend = spi_flash_hal_suspend,\
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.sus_setup = spi_flash_hal_setup_read_suspend,\
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}
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/// configuration for the memspi host
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typedef spi_flash_hal_config_t memspi_host_config_t;
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/// context for the memspi host
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typedef spi_flash_hal_context_t memspi_host_inst_t;
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/**
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* Initialize the memory SPI host.
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*
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* @param host Pointer to the host structure.
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* @param cfg Pointer to configuration structure
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*
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* @return always return ESP_OK
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*/
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esp_err_t memspi_host_init_pointers(memspi_host_inst_t *host, const memspi_host_config_t *cfg);
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/**
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* Initialize the memory SPI host for ESP32-C5 dynamic configuration.
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*
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* @param host Pointer to the host structure.
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*
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* @note This function is available only when CONFIG_SPI_FLASH_FREQ_LIMIT_C5_240MHZ is defined.
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* @note This function can only be called once at startup, after memspi_host_init_pointers() is called.
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* @return always return ESP_OK
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*/
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esp_err_t memspi_host_init_c5_dynamic_config(memspi_host_inst_t *host);
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/*******************************************************************************
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* NOTICE
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* Rest part of this file are part of the HAL layer
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* The HAL is not public api, don't use in application code.
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* See readme.md in hal/include/hal/readme.md
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******************************************************************************/
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/**
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* @brief Read the Status Register read from RDSR (05h).
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*
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* High speed implementation of RDID through memspi interface relying on the
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* ``common_command``.
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*
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* @param host The driver context.
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* @param id Output of the read ID from the slave.
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*
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* @return
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* - ESP_OK: if success
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* - ESP_ERR_FLASH_NO_RESPONSE: if no response from chip
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* - or other cases from ``spi_hal_common_command``
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*/
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esp_err_t memspi_host_read_id_hs(spi_flash_host_inst_t *host, uint32_t *id);
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/**
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* High speed implementation of RDSR through memspi interface relying on the
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* ``common_command``.
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*
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* @param host The driver context.
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* @param id Output of the read ID from the slave.
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*
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* @return
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* - ESP_OK: if success
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* - or other cases from ``spi_hal_common_command``
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*/
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esp_err_t memspi_host_read_status_hs(spi_flash_host_inst_t *host, uint8_t *out_sr);
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/**
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* Flush the cache (if needed) after the contents are modified.
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*
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* @param host The driver context.
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* @param addr Start address of the modified region
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* @param size Size of the region modified.
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*
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* @return always ESP_OK.
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*/
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esp_err_t memspi_host_flush_cache(spi_flash_host_inst_t *host, uint32_t addr, uint32_t size);
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/**
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* Erase contents of entire chip.
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*
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* @param host The driver context.
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*/
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void memspi_host_erase_chip(spi_flash_host_inst_t *host);
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/**
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* Erase a sector starting from a given address. For 24bit address only.
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*
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* @param host The driver context.
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* @param start_address Starting address of the sector.
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*/
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void memspi_host_erase_sector(spi_flash_host_inst_t *host, uint32_t start_address);
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/**
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* Erase a block starting from a given address. For 24bit address only.
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*
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* @param host The driver context.
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* @param start_address Starting address of the block.
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*/
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void memspi_host_erase_block(spi_flash_host_inst_t *host, uint32_t start_address);
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/**
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* Program a page with contents of a buffer. For 24bit address only.
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*
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* @param host The driver context.
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* @param buffer Buffer which contains the data to be flashed.
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* @param address Starting address of where to flash the data.
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* @param length The number of bytes to flash.
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*/
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void memspi_host_program_page(spi_flash_host_inst_t *host, const void *buffer, uint32_t address, uint32_t length);
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/**
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* Set ability to write to chip.
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*
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* @param host The driver context.
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* @param wp Enable or disable write protect (true - enable, false - disable).
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*/
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esp_err_t memspi_host_set_write_protect(spi_flash_host_inst_t *host, bool wp);
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/**
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* Read data to buffer.
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*
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* @param host The driver context.
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* @param buffer Buffer which contains the data to be read.
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* @param address Starting address of where to read the data.
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* @param length The number of bytes to read.
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*/
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esp_err_t memspi_host_read(spi_flash_host_inst_t *host, void *buffer, uint32_t address, uint32_t read_len);
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/**
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* @brief Slicer for read data used in non-encrypted regions. This slicer does nothing but
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* limit the length to the maximum size the host supports.
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*
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* @param address Flash address to read
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* @param len Length to read
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* @param align_address Output of the address to read, should be equal to the input `address`
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* @param page_size Physical SPI flash page size
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*
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* @return Length that can actually be read in one `read` call in `spi_flash_host_driver_t`.
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*/
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int memspi_host_read_data_slicer(spi_flash_host_inst_t *host, uint32_t address, uint32_t len, uint32_t *align_address, uint32_t page_size);
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/**
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* @brief Slicer for write data used in non-encrypted regions. This slicer limit the length to the
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* maximum size the host supports, and truncate if the write data lie across the page boundary
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* (256 bytes)
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*
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* @param address Flash address to write
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* @param len Length to write
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* @param align_address Output of the address to write, should be equal to the input `address`
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* @param page_size Physical SPI flash page size
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*
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* @return Length that can actually be written in one `program_page` call in `spi_flash_host_driver_t`.
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*/
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int memspi_host_write_data_slicer(spi_flash_host_inst_t *host, uint32_t address, uint32_t len, uint32_t *align_address, uint32_t page_size);
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