mirror of
https://github.com/espressif/esp-idf.git
synced 2026-04-27 19:13:21 +00:00
Song Ruo Jing
297 lines
14 KiB
C
297 lines
14 KiB
C
/*
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* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0 OR MIT
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*/
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#pragma once
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#include "modem/reg_base.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define I2C_ANA_MST_I2C0_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x0)
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/* I2C_ANA_MST_I2C0_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */
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/*description: .*/
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#define I2C_ANA_MST_I2C0_BUSY (BIT(25))
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#define I2C_ANA_MST_I2C0_BUSY_M (BIT(25))
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#define I2C_ANA_MST_I2C0_BUSY_V 0x1
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#define I2C_ANA_MST_I2C0_BUSY_S 25
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/* I2C_ANA_MST_I2C0_CTRL : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
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/*description: .*/
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#define I2C_ANA_MST_I2C0_CTRL 0x01FFFFFF
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#define I2C_ANA_MST_I2C0_CTRL_M ((I2C_ANA_MST_I2C0_CTRL_V)<<(I2C_ANA_MST_I2C0_CTRL_S))
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#define I2C_ANA_MST_I2C0_CTRL_V 0x1FFFFFF
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#define I2C_ANA_MST_I2C0_CTRL_S 0
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#define I2C_ANA_MST_I2C1_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x4)
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/* I2C_ANA_MST_I2C1_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */
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/*description: .*/
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#define I2C_ANA_MST_I2C1_BUSY (BIT(25))
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#define I2C_ANA_MST_I2C1_BUSY_M (BIT(25))
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#define I2C_ANA_MST_I2C1_BUSY_V 0x1
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#define I2C_ANA_MST_I2C1_BUSY_S 25
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/* I2C_ANA_MST_I2C1_CTRL : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
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/*description: .*/
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#define I2C_ANA_MST_I2C1_CTRL 0x01FFFFFF
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#define I2C_ANA_MST_I2C1_CTRL_M ((I2C_ANA_MST_I2C1_CTRL_V)<<(I2C_ANA_MST_I2C1_CTRL_S))
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#define I2C_ANA_MST_I2C1_CTRL_V 0x1FFFFFF
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#define I2C_ANA_MST_I2C1_CTRL_S 0
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#define I2C_ANA_MST_I2C_CTRL_REG(n) (I2C_ANA_MST_I2C0_CTRL_REG + n * 4) // 0: I2C_ANA_MST_I2C0_CTRL_REG; 1: I2C_ANA_MST_I2C1_CTRL_REG
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#define REGI2C_RTC_BUSY (BIT(25))
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#define REGI2C_RTC_BUSY_M (BIT(25))
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#define REGI2C_RTC_BUSY_V 0x1
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#define REGI2C_RTC_BUSY_S 25
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#define REGI2C_RTC_WR_CNTL (BIT(24))
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#define REGI2C_RTC_WR_CNTL_M (BIT(24))
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#define REGI2C_RTC_WR_CNTL_V 0x1
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#define REGI2C_RTC_WR_CNTL_S 24
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#define REGI2C_RTC_DATA 0x000000FF
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#define REGI2C_RTC_DATA_M ((I2C_RTC_DATA_V)<<(I2C_RTC_DATA_S))
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#define REGI2C_RTC_DATA_V 0xFF
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#define REGI2C_RTC_DATA_S 16
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#define REGI2C_RTC_ADDR 0x000000FF
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#define REGI2C_RTC_ADDR_M ((I2C_RTC_ADDR_V)<<(I2C_RTC_ADDR_S))
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#define REGI2C_RTC_ADDR_V 0xFF
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#define REGI2C_RTC_ADDR_S 8
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#define REGI2C_RTC_SLAVE_ID 0x000000FF
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#define REGI2C_RTC_SLAVE_ID_M ((I2C_RTC_SLAVE_ID_V)<<(I2C_RTC_SLAVE_ID_S))
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#define REGI2C_RTC_SLAVE_ID_V 0xFF
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#define REGI2C_RTC_SLAVE_ID_S 0
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#define I2C_ANA_MST_I2C0_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x8)
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/* I2C_ANA_MST_I2C0_STATUS : RO ;bitpos:[31:24] ;default: 8'h0 ; */
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/*description: .*/
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#define I2C_ANA_MST_I2C0_STATUS 0x000000FF
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#define I2C_ANA_MST_I2C0_STATUS_M ((I2C_ANA_MST_I2C0_STATUS_V)<<(I2C_ANA_MST_I2C0_STATUS_S))
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#define I2C_ANA_MST_I2C0_STATUS_V 0xFF
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#define I2C_ANA_MST_I2C0_STATUS_S 24
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/* I2C_ANA_MST_I2C0_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
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/*description: .*/
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#define I2C_ANA_MST_I2C0_CONF 0x00FFFFFF
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#define I2C_ANA_MST_I2C0_CONF_M ((I2C_ANA_MST_I2C0_CONF_V)<<(I2C_ANA_MST_I2C0_CONF_S))
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#define I2C_ANA_MST_I2C0_CONF_V 0xFFFFFF
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#define I2C_ANA_MST_I2C0_CONF_S 0
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#define I2C_ANA_MST_I2C1_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0xC)
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/* I2C_ANA_MST_I2C1_STATUS : RO ;bitpos:[31:24] ;default: 8'h0 ; */
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/*description: .*/
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#define I2C_ANA_MST_I2C1_STATUS 0x000000FF
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#define I2C_ANA_MST_I2C1_STATUS_M ((I2C_ANA_MST_I2C1_STATUS_V)<<(I2C_ANA_MST_I2C1_STATUS_S))
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#define I2C_ANA_MST_I2C1_STATUS_V 0xFF
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#define I2C_ANA_MST_I2C1_STATUS_S 24
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/* I2C_ANA_MST_I2C1_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
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/*description: .*/
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#define I2C_ANA_MST_I2C1_CONF 0x00FFFFFF
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#define I2C_ANA_MST_I2C1_CONF_M ((I2C_ANA_MST_I2C1_CONF_V)<<(I2C_ANA_MST_I2C1_CONF_S))
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#define I2C_ANA_MST_I2C1_CONF_V 0xFFFFFF
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#define I2C_ANA_MST_I2C1_CONF_S 0
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#define I2C_ANA_MST_I2C_BURST_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x10)
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/* I2C_ANA_MST_I2C_MST_BURST_CTRL : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
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/*description: .*/
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#define I2C_ANA_MST_I2C_MST_BURST_CTRL 0xFFFFFFFF
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#define I2C_ANA_MST_I2C_MST_BURST_CTRL_M ((I2C_ANA_MST_I2C_MST_BURST_CTRL_V)<<(I2C_ANA_MST_I2C_MST_BURST_CTRL_S))
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#define I2C_ANA_MST_I2C_MST_BURST_CTRL_V 0xFFFFFFFF
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#define I2C_ANA_MST_I2C_MST_BURST_CTRL_S 0
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#define I2C_ANA_MST_I2C_BURST_STATUS_REG (DR_REG_I2C_ANA_MST_BASE + 0x14)
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/* I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT : R/W ;bitpos:[31:20] ;default: 12'h400 ; */
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/*description: .*/
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#define I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT 0x00000FFF
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#define I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_M ((I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_V)<<(I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_S))
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#define I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_V 0xFFF
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#define I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_S 20
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/* I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG : RO ;bitpos:[2] ;default: 1'b0 ; */
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/*description: .*/
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#define I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG (BIT(2))
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#define I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_M (BIT(2))
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#define I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_V 0x1
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#define I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_S 2
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/* I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG : RO ;bitpos:[1] ;default: 1'b0 ; */
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/*description: .*/
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#define I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG (BIT(1))
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#define I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_M (BIT(1))
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#define I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_V 0x1
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#define I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_S 1
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/* I2C_ANA_MST_I2C_MST_BURST_DONE : RO ;bitpos:[0] ;default: 1'b0 ; */
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/*description: .*/
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#define I2C_ANA_MST_I2C_MST_BURST_DONE (BIT(0))
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#define I2C_ANA_MST_I2C_MST_BURST_DONE_M (BIT(0))
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#define I2C_ANA_MST_I2C_MST_BURST_DONE_V 0x1
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#define I2C_ANA_MST_I2C_MST_BURST_DONE_S 0
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#define I2C_ANA_MST_ANA_CONF0_REG (DR_REG_I2C_ANA_MST_BASE + 0x18)
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/* I2C_ANA_MST_ANA_STATUS0 : RO ;bitpos:[31:24] ;default: 8'h0 ; */
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/*description: .*/
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#define I2C_ANA_MST_ANA_STATUS0 0x000000FF
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#define I2C_ANA_MST_ANA_STATUS0_M ((I2C_ANA_MST_ANA_STATUS0_V)<<(I2C_ANA_MST_ANA_STATUS0_S))
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#define I2C_ANA_MST_ANA_STATUS0_V 0xFF
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#define I2C_ANA_MST_ANA_STATUS0_S 24
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/* I2C_ANA_MST_ANA_CONF0 : R/W ;bitpos:[23:0] ;default: 24'h00_e408 ; */
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/*description: .*/
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#define I2C_ANA_MST_ANA_CONF0 0x00FFFFFF
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#define I2C_ANA_MST_ANA_CONF0_M ((I2C_ANA_MST_ANA_CONF0_V)<<(I2C_ANA_MST_ANA_CONF0_S))
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#define I2C_ANA_MST_ANA_CONF0_V 0xFFFFFF
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#define I2C_ANA_MST_ANA_CONF0_S 0
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#define I2C_ANA_MST_ANA_CONF1_REG (DR_REG_I2C_ANA_MST_BASE + 0x1C)
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/* I2C_ANA_MST_ANA_STATUS1 : RO ;bitpos:[31:24] ;default: 8'h0 ; */
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/*description: .*/
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#define I2C_ANA_MST_ANA_STATUS1 0x000000FF
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#define I2C_ANA_MST_ANA_STATUS1_M ((I2C_ANA_MST_ANA_STATUS1_V)<<(I2C_ANA_MST_ANA_STATUS1_S))
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#define I2C_ANA_MST_ANA_STATUS1_V 0xFF
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#define I2C_ANA_MST_ANA_STATUS1_S 24
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/* I2C_ANA_MST_ANA_CONF1 : R/W ;bitpos:[23:0] ;default: 24'h00_002d ; */
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/*description: .*/
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#define I2C_ANA_MST_ANA_CONF1 0x00FFFFFF
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#define I2C_ANA_MST_ANA_CONF1_M ((I2C_ANA_MST_ANA_CONF1_V)<<(I2C_ANA_MST_ANA_CONF1_S))
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#define I2C_ANA_MST_ANA_CONF1_V 0xFFFFFF
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#define I2C_ANA_MST_ANA_CONF1_S 0
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#define I2C_ANA_MST_ANA_CONF2_REG (DR_REG_I2C_ANA_MST_BASE + 0x20)
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/* I2C_ANA_MST_ANA_STATUS2 : RO ;bitpos:[31:24] ;default: 8'h0 ; */
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/*description: .*/
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#define I2C_ANA_MST_ANA_STATUS2 0x000000FF
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#define I2C_ANA_MST_ANA_STATUS2_M ((I2C_ANA_MST_ANA_STATUS2_V)<<(I2C_ANA_MST_ANA_STATUS2_S))
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#define I2C_ANA_MST_ANA_STATUS2_V 0xFF
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#define I2C_ANA_MST_ANA_STATUS2_S 24
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/* I2C_ANA_MST_ANA_CONF2 : R/W ;bitpos:[23:0] ;default: 24'h00_0004 ; */
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/*description: .*/
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#define I2C_ANA_MST_ANA_CONF2 0x00FFFFFF
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#define I2C_ANA_MST_ANA_CONF2_M ((I2C_ANA_MST_ANA_CONF2_V)<<(I2C_ANA_MST_ANA_CONF2_S))
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#define I2C_ANA_MST_ANA_CONF2_V 0xFFFFFF
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#define I2C_ANA_MST_ANA_CONF2_S 0
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/**
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* In I2C_ANA_MST_ANA_CONF1_REG, the real slave bit position is REGI2C_xxx_BIT_MASK << REGI2C_CONF1_SLAVE_SEL_V
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* In I2C_ANA_MST_ANA_CONF2_REG, the real slave bit position is REGI2C_xxx_BIT_MASK << REGI2C_CONF2_SLAVE_SEL_V
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*/
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#define REGI2C_CONF1_SLAVE_SEL_V 2
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#define REGI2C_CONF2_SLAVE_SEL_V 4
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#define REGI2C_BB_BIT_MASK (BIT(0))
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#define REGI2C_TXRF_BIT_MASK (BIT(1))
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#define REGI2C_SDM_BIT_MASK (BIT(2))
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#define REGI2C_RFPLL_BIT_MASK (BIT(3))
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#define REGI2C_BIAS_BIT_MASK (BIT(4))
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#define REGI2C_BBPLL_BIT_MASK (BIT(5))
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#define REGI2C_ULP_BIT_MASK (BIT(6))
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#define REGI2C_SAR_MASTER_BIT_MASK (BIT(7))
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#define REGI2C_SAR_SLAVE_BIT_MASK (BIT(8))
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#define REGI2C_PERIF_BIT_MASK (BIT(9))
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#define REGI2C_APLL_BIT_MASK (BIT(10))
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#define REGI2C_CPLL_BIT_MASK (BIT(11))
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#define REGI2C_MPLL_BIT_MASK (BIT(12))
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#define REGI2C_DIG_REG_BIT_MASK (BIT(13))
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#define I2C_ANA_MST_I2C0_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x24)
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/* I2C_ANA_MST_I2C0_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */
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/*description: .*/
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#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD 0x0000001F
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#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_M ((I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_V)<<(I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_S))
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#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_V 0x1F
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#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_S 6
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/* I2C_ANA_MST_I2C0_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */
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/*description: .*/
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#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR 0x0000003F
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#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_M ((I2C_ANA_MST_I2C0_SCL_PULSE_DUR_V)<<(I2C_ANA_MST_I2C0_SCL_PULSE_DUR_S))
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#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_V 0x3F
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#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_S 0
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#define I2C_ANA_MST_I2C1_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x28)
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/* I2C_ANA_MST_I2C1_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */
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/*description: .*/
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#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD 0x0000001F
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#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_M ((I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_V)<<(I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_S))
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#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_V 0x1F
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#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_S 6
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/* I2C_ANA_MST_I2C1_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */
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/*description: .*/
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#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR 0x0000003F
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#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_M ((I2C_ANA_MST_I2C1_SCL_PULSE_DUR_V)<<(I2C_ANA_MST_I2C1_SCL_PULSE_DUR_S))
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#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_V 0x3F
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#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_S 0
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#define I2C_ANA_MST_HW_I2C_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x2C)
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/* I2C_ANA_MST_ARBITER_DIS : R/W ;bitpos:[11] ;default: 1'h0 ; */
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/*description: .*/
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#define I2C_ANA_MST_ARBITER_DIS (BIT(11))
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#define I2C_ANA_MST_ARBITER_DIS_M (BIT(11))
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#define I2C_ANA_MST_ARBITER_DIS_V 0x1
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#define I2C_ANA_MST_ARBITER_DIS_S 11
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/* I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */
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/*description: .*/
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#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD 0x0000001F
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#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_M ((I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_V)<<(I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_S))
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#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_V 0x1F
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#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_S 6
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/* I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */
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/*description: .*/
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#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR 0x0000003F
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#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_M ((I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_V)<<(I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_S))
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#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_V 0x3F
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#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_S 0
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#define I2C_ANA_MST_I2C_MST_NOUSE_REG (DR_REG_I2C_ANA_MST_BASE + 0x30)
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/* I2C_ANA_MST_I2C_MST_NOUSE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
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/*description: .*/
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#define I2C_ANA_MST_I2C_MST_NOUSE 0xFFFFFFFF
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#define I2C_ANA_MST_I2C_MST_NOUSE_M ((I2C_ANA_MST_I2C_MST_NOUSE_V)<<(I2C_ANA_MST_I2C_MST_NOUSE_S))
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#define I2C_ANA_MST_I2C_MST_NOUSE_V 0xFFFFFFFF
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#define I2C_ANA_MST_I2C_MST_NOUSE_S 0
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#define I2C_ANA_MST_EXT_I2C_MASK_REG (DR_REG_I2C_ANA_MST_BASE + 0x34)
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/* I2C_ANA_MST_EXT_I2C_SDA_O_MASK : R/W ;bitpos:[31:16] ;default: 16'h0 ; */
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/*description: .*/
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#define I2C_ANA_MST_EXT_I2C_SDA_O_MASK 0x0000FFFF
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#define I2C_ANA_MST_EXT_I2C_SDA_O_MASK_M ((I2C_ANA_MST_EXT_I2C_SDA_O_MASK_V)<<(I2C_ANA_MST_EXT_I2C_SDA_O_MASK_S))
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#define I2C_ANA_MST_EXT_I2C_SDA_O_MASK_V 0xFFFF
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#define I2C_ANA_MST_EXT_I2C_SDA_O_MASK_S 16
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/* I2C_ANA_MST_EXT_I2C_SDA_I_MASK : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
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/*description: .*/
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#define I2C_ANA_MST_EXT_I2C_SDA_I_MASK 0x0000FFFF
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#define I2C_ANA_MST_EXT_I2C_SDA_I_MASK_M ((I2C_ANA_MST_EXT_I2C_SDA_I_MASK_V)<<(I2C_ANA_MST_EXT_I2C_SDA_I_MASK_S))
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#define I2C_ANA_MST_EXT_I2C_SDA_I_MASK_V 0xFFFF
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#define I2C_ANA_MST_EXT_I2C_SDA_I_MASK_S 0
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#define I2C_ANA_MST_I2C_MASK_REG (DR_REG_I2C_ANA_MST_BASE + 0x38)
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/* I2C_ANA_MST_I2C_SDA_O_MASK : R/W ;bitpos:[31:16] ;default: 16'h0 ; */
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/*description: .*/
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#define I2C_ANA_MST_I2C_SDA_O_MASK 0x0000FFFF
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#define I2C_ANA_MST_I2C_SDA_O_MASK_M ((I2C_ANA_MST_I2C_SDA_O_MASK_V)<<(I2C_ANA_MST_I2C_SDA_O_MASK_S))
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#define I2C_ANA_MST_I2C_SDA_O_MASK_V 0xFFFF
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#define I2C_ANA_MST_I2C_SDA_O_MASK_S 16
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/* I2C_ANA_MST_I2C_SDA_I_MASK : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
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/*description: .*/
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#define I2C_ANA_MST_I2C_SDA_I_MASK 0x0000FFFF
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#define I2C_ANA_MST_I2C_SDA_I_MASK_M ((I2C_ANA_MST_I2C_SDA_I_MASK_V)<<(I2C_ANA_MST_I2C_SDA_I_MASK_S))
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#define I2C_ANA_MST_I2C_SDA_I_MASK_V 0xFFFF
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#define I2C_ANA_MST_I2C_SDA_I_MASK_S 0
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#define I2C_ANA_MST_DATE_REG (DR_REG_I2C_ANA_MST_BASE + 0x3C)
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/* I2C_ANA_MST_CLK_EN : R/W ;bitpos:[28] ;default: 1'h0 ; */
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/*description: .*/
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#define I2C_ANA_MST_CLK_EN (BIT(28))
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#define I2C_ANA_MST_CLK_EN_M (BIT(28))
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#define I2C_ANA_MST_CLK_EN_V 0x1
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#define I2C_ANA_MST_CLK_EN_S 28
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/* I2C_ANA_MST_DATE : R/W ;bitpos:[27:0] ;default: 28'h2411290 ; */
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/*description: .*/
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#define I2C_ANA_MST_DATE 0x0FFFFFFF
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#define I2C_ANA_MST_DATE_M ((I2C_ANA_MST_DATE_V)<<(I2C_ANA_MST_DATE_S))
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#define I2C_ANA_MST_DATE_V 0xFFFFFFF
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#define I2C_ANA_MST_DATE_S 0
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#ifdef __cplusplus
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}
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#endif
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