mirror of
https://github.com/espressif/esp-idf.git
synced 2026-04-27 19:13:21 +00:00
Chen Jichang
118 lines
4.4 KiB
C
118 lines
4.4 KiB
C
/*
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* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "hal/lcd_periph.h"
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#include "soc/gpio_sig_map.h"
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#include "soc/lcd_cam_reg.h"
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const soc_lcd_i80_signal_desc_t soc_lcd_i80_signals[1] = {
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[0] = {
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.module = PERIPH_LCD_CAM_MODULE,
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.irq_id = ETS_LCD_CAM_INTR_SOURCE,
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.data_sigs = {
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LCD_DATA_OUT_PAD_OUT0_IDX,
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LCD_DATA_OUT_PAD_OUT1_IDX,
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LCD_DATA_OUT_PAD_OUT2_IDX,
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LCD_DATA_OUT_PAD_OUT3_IDX,
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LCD_DATA_OUT_PAD_OUT4_IDX,
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LCD_DATA_OUT_PAD_OUT5_IDX,
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LCD_DATA_OUT_PAD_OUT6_IDX,
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LCD_DATA_OUT_PAD_OUT7_IDX,
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LCD_DATA_OUT_PAD_OUT8_IDX,
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LCD_DATA_OUT_PAD_OUT9_IDX,
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LCD_DATA_OUT_PAD_OUT10_IDX,
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LCD_DATA_OUT_PAD_OUT11_IDX,
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LCD_DATA_OUT_PAD_OUT12_IDX,
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LCD_DATA_OUT_PAD_OUT13_IDX,
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LCD_DATA_OUT_PAD_OUT14_IDX,
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LCD_DATA_OUT_PAD_OUT15_IDX,
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LCD_DATA_OUT_PAD_OUT16_IDX,
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LCD_DATA_OUT_PAD_OUT17_IDX,
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LCD_DATA_OUT_PAD_OUT18_IDX,
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LCD_DATA_OUT_PAD_OUT19_IDX,
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LCD_DATA_OUT_PAD_OUT20_IDX,
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LCD_DATA_OUT_PAD_OUT21_IDX,
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LCD_DATA_OUT_PAD_OUT22_IDX,
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LCD_DATA_OUT_PAD_OUT23_IDX,
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},
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.cs_sig = LCD_CS_PAD_OUT_IDX,
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.dc_sig = LCD_DC_PAD_OUT_IDX,
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.wr_sig = LCD_PCLK_PAD_OUT_IDX
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}
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};
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const soc_lcd_rgb_signal_desc_t soc_lcd_rgb_signals[1] = {
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[0] = {
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.module = PERIPH_LCD_CAM_MODULE,
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.irq_id = ETS_LCD_CAM_INTR_SOURCE,
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.data_sigs = {
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LCD_DATA_OUT_PAD_OUT0_IDX,
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LCD_DATA_OUT_PAD_OUT1_IDX,
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LCD_DATA_OUT_PAD_OUT2_IDX,
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LCD_DATA_OUT_PAD_OUT3_IDX,
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LCD_DATA_OUT_PAD_OUT4_IDX,
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LCD_DATA_OUT_PAD_OUT5_IDX,
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LCD_DATA_OUT_PAD_OUT6_IDX,
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LCD_DATA_OUT_PAD_OUT7_IDX,
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LCD_DATA_OUT_PAD_OUT8_IDX,
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LCD_DATA_OUT_PAD_OUT9_IDX,
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LCD_DATA_OUT_PAD_OUT10_IDX,
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LCD_DATA_OUT_PAD_OUT11_IDX,
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LCD_DATA_OUT_PAD_OUT12_IDX,
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LCD_DATA_OUT_PAD_OUT13_IDX,
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LCD_DATA_OUT_PAD_OUT14_IDX,
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LCD_DATA_OUT_PAD_OUT15_IDX,
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LCD_DATA_OUT_PAD_OUT16_IDX,
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LCD_DATA_OUT_PAD_OUT17_IDX,
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LCD_DATA_OUT_PAD_OUT18_IDX,
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LCD_DATA_OUT_PAD_OUT19_IDX,
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LCD_DATA_OUT_PAD_OUT20_IDX,
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LCD_DATA_OUT_PAD_OUT21_IDX,
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LCD_DATA_OUT_PAD_OUT22_IDX,
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LCD_DATA_OUT_PAD_OUT23_IDX,
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},
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.hsync_sig = LCD_H_SYNC_PAD_OUT_IDX,
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.vsync_sig = LCD_V_SYNC_PAD_OUT_IDX,
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.pclk_sig = LCD_PCLK_PAD_OUT_IDX,
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.de_sig = LCD_H_ENABLE_PAD_OUT_IDX,
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.disp_sig = SIG_GPIO_OUT_IDX,
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}
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};
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/**
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* LCD_CAM Registers to be saved during sleep retention
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* - LCD Clock Configuration registers: LCDCAM_LCD_CLOCK_REG (0x0)
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* - LCD User Configuration registers: LCDCAM_LCD_USER_REG (0x14), LCDCAM_LCD_MISC_REG (0x18)
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* - LCD Control registers: LCDCAM_LCD_CTRL_REG (0x1c) (Note: lcd_rgb_mode_en is in this register)
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* - LCD Delay Mode Configuration registers: LCDCAM_LCD_DLY_MODE_CFG1_REG (0x30), LCDCAM_LCD_DLY_MODE_CFG2_REG (0x38)
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* - LCD DMA Interrupt Enable register: LCDCAM_LC_DMA_INT_ENA_REG (0x64)
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*
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* NOTE: Only I80 LCD supports sleep retention, not RGB LCD.
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*/
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#define LCD_RETENTION_REGS_CNT 7
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#define LCD_RETENTION_REGS_BASE (DR_REG_LCDCAM_BASE + 0x0)
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static const uint32_t lcd_cam_regs_map[4] = {0x20050e1, 0x0, 0x0, 0x0};
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static const regdma_entries_config_t lcd_regs_retention[] = {
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// backup stage: save configuration registers
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// restore stage: restore the configuration registers
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[0] = {
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.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_LCDCAM_LINK(0x00),
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LCD_RETENTION_REGS_BASE, LCD_RETENTION_REGS_BASE,
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LCD_RETENTION_REGS_CNT, 0, 0,
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lcd_cam_regs_map[0], lcd_cam_regs_map[1],
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lcd_cam_regs_map[2], lcd_cam_regs_map[3]),
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.owner = ENTRY(0),
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},
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};
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const soc_i80_lcd_retention_info_t soc_i80_lcd_retention_info[1] = {
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[0] = {
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.regdma_entry_array = lcd_regs_retention,
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.array_size = ARRAY_SIZE(lcd_regs_retention),
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.retention_module = SLEEP_RETENTION_MODULE_LCDCAM
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},
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};
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