mirror of
https://github.com/espressif/esp-idf.git
synced 2026-04-27 19:13:21 +00:00
Marius Vikhammer
203 lines
6.3 KiB
C
203 lines
6.3 KiB
C
/*
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* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include "sdkconfig.h"
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#include "esp_attr.h"
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#include "esp_log.h"
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#include "esp_image_format.h"
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#include "flash_qio_mode.h"
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#include "esp_rom_gpio.h"
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#include "esp_rom_efuse.h"
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#include "esp_rom_serial_output.h"
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#include "esp_rom_sys.h"
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#include "soc/gpio_sig_map.h"
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#include "esp_cpu.h"
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#include "soc/rtc.h"
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#include "soc/soc_caps.h"
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#include "soc/cache_reg.h"
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#include "soc/io_mux_reg.h"
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#include "soc/pcr_reg.h"
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#include "soc/bus_monitor_reg.h"
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#include "bootloader_common.h"
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#include "bootloader_init.h"
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#include "bootloader_clock.h"
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#include "bootloader_flash_config.h"
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#include "bootloader_mem.h"
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#include "esp_private/regi2c_ctrl.h"
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#include "soc/hp_system_reg.h"
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#include "bootloader_console.h"
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#include "bootloader_flash_priv.h"
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#include "bootloader_soc.h"
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#include "esp_private/bootloader_flash_internal.h"
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#include "esp_efuse.h"
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#include "hal/mmu_hal.h"
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#include "hal/cache_hal.h"
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#include "hal/clk_tree_ll.h"
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#include "soc/lp_wdt_reg.h"
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#include "hal/efuse_hal.h"
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#include "hal/lpwdt_ll.h"
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#include "hal/assist_debug_ll.h"
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ESP_LOG_ATTR_TAG(TAG, "boot.esp32h4");
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#if SOC_RTC_WDT_SUPPORTED || SOC_CPU_LOCKUP_DEBUG_SUPPORTED
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void bootloader_enable_cpu_reset_info(void)
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{
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assist_debug_ll_enable_bus_clock(0, true);
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assist_debug_ll_enable_pc_recording(0, true);
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assist_debug_ll_lockup_monitor_enable(0, true);
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assist_debug_ll_lockup_reset_enable(0);
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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assist_debug_ll_enable_bus_clock(1, true);
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assist_debug_ll_enable_pc_recording(1, true);
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assist_debug_ll_lockup_monitor_enable(1, true);
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assist_debug_ll_lockup_reset_enable(1);
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#endif
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}
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void bootloader_dump_wdt_reset_info(int cpu)
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{
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(void) cpu;
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// saved PC was already printed by the ROM bootloader.
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// nothing to do here.
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}
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bool bootloader_check_if_wdt_reset(int cpu, soc_reset_reason_t reset_reason)
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{
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if (cpu == 0 && (reset_reason == RESET_REASON_CORE_RTC_WDT || reset_reason == RESET_REASON_CORE_MWDT0 ||
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reset_reason == RESET_REASON_CORE_MWDT1 || reset_reason == RESET_REASON_CPU0_MWDT0 ||
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reset_reason == RESET_REASON_CPU0_MWDT1 || reset_reason == RESET_REASON_CPU0_RTC_WDT)) {
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ESP_LOGW(TAG, "PRO CPU has been reset by WDT.");
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return true;
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}
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if (cpu == 1 && (reset_reason == RESET_REASON_CORE_RTC_WDT || reset_reason == RESET_REASON_CORE_MWDT0 ||
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reset_reason == RESET_REASON_CORE_MWDT1 || reset_reason == RESET_REASON_CPU0_MWDT0 ||
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reset_reason == RESET_REASON_CPU0_MWDT1 || reset_reason == RESET_REASON_CPU0_RTC_WDT)) {
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ESP_LOGW(TAG, "APP CPU has been reset by WDT.");
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return true;
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}
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return false;
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}
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#if SOC_RTC_WDT_SUPPORTED
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static void bootloader_super_wdt_auto_feed(void)
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{
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REG_WRITE(LP_WDT_SWD_WPROTECT_REG, LP_WDT_SWD_WKEY_VALUE);
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REG_SET_BIT(LP_WDT_SWD_CONFIG_REG, LP_WDT_SWD_AUTO_FEED_EN);
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REG_WRITE(LP_WDT_SWD_WPROTECT_REG, 0);
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}
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#endif
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#endif // SOC_RTC_WDT_SUPPORTED || SOC_CPU_LOCKUP_DEBUG_SUPPORTED
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static inline void bootloader_hardware_init(void)
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{
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/* Disable RF pll by default */
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CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_RFPLL);
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SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_FORCE_RFPLL);
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#if !CONFIG_IDF_ENV_FPGA
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/* Enable analog i2c master clock */
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_regi2c_ctrl_ll_master_enable_clock(true); // keep ana i2c mst clock always enabled in bootloader
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regi2c_ctrl_ll_master_force_enable_clock(true); // TODO: IDF-12313 Remove this?
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regi2c_ctrl_ll_master_configure_clock();
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#endif
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}
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static inline void bootloader_ana_reset_config(void)
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{
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//Enable super WDT reset.
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bootloader_ana_super_wdt_reset_config(true);
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//Enable BOD reset
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//TODO: [ESP32H4] IDF-12295 need check
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}
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static inline void bootloader_config_dcache(void)
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{
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REG_SET_BIT(LP_AON_SRAM_USAGE_CONF_REG, LP_AON_DCACHE_USAGE);
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}
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static inline void bootloader_config_icache1(void)
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{
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#if CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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REG_CLR_BIT(LP_AON_SRAM_USAGE_CONF_REG, LP_AON_ICACHE1_USAGE);
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#else
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REG_SET_BIT(LP_AON_SRAM_USAGE_CONF_REG, LP_AON_ICACHE1_USAGE);
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#endif
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}
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esp_err_t bootloader_init(void)
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{
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esp_err_t ret = ESP_OK;
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bootloader_hardware_init();
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bootloader_ana_reset_config();
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#if SOC_RTC_WDT_SUPPORTED
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bootloader_super_wdt_auto_feed();
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#endif
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// In RAM_APP, memory will be initialized in `call_start_cpu0`
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#if !CONFIG_APP_BUILD_TYPE_RAM
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// protect memory region
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bootloader_init_mem();
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/* check that static RAM is after the stack */
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assert(&_bss_start <= &_bss_end);
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assert(&_data_start <= &_data_end);
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// clear bss section
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bootloader_clear_bss_section();
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#endif // !CONFIG_APP_BUILD_TYPE_RAM
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// init eFuse virtual mode (read eFuses to RAM)
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#ifdef CONFIG_EFUSE_VIRTUAL
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ESP_EARLY_LOGW(TAG, "eFuse virtual mode is enabled. If Secure boot or Flash encryption is enabled then it does not provide any security. FOR TESTING ONLY!");
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#ifndef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH
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esp_efuse_init_virtual_mode_in_ram();
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#endif
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#endif
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// config clock
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bootloader_clock_configure();
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// initialize console, from now on, we can use esp_log
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bootloader_console_init();
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/* print 2nd bootloader banner */
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bootloader_print_banner();
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#if !CONFIG_APP_BUILD_TYPE_RAM
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// init cache and mmu
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bootloader_init_ext_mem();
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// update flash ID
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bootloader_flash_update_id();
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// Check and run XMC startup flow
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if ((ret = bootloader_flash_xmc_startup()) != ESP_OK) {
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ESP_LOGE(TAG, "failed when running XMC startup flow, reboot!");
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return ret;
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}
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// read bootloader header
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if ((ret = bootloader_read_bootloader_header()) != ESP_OK) {
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return ret;
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}
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// read chip revision and check if it's compatible to bootloader
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if ((ret = bootloader_check_bootloader_validity()) != ESP_OK) {
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return ret;
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}
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// initialize spi flash
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if ((ret = bootloader_init_spi_flash()) != ESP_OK) {
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return ret;
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}
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#endif // !CONFIG_APP_BUILD_TYPE_RAM
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bootloader_config_dcache();
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bootloader_config_icache1();
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// check reset reason and dump diagnostic info
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bootloader_check_reset();
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#if SOC_RTC_WDT_SUPPORTED || SOC_WDT_SUPPORTED
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// config WDT
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bootloader_config_wdt();
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#endif
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// enable RNG early entropy source
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bootloader_enable_random();
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return ret;
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}
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