mirror of
https://github.com/espressif/esp-idf.git
synced 2026-04-27 11:03:11 +00:00
Song Ruo Jing
97 lines
4.2 KiB
C
97 lines
4.2 KiB
C
/*
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* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdio.h>
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#include <stdint.h>
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#include "unity.h"
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#include "test_regi2c.h"
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#include "esp_private/regi2c_ctrl.h"
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#include "sdkconfig.h"
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TEST_CASE("regi2c basic read/write test", "[regi2c]")
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{
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#if CONFIG_IDF_ENV_FPGA
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TEST_PASS_MESSAGE("regi2c is not supported on FPGA, skip this test");
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#endif
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#if CONFIG_IDF_TARGET_ESP32
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// For ESP32, we need to enable the APLL clock before accessing the APLL regi2c registers
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periph_rtc_apll_acquire();
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#endif
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/* ---- Part 1: full-register read / write ---- */
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printf("Test regi2c read/write: block=0x%02X host=%d reg=%d\n",
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TEST_BLOCK, TEST_HOST_ID, TEST_REG_FULL);
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uint8_t orig_full = regi2c_ctrl_read_reg(TEST_BLOCK, TEST_HOST_ID, TEST_REG_FULL);
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printf(" Original value: 0x%02X\n", orig_full);
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const uint8_t patterns[] = {0xA5, 0x5A, 0xFF, 0x00};
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for (size_t i = 0; i < sizeof(patterns) / sizeof(patterns[0]); i++) {
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regi2c_ctrl_write_reg(TEST_BLOCK, TEST_HOST_ID, TEST_REG_FULL, patterns[i]);
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uint8_t rb = regi2c_ctrl_read_reg(TEST_BLOCK, TEST_HOST_ID, TEST_REG_FULL);
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printf(" Write 0x%02X -> Read 0x%02X\n", patterns[i], rb);
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TEST_ASSERT_EQUAL_HEX8(patterns[i], rb);
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}
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/* ---- Part 2: masked read / write ---- */
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const uint8_t field_width = TEST_REG_MASK_MSB - TEST_REG_MASK_LSB + 1;
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const uint8_t field_max = (uint8_t)((1U << field_width) - 1);
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const uint8_t reg_mask = (uint8_t)(field_max << TEST_REG_MASK_LSB);
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printf("Test regi2c read_mask/write_mask: block=0x%02X host=%d reg=%d bits[%d:%d]\n",
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TEST_BLOCK, TEST_HOST_ID, TEST_REG_MASK,
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TEST_REG_MASK_MSB, TEST_REG_MASK_LSB);
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uint8_t orig_mask = regi2c_ctrl_read_reg(TEST_BLOCK, TEST_HOST_ID, TEST_REG_MASK);
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printf(" Original full reg value: 0x%02X\n", orig_mask);
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/* Write all-ones to masked field */
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regi2c_ctrl_write_reg_mask(TEST_BLOCK, TEST_HOST_ID, TEST_REG_MASK,
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TEST_REG_MASK_MSB, TEST_REG_MASK_LSB, field_max);
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uint8_t mval = regi2c_ctrl_read_reg_mask(TEST_BLOCK, TEST_HOST_ID, TEST_REG_MASK,
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TEST_REG_MASK_MSB, TEST_REG_MASK_LSB);
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printf(" write_mask(0x%02X) -> read_mask=0x%02X\n", field_max, mval);
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TEST_ASSERT_EQUAL_HEX8(field_max, mval);
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uint8_t full = regi2c_ctrl_read_reg(TEST_BLOCK, TEST_HOST_ID, TEST_REG_MASK);
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TEST_ASSERT_EQUAL_HEX8(orig_mask & (uint8_t)(~reg_mask), full & (uint8_t)(~reg_mask));
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/* Write all-zeros to masked field */
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regi2c_ctrl_write_reg_mask(TEST_BLOCK, TEST_HOST_ID, TEST_REG_MASK,
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TEST_REG_MASK_MSB, TEST_REG_MASK_LSB, 0x00);
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mval = regi2c_ctrl_read_reg_mask(TEST_BLOCK, TEST_HOST_ID, TEST_REG_MASK,
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TEST_REG_MASK_MSB, TEST_REG_MASK_LSB);
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printf(" write_mask(0x00) -> read_mask=0x%02X\n", mval);
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TEST_ASSERT_EQUAL_HEX8(0x00, mval);
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full = regi2c_ctrl_read_reg(TEST_BLOCK, TEST_HOST_ID, TEST_REG_MASK);
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TEST_ASSERT_EQUAL_HEX8(orig_mask & (uint8_t)(~reg_mask), full & (uint8_t)(~reg_mask));
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/* Write a mid-range value */
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uint8_t mid = field_max >> 1;
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if (mid == 0 && field_max > 0) {
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mid = 1;
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}
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regi2c_ctrl_write_reg_mask(TEST_BLOCK, TEST_HOST_ID, TEST_REG_MASK,
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TEST_REG_MASK_MSB, TEST_REG_MASK_LSB, mid);
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mval = regi2c_ctrl_read_reg_mask(TEST_BLOCK, TEST_HOST_ID, TEST_REG_MASK,
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TEST_REG_MASK_MSB, TEST_REG_MASK_LSB);
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printf(" write_mask(0x%02X) -> read_mask=0x%02X\n", mid, mval);
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TEST_ASSERT_EQUAL_HEX8(mid, mval);
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/* Restore all modified registers to their original values */
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regi2c_ctrl_write_reg(TEST_BLOCK, TEST_HOST_ID, TEST_REG_FULL, orig_full);
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TEST_ASSERT_EQUAL_HEX8(orig_full,
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regi2c_ctrl_read_reg(TEST_BLOCK, TEST_HOST_ID, TEST_REG_FULL));
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regi2c_ctrl_write_reg(TEST_BLOCK, TEST_HOST_ID, TEST_REG_MASK, orig_mask);
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TEST_ASSERT_EQUAL_HEX8(orig_mask,
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regi2c_ctrl_read_reg(TEST_BLOCK, TEST_HOST_ID, TEST_REG_MASK));
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#if CONFIG_IDF_TARGET_ESP32
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// Disable APLL clock
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periph_rtc_apll_release();
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#endif
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}
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