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c4e2fe2c8b
Wrap MWDT-related code under SOC_WDT_SUPPORTED so targets without a main watchdog can compile. Add SOC_RTC_WDT_SUPPORTED for RTC watchdog usage (bootloader, slow-clock paths) and regenerate Kconfig.soc_caps.in. Bootloader RWDT setup stays under SOC_RTC_WDT_SUPPORTED; MWDT flashboot teardown stays under SOC_WDT_SUPPORTED. ESP_INT_WDT, ESP_TASK_WDT_EN, and BOOTLOADER_WDT_ENABLE depend on SOC_WDT_SUPPORTED where applicable. Build xt_wdt.c only when SOC_XT_WDT_SUPPORTED. Provide no-op panic WDT helpers when SOC_WDT_SUPPORTED is disabled.
155 lines
6.4 KiB
C
155 lines
6.4 KiB
C
/*
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* SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <string.h>
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#include "sdkconfig.h"
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#include "esp_system.h"
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#include "esp_private/system_internal.h"
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#include "esp_macros.h"
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#include "esp_attr.h"
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#include "esp_log.h"
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#include "esp_rom_sys.h"
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#include "riscv/rv_utils.h"
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#include "esp_rom_serial_output.h"
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#include "soc/gpio_reg.h"
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#include "soc/soc_caps.h"
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#include "esp_cpu.h"
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#include "soc/rtc.h"
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#include "esp_private/rtc_clk.h"
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#include "soc/uart_reg.h"
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#include "hal/uart_ll.h"
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#if SOC_WDT_SUPPORTED || SOC_RTC_WDT_SUPPORTED
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#include "hal/wdt_hal.h"
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#endif
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#include "hal/uart_ll.h"
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#include "esp_private/cache_err_int.h"
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#if SOC_MODEM_CLOCK_SUPPORTED
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#include "hal/modem_syscon_ll.h"
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#include "hal/modem_lpcon_ll.h"
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#endif
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#include "esp32c61/rom/cache.h"
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#include "esp32c61/rom/rtc.h"
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#include "soc/pcr_reg.h"
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void esp_system_reset_modules_on_exit(void)
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{
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// Flush any data left in UART FIFOs before reset the UART peripheral
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for (int i = 0; i < SOC_UART_HP_NUM; ++i) {
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if (uart_ll_is_enabled(i)) {
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esp_rom_output_tx_wait_idle(i);
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}
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}
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#if SOC_MODEM_CLOCK_SUPPORTED
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modem_syscon_ll_reset_all(&MODEM_SYSCON);
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modem_lpcon_ll_reset_all(&MODEM_LPCON);
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#endif
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// Set Peripheral clk rst
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SET_PERI_REG_MASK(PCR_MSPI_CLK_CONF_REG, PCR_MSPI_AXI_RST_EN); // Must reset mspi AXI before reset mspi core.
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SET_PERI_REG_MASK(PCR_MSPI_CONF_REG, PCR_MSPI_RST_EN);
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SET_PERI_REG_MASK(PCR_UART0_CONF_REG, PCR_UART0_RST_EN);
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SET_PERI_REG_MASK(PCR_UART1_CONF_REG, PCR_UART1_RST_EN);
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SET_PERI_REG_MASK(PCR_SYSTIMER_CONF_REG, PCR_SYSTIMER_RST_EN);
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SET_PERI_REG_MASK(PCR_GDMA_CONF_REG, PCR_GDMA_RST_EN);
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SET_PERI_REG_MASK(PCR_MODEM_CONF_REG, PCR_MODEM_RST_EN);
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// The DMA inside SDIO slave needs to be reset to avoid memory corruption after restart.
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SET_PERI_REG_MASK(PCR_SDIO_SLAVE_CONF_REG, PCR_SDIO_SLAVE_RST_EN);
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//ETM may directly control the GPIO or other peripherals even after CPU reset. Reset to stop these control.
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SET_PERI_REG_MASK(PCR_ETM_CONF_REG, PCR_ETM_RST_EN);
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SET_PERI_REG_MASK(PCR_REGDMA_CONF_REG, PCR_REGDMA_RST_EN);
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// Clear Peripheral clk rst
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CLEAR_PERI_REG_MASK(PCR_MSPI_CONF_REG, PCR_MSPI_RST_EN);
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CLEAR_PERI_REG_MASK(PCR_MSPI_CLK_CONF_REG, PCR_MSPI_AXI_RST_EN); // Must release mspi core reset before mspi AXI.
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CLEAR_PERI_REG_MASK(PCR_UART0_CONF_REG, PCR_UART0_RST_EN);
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CLEAR_PERI_REG_MASK(PCR_UART1_CONF_REG, PCR_UART1_RST_EN);
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CLEAR_PERI_REG_MASK(PCR_SYSTIMER_CONF_REG, PCR_SYSTIMER_RST_EN);
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CLEAR_PERI_REG_MASK(PCR_GDMA_CONF_REG, PCR_GDMA_RST_EN);
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CLEAR_PERI_REG_MASK(PCR_MODEM_CONF_REG, PCR_MODEM_RST_EN);
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CLEAR_PERI_REG_MASK(PCR_SDIO_SLAVE_CONF_REG, PCR_SDIO_SLAVE_RST_EN);
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CLEAR_PERI_REG_MASK(PCR_ETM_CONF_REG, PCR_ETM_RST_EN);
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CLEAR_PERI_REG_MASK(PCR_REGDMA_CONF_REG, PCR_REGDMA_RST_EN);
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// Reset crypto peripherals. This ensures a clean state for the crypto peripherals after a CPU restart
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// and hence avoiding any possibility with crypto failure in ROM security workflows.
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// We also avoid resetting all the crypto peripherals at once because it would create a period when
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// all the peripherals are reset at the same time, which triggers a hardware SEC reset. The SEC reset
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// causes the crypto -> APB path to be reset, but the APB -> crypto path is not reset. This asymmetry
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// results in the crypto module hanging and refusing all access.
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SET_PERI_REG_MASK(PCR_AES_CONF_REG, PCR_AES_RST_EN);
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CLEAR_PERI_REG_MASK(PCR_AES_CONF_REG, PCR_AES_RST_EN);
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SET_PERI_REG_MASK(PCR_DS_CONF_REG, PCR_DS_RST_EN);
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CLEAR_PERI_REG_MASK(PCR_DS_CONF_REG, PCR_DS_RST_EN);
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SET_PERI_REG_MASK(PCR_ECC_CONF_REG, PCR_ECC_RST_EN);
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CLEAR_PERI_REG_MASK(PCR_ECC_CONF_REG, PCR_ECC_RST_EN);
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SET_PERI_REG_MASK(PCR_ECDSA_CONF_REG, PCR_ECDSA_RST_EN);
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CLEAR_PERI_REG_MASK(PCR_ECDSA_CONF_REG, PCR_ECDSA_RST_EN);
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SET_PERI_REG_MASK(PCR_HMAC_CONF_REG, PCR_HMAC_RST_EN);
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CLEAR_PERI_REG_MASK(PCR_HMAC_CONF_REG, PCR_HMAC_RST_EN);
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SET_PERI_REG_MASK(PCR_RSA_CONF_REG, PCR_RSA_RST_EN);
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CLEAR_PERI_REG_MASK(PCR_RSA_CONF_REG, PCR_RSA_RST_EN);
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SET_PERI_REG_MASK(PCR_SHA_CONF_REG, PCR_SHA_RST_EN);
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CLEAR_PERI_REG_MASK(PCR_SHA_CONF_REG, PCR_SHA_RST_EN);
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// UART's sclk is controlled in the PCR register and does not reset with the UART module. The ROM missed enabling
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// it when initializing the ROM UART. If it is not turned on, it will trigger LP_WDT in the ROM.
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uart_ll_sclk_enable(&UART0);
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}
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/* "inner" restart function for after RTOS, interrupts & anything else on this
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* core are already stopped. Stalls other core, resets hardware,
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* triggers restart.
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*/
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void esp_restart_noos(void)
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{
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// Disable interrupts
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rv_utils_intr_global_disable();
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#if SOC_RTC_WDT_SUPPORTED
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// Enable RTC watchdog for 1 second
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wdt_hal_context_t rtc_wdt_ctx;
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wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, false);
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uint32_t stage_timeout_ticks = (uint32_t)(1000ULL * rtc_clk_slow_freq_get_hz() / 1000ULL);
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wdt_hal_write_protect_disable(&rtc_wdt_ctx);
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wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_SYSTEM);
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wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE1, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
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//Enable flash boot mode so that flash booting after restart is protected by the RTC WDT.
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wdt_hal_set_flashboot_en(&rtc_wdt_ctx, true);
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wdt_hal_write_protect_enable(&rtc_wdt_ctx);
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#endif /* SOC_RTC_WDT_SUPPORTED */
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// C61 is a single core SoC, no need to reset and stall the other CPU
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#if SOC_WDT_SUPPORTED
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// Disable TG0/TG1 watchdogs
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wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0};
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wdt_hal_write_protect_disable(&wdt0_context);
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wdt_hal_disable(&wdt0_context);
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wdt_hal_write_protect_enable(&wdt0_context);
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wdt_hal_context_t wdt1_context = {.inst = WDT_MWDT1, .mwdt_dev = &TIMERG1};
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wdt_hal_write_protect_disable(&wdt1_context);
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wdt_hal_disable(&wdt1_context);
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wdt_hal_write_protect_enable(&wdt1_context);
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#endif /* SOC_WDT_SUPPORTED */
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// Disable cache
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Cache_Disable_Cache();
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esp_system_reset_modules_on_exit();
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// Set CPU back to XTAL source, same as hard reset, but keep BBPLL on so that USB Serial JTAG can log at 1st stage bootloader.
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#if !CONFIG_IDF_ENV_FPGA
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rtc_clk_cpu_set_to_default_config();
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#endif
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// Reset PRO CPU
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esp_rom_software_reset_cpu(0);
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ESP_INFINITE_LOOP();
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}
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