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c4e2fe2c8b
Wrap MWDT-related code under SOC_WDT_SUPPORTED so targets without a main watchdog can compile. Add SOC_RTC_WDT_SUPPORTED for RTC watchdog usage (bootloader, slow-clock paths) and regenerate Kconfig.soc_caps.in. Bootloader RWDT setup stays under SOC_RTC_WDT_SUPPORTED; MWDT flashboot teardown stays under SOC_WDT_SUPPORTED. ESP_INT_WDT, ESP_TASK_WDT_EN, and BOOTLOADER_WDT_ENABLE depend on SOC_WDT_SUPPORTED where applicable. Build xt_wdt.c only when SOC_XT_WDT_SUPPORTED. Provide no-op panic WDT helpers when SOC_WDT_SUPPORTED is disabled.
132 lines
4.1 KiB
C
132 lines
4.1 KiB
C
/*
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* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <string.h>
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#include "sdkconfig.h"
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#include "esp_macros.h"
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#include "esp_system.h"
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#include "esp_private/system_internal.h"
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#include "esp_attr.h"
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#include "esp_log.h"
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#include "esp_rom_sys.h"
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#include "riscv/rv_utils.h"
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#include "esp_rom_serial_output.h"
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#include "soc/gpio_reg.h"
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#include "soc/soc_caps.h"
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#include "esp_cpu.h"
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#include "soc/rtc.h"
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#include "esp_private/rtc_clk.h"
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#include "soc/rtc_periph.h"
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#include "soc/uart_reg.h"
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#if SOC_WDT_SUPPORTED || SOC_RTC_WDT_SUPPORTED
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#include "hal/wdt_hal.h"
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#endif
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#include "esp_private/cache_err_int.h"
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#include "hal/uart_ll.h"
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#include "esp32s31/rom/cache.h"
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#include "esp32s31/rom/ets_sys.h"
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#include "esp32s31/rom/rtc.h"
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#include "soc/hp_sys_clkrst_reg.h"
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#include "soc/lp_clkrst_reg.h"
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#include "soc/hp_system_reg.h"
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// TODO: [ESP32S31] IDF-14841
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void esp_system_reset_modules_on_exit(void)
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{
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// Flush any data left in UART FIFOs
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for (int i = 0; i < SOC_UART_HP_NUM; ++i) {
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if (uart_ll_is_enabled(i)) {
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esp_rom_output_tx_wait_idle(i);
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}
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}
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}
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/* "inner" restart function for after RTOS, interrupts & anything else on this
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* core are already stopped. Stalls other core, resets hardware,
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* triggers restart.
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*/
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void esp_restart_noos(void)
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{
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// Disable interrupts
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rv_utils_intr_global_disable();
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#if SOC_RTC_WDT_SUPPORTED
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// Enable RTC watchdog for 1 second
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wdt_hal_context_t rtc_wdt_ctx;
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wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, false);
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// uint32_t stage_timeout_ticks = (uint32_t)(1000ULL * rtc_clk_slow_freq_get_hz() / 1000ULL);
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uint32_t stage_timeout_ticks = (uint32_t)rtc_clk_slow_freq_get_hz();
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wdt_hal_write_protect_disable(&rtc_wdt_ctx);
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wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_SYSTEM);
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wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE1, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
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//Enable flash boot mode so that flash booting after restart is protected by the RTC WDT.
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wdt_hal_set_flashboot_en(&rtc_wdt_ctx, true);
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wdt_hal_write_protect_enable(&rtc_wdt_ctx);
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#endif /* SOC_RTC_WDT_SUPPORTED */
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const uint32_t core_id = esp_cpu_get_core_id();
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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const uint32_t other_core_id = (core_id == 0) ? 1 : 0;
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esp_cpu_reset(other_core_id);
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esp_cpu_stall(other_core_id);
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#endif
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#if SOC_WDT_SUPPORTED
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// Disable TG0/TG1 watchdogs
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wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0};
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wdt_hal_write_protect_disable(&wdt0_context);
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wdt_hal_disable(&wdt0_context);
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wdt_hal_write_protect_enable(&wdt0_context);
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wdt_hal_context_t wdt1_context = {.inst = WDT_MWDT1, .mwdt_dev = &TIMERG1};
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wdt_hal_write_protect_disable(&wdt1_context);
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wdt_hal_disable(&wdt1_context);
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wdt_hal_write_protect_enable(&wdt1_context);
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#endif /* SOC_WDT_SUPPORTED */
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// Disable cache
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#if CONFIG_SPIRAM
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Cache_WriteBack_All(CACHE_MAP_L1_DCACHE);
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#endif
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esp_system_reset_modules_on_exit();
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// Set CPU back to XTAL source (and MEM_CLK, APB_CLK back to power-on reset frequencies), same as hard reset, keep CPLL on.
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#if !CONFIG_IDF_ENV_FPGA
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rtc_clk_cpu_set_to_default_config();
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#endif
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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// clear entry point for APP CPU
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ets_set_appcpu_boot_addr(0);
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#endif
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#if CONFIG_SPIRAM_INSTRUCTIONS_RODATA
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// disable remap if enabled in menuconfig
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REG_CLR_BIT(HP_SYS_HP_PSRAM_FLASH_ADDR_INTERCHANGE_REG, HP_SYS_HP_PSRAM_FLASH_ADDR_INTERCHANGE_DMA | HP_SYS_HP_PSRAM_FLASH_ADDR_INTERCHANGE_CPU);
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#endif
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// Reset CPUs
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if (core_id == 0) {
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// Running on PRO CPU: APP CPU is stalled. Can reset both CPUs.
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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esp_cpu_reset(1);
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#endif
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esp_cpu_reset(0);
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}
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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else {
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// Running on APP CPU: need to reset PRO CPU and unstall it,
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// then reset APP CPU
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esp_cpu_reset(0);
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esp_cpu_unstall(0);
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esp_cpu_reset(1);
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}
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#endif
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ESP_INFINITE_LOOP();
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}
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