Sudeep Mohanty a67d15fdea ulp: Added APIs to handle ULP signal ISRs for the main CPU ...

This commit introduces APIs to handle ULP signal ISRs when the main core
is not in sleepmode.

Closes https://github.com/espressif/esp-idf/issues/10737

2023-02-24 07:25:39 +00:00

..

cmake

tools: add riscv zicsr/zifencei because they were separated from i

2023-02-22 05:33:03 +00:00

ld

ulp: Added support for RTC I2C driver for ULP RISC-V on esp32s2 and esp32s3

2022-09-05 10:21:43 +02:00

test_apps

ulp: Added APIs to handle ULP signal ISRs for the main CPU

2023-02-24 07:25:39 +00:00

ulp_common

ulp-fsm: Update ulp-fsm ADC example with S3 support

2022-09-07 16:48:06 +08:00

ulp_fsm

ulp: Added APIs to handle ULP signal ISRs for the main CPU

2023-02-24 07:25:39 +00:00

ulp_riscv

ulp: Added APIs to handle ULP signal ISRs for the main CPU

2023-02-24 07:25:39 +00:00

.build-test-rules.yml

ci: Modify build-test-rules.yml enable' to disable` to exclude preview targets

2022-09-01 12:38:00 +08:00

CMakeLists.txt

ulp-fsm: Update ulp-fsm ADC example with S3 support

2022-09-07 16:48:06 +08:00

component_ulp_common.cmake

…

esp32ulp_mapgen.py

ulp: esp32ulp_mapgen: remove the special case for RISC-V, cleanup

2022-08-30 02:34:28 +02:00

Kconfig

Add ULP-RISCV print and bitbanged UART tx API

2022-07-29 12:18:01 +08:00

project_include.cmake

ulp-riscv: add support for using ADC as well as an example show-casing it.

2022-07-11 09:31:22 +08:00

sdkconfig.rename.esp32

soc: moved kconfig options out of the target component.

2022-04-21 12:09:43 +08:00

sdkconfig.rename.esp32s2

soc: moved kconfig options out of the target component.

2022-04-21 12:09:43 +08:00