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espressif
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esp-idf
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e7cf8cd3cbb69b23c91f54d00a810d23c9bdd3e8
esp-idf
/
components
/
riscv
T
History
Marius Vikhammer
a4b817d0fe
fix(cpu): fix CSR_PRV_MODE not defined for S31
2026-04-07 09:37:39 +08:00
..
include
fix(cpu): fix CSR_PRV_MODE not defined for S31
2026-04-07 09:37:39 +08:00
ld
…
CMakeLists.txt
feat(esp_tee): Support for ESP32-C5 - the rest of the components
2025-08-13 14:08:59 +05:30
instruction_decode.c
…
interrupt_clic.c
feat(esp_tee): Support for ESP32-C5 - the rest of the components
2025-08-13 14:08:59 +05:30
interrupt_intc.c
…
interrupt_plic.c
…
interrupt.c
…
linker.lf
…
rv_utils.c
…
vectors_clic.S
change(riscv): Remove redundant definition of MEMPROT_ISR
2025-08-04 11:43:01 +05:30
vectors_intc.S
refactor(esp_system): Update all references of the memory protection configs
2025-08-04 11:43:01 +05:30
vectors.S
feat: add support for PIE coprocessor on the ESP32-S31
2026-03-31 13:27:16 +08:00