mirror of
https://github.com/espressif/esp-idf.git
synced 2026-04-27 19:13:21 +00:00
morris
f2d62bba74
- Add intr_priority field to gdma_channel_t structure - Add intr_bind_name field to gdma_signal_conn_t for interrupt binding - Validate intr_priority during channel allocation (must be 0-3) - Use ESP_INTR_FLAG_SHARED_PRIVATE instead of ESP_INTR_FLAG_SHARED - Use esp_intr_alloc_info() with bind_by.name for shared interrupts - Add interrupt priority configuration test case - Update all gdma_periph.c files with pair-specific bind names (gdma_gXpY)
553 lines
16 KiB
C
553 lines
16 KiB
C
/*
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* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stddef.h> /* Required for NULL constant */
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#include <stdint.h>
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#include <stdbool.h>
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#include "hal/gdma_types.h"
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#include "soc/gdma_struct.h"
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#include "soc/gdma_reg.h"
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#include "soc/system_struct.h"
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#define GDMA_LL_GET(_attr) GDMA_LL_ ## _attr
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#define GDMA_LL_INST_NUM 1
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#define GDMA_LL_PAIRS_PER_INST GDMA_LL_AHB_PAIRS_PER_GROUP
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define GDMA_LL_GET_HW(id) (((id) == 0) ? (&GDMA) : NULL)
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#define GDMA_LL_CHANNEL_MAX_PRIORITY 5 // supported priority levels: [0,5]
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#define GDMA_LL_RX_EVENT_MASK (0x06A7)
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#define GDMA_LL_TX_EVENT_MASK (0x1958)
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// any "valid" peripheral ID can be used for M2M mode
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#define GDMA_LL_M2M_FREE_PERIPH_ID_MASK (0x1CD)
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#define GDMA_LL_EVENT_TX_FIFO_UDF (1<<12)
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#define GDMA_LL_EVENT_TX_FIFO_OVF (1<<11)
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#define GDMA_LL_EVENT_RX_FIFO_UDF (1<<10)
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#define GDMA_LL_EVENT_RX_FIFO_OVF (1<<9)
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#define GDMA_LL_EVENT_TX_TOTAL_EOF (1<<8)
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#define GDMA_LL_EVENT_RX_DESC_EMPTY (1<<7)
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#define GDMA_LL_EVENT_TX_DESC_ERROR (1<<6)
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#define GDMA_LL_EVENT_RX_DESC_ERROR (1<<5)
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#define GDMA_LL_EVENT_TX_EOF (1<<4)
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#define GDMA_LL_EVENT_TX_DONE (1<<3)
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#define GDMA_LL_EVENT_RX_ERR_EOF (1<<2)
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#define GDMA_LL_EVENT_RX_SUC_EOF (1<<1)
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#define GDMA_LL_EVENT_RX_DONE (1<<0)
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#define GDMA_LL_AHB_GROUP_START_ID 0 // AHB GDMA group ID starts from 0
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#define GDMA_LL_AHB_NUM_GROUPS 1 // Number of AHB GDMA groups
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#define GDMA_LL_AHB_PAIRS_PER_GROUP 3 // Number of GDMA pairs in each AHB group
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#define GDMA_LL_AHB_M2M_CAPABLE_PAIR_MASK 0x07 // pair 0,1,2 are M2M capable
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#define GDMA_LL_AHB_DESC_ALIGNMENT 4
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#define GDMA_LL_AHB_RX_BURST_NEEDS_ALIGNMENT 1
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///////////////////////////////////// Common /////////////////////////////////////////
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/**
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* @brief Enable the bus clock for the DMA module
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*/
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static inline void _gdma_ll_enable_bus_clock(int group_id, bool enable)
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{
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(void)group_id;
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SYSTEM.perip_clk_en1.reg_dma_clk_en = enable;
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}
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/// use a macro to wrap the function, force the caller to use it in a critical section
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/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
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#define gdma_ll_enable_bus_clock(...) do { \
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(void)__DECLARE_RCC_ATOMIC_ENV; \
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_gdma_ll_enable_bus_clock(__VA_ARGS__); \
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} while(0)
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/**
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* @brief Reset the DMA module
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*/
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static inline void _gdma_ll_reset_register(int group_id)
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{
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(void)group_id;
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SYSTEM.perip_rst_en1.reg_dma_rst = 1;
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SYSTEM.perip_rst_en1.reg_dma_rst = 0;
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}
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/// use a macro to wrap the function, force the caller to use it in a critical section
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/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
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#define gdma_ll_reset_register(...) do { \
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(void)__DECLARE_RCC_ATOMIC_ENV; \
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_gdma_ll_reset_register(__VA_ARGS__); \
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} while(0)
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/**
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* @brief Force enable register clock
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*/
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static inline void gdma_ll_force_enable_reg_clock(gdma_dev_t *dev, bool enable)
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{
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dev->misc_conf.clk_en = enable;
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}
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///////////////////////////////////// RX /////////////////////////////////////////
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/**
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* @brief Get DMA RX channel interrupt status word
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*/
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__attribute__((always_inline))
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static inline uint32_t gdma_ll_rx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel, bool raw)
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{
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if (raw) {
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return dev->intr[channel].raw.val & GDMA_LL_RX_EVENT_MASK;
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} else {
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return dev->intr[channel].st.val & GDMA_LL_RX_EVENT_MASK;
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}
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}
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/**
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* @brief Enable DMA RX channel interrupt
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*/
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static inline void gdma_ll_rx_enable_interrupt(gdma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable)
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{
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if (enable) {
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dev->intr[channel].ena.val |= (mask & GDMA_LL_RX_EVENT_MASK);
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} else {
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dev->intr[channel].ena.val &= ~(mask & GDMA_LL_RX_EVENT_MASK);
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}
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}
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/**
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* @brief Clear DMA RX channel interrupt
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*/
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__attribute__((always_inline))
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static inline void gdma_ll_rx_clear_interrupt_status(gdma_dev_t *dev, uint32_t channel, uint32_t mask)
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{
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dev->intr[channel].clr.val = (mask & GDMA_LL_RX_EVENT_MASK);
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}
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/**
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* @brief Get DMA RX channel interrupt status register address
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*/
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static inline volatile void *gdma_ll_rx_get_interrupt_status_reg(gdma_dev_t *dev, uint32_t channel)
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{
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return (volatile void *)(&dev->intr[channel].st);
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}
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/**
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* @brief Enable DMA RX channel to check the owner bit in the descriptor, disabled by default
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*/
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static inline void gdma_ll_rx_enable_owner_check(gdma_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->channel[channel].in.in_conf1.in_check_owner = enable;
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}
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/**
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* @brief Enable DMA RX channel burst reading data, disabled by default
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*/
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static inline void gdma_ll_rx_enable_data_burst(gdma_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->channel[channel].in.in_conf0.in_data_burst_en = enable;
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}
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/**
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* @brief Enable DMA RX channel burst reading descriptor link, disabled by default
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*/
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static inline void gdma_ll_rx_enable_descriptor_burst(gdma_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->channel[channel].in.in_conf0.indscr_burst_en = enable;
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}
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/**
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* @brief Reset DMA RX channel FSM and FIFO pointer
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*/
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__attribute__((always_inline))
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static inline void gdma_ll_rx_reset_channel(gdma_dev_t *dev, uint32_t channel)
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{
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dev->channel[channel].in.in_conf0.in_rst = 1;
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dev->channel[channel].in.in_conf0.in_rst = 0;
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}
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/**
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* @brief Check if DMA RX FIFO is full
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* @param fifo_level only supports level 1
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*/
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static inline bool gdma_ll_rx_is_fifo_full(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
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{
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return dev->channel[channel].in.infifo_status.val & 0x01;
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}
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/**
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* @brief Check if DMA RX FIFO is empty
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* @param fifo_level only supports level 1
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*/
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static inline bool gdma_ll_rx_is_fifo_empty(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
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{
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return dev->channel[channel].in.infifo_status.val & 0x02;
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}
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/**
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* @brief Get number of bytes in RX FIFO
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* @param fifo_level only supports level 1
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*/
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static inline uint32_t gdma_ll_rx_get_fifo_bytes(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
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{
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return dev->channel[channel].in.infifo_status.infifo_cnt;
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}
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/**
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* @brief Pop data from DMA RX FIFO
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*/
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static inline uint32_t gdma_ll_rx_pop_data(gdma_dev_t *dev, uint32_t channel)
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{
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dev->channel[channel].in.in_pop.infifo_pop = 1;
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return dev->channel[channel].in.in_pop.infifo_rdata;
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}
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/**
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* @brief Set the descriptor link base address for RX channel
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*/
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__attribute__((always_inline))
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static inline void gdma_ll_rx_set_desc_addr(gdma_dev_t *dev, uint32_t channel, uint32_t addr)
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{
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dev->channel[channel].in.in_link.addr = addr;
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}
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/**
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* @brief Start dealing with RX descriptors
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*/
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__attribute__((always_inline))
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static inline void gdma_ll_rx_start(gdma_dev_t *dev, uint32_t channel)
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{
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dev->channel[channel].in.in_link.start = 1;
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}
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/**
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* @brief Stop dealing with RX descriptors
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*/
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__attribute__((always_inline))
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static inline void gdma_ll_rx_stop(gdma_dev_t *dev, uint32_t channel)
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{
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dev->channel[channel].in.in_link.stop = 1;
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}
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/**
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* @brief Restart a new inlink right after the last descriptor
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*/
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__attribute__((always_inline))
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static inline void gdma_ll_rx_restart(gdma_dev_t *dev, uint32_t channel)
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{
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dev->channel[channel].in.in_link.restart = 1;
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}
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/**
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* @brief Enable DMA RX to return the address of current descriptor when receives error
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*/
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static inline void gdma_ll_rx_enable_auto_return(gdma_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->channel[channel].in.in_link.auto_ret = enable;
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}
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/**
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* @brief Check if DMA RX descriptor FSM is in IDLE state
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*/
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static inline bool gdma_ll_rx_is_desc_fsm_idle(gdma_dev_t *dev, uint32_t channel)
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{
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return dev->channel[channel].in.in_link.park;
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}
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/**
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* @brief Get RX success EOF descriptor's address
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*/
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__attribute__((always_inline))
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static inline uint32_t gdma_ll_rx_get_success_eof_desc_addr(gdma_dev_t *dev, uint32_t channel)
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{
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return dev->channel[channel].in.in_suc_eof_des_addr;
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}
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/**
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* @brief Get RX error EOF descriptor's address
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*/
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__attribute__((always_inline))
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static inline uint32_t gdma_ll_rx_get_error_eof_desc_addr(gdma_dev_t *dev, uint32_t channel)
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{
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return dev->channel[channel].in.in_err_eof_des_addr;
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}
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/**
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* @brief Get the pre-fetched RX descriptor's address
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*/
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__attribute__((always_inline))
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static inline uint32_t gdma_ll_rx_get_prefetched_desc_addr(gdma_dev_t *dev, uint32_t channel)
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{
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return dev->channel[channel].in.in_dscr;
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}
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/**
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* @brief Set priority for DMA RX channel
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*/
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static inline void gdma_ll_rx_set_priority(gdma_dev_t *dev, uint32_t channel, uint32_t prio)
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{
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dev->channel[channel].in.in_pri.rx_pri = prio;
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}
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/**
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* @brief Connect DMA RX channel to a given peripheral
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*/
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static inline void gdma_ll_rx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, int periph_id)
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{
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dev->channel[channel].in.in_peri_sel.sel = periph_id;
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dev->channel[channel].in.in_conf0.mem_trans_en = false;
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}
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/**
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* @brief Connect DMA RX channel to memory (M2M mode)
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*/
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static inline void gdma_ll_rx_connect_to_mem(gdma_dev_t *dev, uint32_t channel, int dummy_id)
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{
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dev->channel[channel].in.in_peri_sel.sel = dummy_id;
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dev->channel[channel].in.in_conf0.mem_trans_en = true;
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}
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/**
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* @brief Disconnect DMA RX channel from all peripherals
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*/
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static inline void gdma_ll_rx_disconnect_all(gdma_dev_t *dev, uint32_t channel)
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{
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dev->channel[channel].in.in_peri_sel.sel = 0x3F;
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dev->channel[channel].in.in_conf0.mem_trans_en = false;
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}
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///////////////////////////////////// TX /////////////////////////////////////////
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/**
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* @brief Get DMA TX channel interrupt status word
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*/
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__attribute__((always_inline))
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static inline uint32_t gdma_ll_tx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel, bool raw)
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{
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if (raw) {
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return dev->intr[channel].raw.val & GDMA_LL_TX_EVENT_MASK;
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} else {
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return dev->intr[channel].st.val & GDMA_LL_TX_EVENT_MASK;
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}
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}
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/**
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* @brief Enable DMA TX channel interrupt
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*/
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static inline void gdma_ll_tx_enable_interrupt(gdma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable)
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{
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if (enable) {
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dev->intr[channel].ena.val |= (mask & GDMA_LL_TX_EVENT_MASK);
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} else {
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dev->intr[channel].ena.val &= ~(mask & GDMA_LL_TX_EVENT_MASK);
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}
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}
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/**
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* @brief Clear DMA TX channel interrupt
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*/
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__attribute__((always_inline))
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static inline void gdma_ll_tx_clear_interrupt_status(gdma_dev_t *dev, uint32_t channel, uint32_t mask)
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{
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dev->intr[channel].clr.val = (mask & GDMA_LL_TX_EVENT_MASK);
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}
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/**
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* @brief Get DMA TX channel interrupt status register address
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*/
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static inline volatile void *gdma_ll_tx_get_interrupt_status_reg(gdma_dev_t *dev, uint32_t channel)
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{
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return (volatile void *)(&dev->intr[channel].st);
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}
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/**
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* @brief Enable DMA TX channel to check the owner bit in the descriptor, disabled by default
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*/
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static inline void gdma_ll_tx_enable_owner_check(gdma_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->channel[channel].out.out_conf1.out_check_owner = enable;
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}
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/**
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* @brief Enable DMA TX channel burst sending data, disabled by default
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*/
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static inline void gdma_ll_tx_enable_data_burst(gdma_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->channel[channel].out.out_conf0.out_data_burst_en = enable;
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}
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/**
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* @brief Enable DMA TX channel burst reading descriptor link, disabled by default
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*/
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static inline void gdma_ll_tx_enable_descriptor_burst(gdma_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->channel[channel].out.out_conf0.outdscr_burst_en = enable;
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}
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/**
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* @brief Set TX channel EOF mode
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*/
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static inline void gdma_ll_tx_set_eof_mode(gdma_dev_t *dev, uint32_t channel, uint32_t mode)
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{
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dev->channel[channel].out.out_conf0.out_eof_mode = mode;
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}
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/**
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* @brief Enable DMA TX channel automatic write results back to descriptor after all data has been sent out, disabled by default
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*/
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static inline void gdma_ll_tx_enable_auto_write_back(gdma_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->channel[channel].out.out_conf0.out_auto_wrback = enable;
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}
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/**
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* @brief Reset DMA TX channel FSM and FIFO pointer
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*/
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__attribute__((always_inline))
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static inline void gdma_ll_tx_reset_channel(gdma_dev_t *dev, uint32_t channel)
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{
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dev->channel[channel].out.out_conf0.out_rst = 1;
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dev->channel[channel].out.out_conf0.out_rst = 0;
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}
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/**
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* @brief Check if DMA TX FIFO is full
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* @param fifo_level only supports level 1
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*/
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static inline bool gdma_ll_tx_is_fifo_full(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
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{
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return dev->channel[channel].out.outfifo_status.val & 0x01;
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}
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/**
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* @brief Check if DMA TX FIFO is empty
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* @param fifo_level only supports level 1
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*/
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static inline bool gdma_ll_tx_is_fifo_empty(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
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{
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return dev->channel[channel].out.outfifo_status.val & 0x02;
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}
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/**
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* @brief Get number of bytes in TX FIFO
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* @param fifo_level only supports level 1
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*/
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static inline uint32_t gdma_ll_tx_get_fifo_bytes(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
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{
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return dev->channel[channel].out.outfifo_status.outfifo_cnt;
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}
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/**
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* @brief Push data into DMA TX FIFO
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*/
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static inline void gdma_ll_tx_push_data(gdma_dev_t *dev, uint32_t channel, uint32_t data)
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{
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dev->channel[channel].out.out_push.outfifo_wdata = data;
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dev->channel[channel].out.out_push.outfifo_push = 1;
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}
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/**
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* @brief Set the descriptor link base address for TX channel
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*/
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__attribute__((always_inline))
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static inline void gdma_ll_tx_set_desc_addr(gdma_dev_t *dev, uint32_t channel, uint32_t addr)
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{
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dev->channel[channel].out.out_link.addr = addr;
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}
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/**
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* @brief Start dealing with TX descriptors
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*/
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__attribute__((always_inline))
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static inline void gdma_ll_tx_start(gdma_dev_t *dev, uint32_t channel)
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{
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|
dev->channel[channel].out.out_link.start = 1;
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}
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|
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/**
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|
* @brief Stop dealing with TX descriptors
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|
*/
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__attribute__((always_inline))
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static inline void gdma_ll_tx_stop(gdma_dev_t *dev, uint32_t channel)
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|
{
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|
dev->channel[channel].out.out_link.stop = 1;
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}
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|
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/**
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|
* @brief Restart a new outlink right after the last descriptor
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|
*/
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|
__attribute__((always_inline))
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static inline void gdma_ll_tx_restart(gdma_dev_t *dev, uint32_t channel)
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|
{
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|
dev->channel[channel].out.out_link.restart = 1;
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|
}
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|
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|
/**
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|
* @brief Check if DMA TX descriptor FSM is in IDLE state
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|
*/
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|
static inline bool gdma_ll_tx_is_desc_fsm_idle(gdma_dev_t *dev, uint32_t channel)
|
|
{
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|
return dev->channel[channel].out.out_link.park;
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|
}
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|
|
|
/**
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|
* @brief Get TX EOF descriptor's address
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|
*/
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|
__attribute__((always_inline))
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|
static inline uint32_t gdma_ll_tx_get_eof_desc_addr(gdma_dev_t *dev, uint32_t channel)
|
|
{
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|
return dev->channel[channel].out.out_eof_des_addr;
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|
}
|
|
|
|
/**
|
|
* @brief Get the pre-fetched TX descriptor's address
|
|
*/
|
|
__attribute__((always_inline))
|
|
static inline uint32_t gdma_ll_tx_get_prefetched_desc_addr(gdma_dev_t *dev, uint32_t channel)
|
|
{
|
|
return dev->channel[channel].out.out_dscr;
|
|
}
|
|
|
|
/**
|
|
* @brief Set priority for DMA TX channel
|
|
*/
|
|
static inline void gdma_ll_tx_set_priority(gdma_dev_t *dev, uint32_t channel, uint32_t prio)
|
|
{
|
|
dev->channel[channel].out.out_pri.tx_pri = prio;
|
|
}
|
|
|
|
/**
|
|
* @brief Connect DMA TX channel to a given peripheral
|
|
*/
|
|
static inline void gdma_ll_tx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, int periph_id)
|
|
{
|
|
dev->channel[channel].out.out_peri_sel.sel = periph_id;
|
|
}
|
|
|
|
/**
|
|
* @brief Connect DMA TX channel to memory (M2M mode)
|
|
*/
|
|
static inline void gdma_ll_tx_connect_to_mem(gdma_dev_t *dev, uint32_t channel, int dummy_id)
|
|
{
|
|
dev->channel[channel].out.out_peri_sel.sel = dummy_id;
|
|
}
|
|
|
|
/**
|
|
* @brief Disconnect DMA TX channel from all peripherals
|
|
*/
|
|
static inline void gdma_ll_tx_disconnect_all(gdma_dev_t *dev, uint32_t channel)
|
|
{
|
|
dev->channel[channel].out.out_peri_sel.sel = 0x3F;
|
|
}
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|