latest v1.1 iteration

2025-07-01 23:50:42 +02:00
parent 5d5fb76eb7
commit 2a058fe8d5
9 changed files with 6426 additions and 101479 deletions
--- a/.gitignore
+++ b/.gitignore
@@ -3,3 +3,4 @@
 jlcpcb/
 .DS_Store
 **/*.bak
+fp-info-cache*
--- a/Control.kicad_dru
+++ b/Control.kicad_dru
@@ -19,115 +19,201 @@
 # TODO new rule: non-plated slots: min diameter/width 1.0mm
 # JLCPCB: "The minimum Non-Plated Slot Width is 1.0mm, please draw the slot outline in the mechanical layer(GML or GKO)""

-(rule "Track width, outer layer (1oz copper)"
-	(layer outer)
-	(condition "A.Type == 'track'")
-	(constraint track_width (min 0.127mm))
-)

-(rule "Track spacing, outer layer (1oz copper)"
-	(layer outer)
-	(condition "A.Type == 'track' && B.Type == A.Type")
-	(constraint clearance (min 0.127mm))
-)
+# --- Drill/Hole Size ---

-(rule "Track width, inner layer"
-	(layer inner)
-	(condition "A.Type == 'track'")
-	(constraint track_width (min 0.09mm))
-)
-
-(rule "Track spacing, inner layer"
-	(layer inner)
-	(condition "A.Type == 'track' && B.Type == A.Type")
-	(constraint clearance (min 0.09mm))
-)
-
-(rule "Silkscreen text"
-	(layer "?.Silkscreen")
-	(condition "A.Type == 'Text' || A.Type == 'Text Box'")
-	(constraint text_thickness (min 0.15mm))
-	(constraint text_height (min 1mm))
-)
-
-(rule "Pad to Silkscreen"
-	(layer outer)
-	(condition "A.Type == 'pad' && B.Layer == '?.Silkscreen'")
-	(constraint silk_clearance (min 0.15mm))
-)
-
-(rule "Edge (routed) to track clearance"
-	(condition "A.Type == 'track'")
-	(constraint edge_clearance (min 0.3mm))
-)
-
-#(rule "Edge (v-cut) to track clearance"
-#	(condition "A.Type == 'track'")
-#	(constraint edge_clearance (min 0.4mm))
-#)
-
-# JLCPCB restrictions ambiguous:
-# Illustration: 0.2 mm, 1&2 layer: 0.3 mm, multilayer: "(0.15mm more costly)"
-# This rule handles diameter minimum and maximum for ALL holes.
-# Other specialized rules handle restrictions (e.g. Via, PTH, NPTH) 
-(rule "Hole diameter"
+(rule "JLCPCB: Drill Hole Size"
+  # Choose between:
+  # 1-2 Layers
+	# (constraint hole_size (min 0.3mm) (max 6.3mm))
+  # 4-6 Layers (more costly)
+	# (constraint hole_size (min 0.15mm) (max 6.3mm))
+  # 4-6 Layers (preferred)
 	(constraint hole_size (min 0.2mm) (max 6.3mm))
 )

-(rule "Hole (NPTH) diameter"
-	(layer outer)
-	(condition "!A.isPlated()")
-	(constraint hole_size (min 0.5mm))
+(rule "JLCPCB: Via Hole Size"
+	(condition "A.Type == 'Via'")
+  # Choose between:
+  # 1-2 Layers
+	# (constraint hole_size (min 0.3mm))
+  # 4-6 Layers (more costly)
+  # (constraint hole_size (min 0.15mm))
+  # 4-6 Layers (preferred)
+	(constraint hole_size (min 0.2mm))
 )

-# TODO: Hole to board edge ≥ 1 mm. Min. board size 10 × 10 mm
-(rule "Hole (castellated) diameter"
-	(layer outer)
-	(condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'")
-	(constraint hole_size (min 0.6mm))
-)
-
-# JLCPCB: "Via diameter should be 0.1mm(0.15mm preferred) larger than Via hole size" (illustration shows diameters for both dimensions)
-# JLCPCB: PTH: "The annular ring size will be enlarged to 0.15mm in production."
-(rule "Annular ring width (via and PTH)"
-	(layer outer)
-	(condition "A.isPlated()")
+(rule "JLCPCB: Via Annular Ring"
+	(condition "A.Type == 'Via'")
+  # Choose between:
+  # 1-6 Layers
+  # (constraint annular_width (min 0.05mm))
+  # 1-6 Layers (preferred)
 	(constraint annular_width (min 0.075mm))
 )

-(rule "Clearance: hole to hole (perimeter), different nets"
+(rule "JLCPCB: PTH Hole Size"
+	(condition "A.Type == 'Pad' && A.Pad_Type == 'Through-hole' && A.isPlated()")
+	(constraint hole_size (min 0.2mm) (max 6.3mm))
+)
+
+(rule "JLCPCB: NPTH Hole Size"
+	(condition "A.Type == 'Pad' && A.Pad_Type == 'NPTH, mechanical' && !A.isPlated()")
+	(constraint hole_size (min 0.5mm))
+)
+
+# TODO: Hole to board edge ≥ 1 mm. Min. board size 10 × 10 mm.
+(rule "JLCPCB: Castellated Hole Size"
 	(layer outer)
+	(condition "A.Type == 'Pad' && A.Fabrication_Property == 'Castellated pad'")
+	(constraint hole_size (min 0.6mm))
+)
+
+(rule "JLCPCB: PTH Annular Ring"
+	(condition "A.Type == 'Pad' && A.Pad_Type == 'Through-hole' && A.isPlated()")
+	(constraint annular_width (min 0.075mm))
+)
+
+(rule "JLCPCB: NPTH Annular Ring"
+	(condition "A.Type == 'Pad' && A.Pad_Type == 'NPTH, mechanical' && !A.isPlated()")
+	(constraint annular_width (min 0.25mm))
+)
+
+# An expensive 4-Wire Kelvin Test is automatically added for holes that are < 0.3mm with a diameter ≤ 0.4mm.
+(rule "JLCPCB: Avoid 4-Wire Kelvin Test"
+	(condition "(A.Type == 'Via' && A.Hole < 0.3mm && A.Diameter <= 0.4mm) || (A.Type == 'Pad' && ((A.Hole_Size_X < 0.3mm && A.Size_X <= 0.4mm) || (A.Hole_Size_Y < 0.3mm && A.Size_Y <= 0.4mm)))")
+  # 4-6 Layers
+  (constraint annular_width (min 0.125mm))
+)
+
+
+# --- Minimum Clearance ---
+
+(rule "JLCPCB: Hole to Hole Clearance (Different Nets)"
 	(condition "A.Net != B.Net")
 	(constraint hole_to_hole (min 0.5mm))
 )

-(rule "Clearance: hole to hole (perimeter), same net"
-	(layer outer)
-	(condition "A.Net == B.Net")
+(rule "JLCPCB: Via Hole to Via Hole Clearance (Same Net)"
+	(condition "A.Type == 'Via' && B.Type == 'Via' && A.Net == B.Net")
 	(constraint hole_to_hole (min 0.254mm))
 )

-(rule "Clearance: track to NPTH hole (perimeter)"
-#	(condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track' && A.Net != B.Net")
-	(condition "!A.isPlated() && B.Type == 'track' && A.Net != B.Net")
-	(constraint hole_clearance (min 0.254mm))
-)
-
-(rule "Clearance: track to PTH hole perimeter"
-	(condition "A.isPlated() && B.Type == 'track' && A.Net != B.Net")
-	(constraint hole_clearance (min 0.33mm))
-)
-
-# TODO: try combining with rule "Clearance: PTH to track, different nets"
-(rule "Clearance: track to pad"
-	(condition "A.Type == 'pad' && B.Type == 'track' &&  A.Net != B.Net")
-	(constraint clearance (min 0.2mm))
-)
-
-(rule "Clearance: pad/via to pad/via"
-	(layer outer)
-#	(condition "(A.Type == 'Pad' || A.Type == 'Via') && (B.Type == 'Pad' || B.Type == 'Via') && A.Net != B.Net")	
-	(condition "A.isPlated() && B.isPlated() && A.Net != B.Net")
+(rule "JLCPCB: Pad to Pad Clearance (Pad without Hole, Different Nets)"
+	(condition "A.Type == 'Pad' && (A.Pad_Type != 'Through-hole' && A.Pad_Type != 'NPTH, mechanical') && B.Type == 'Pad' && (B.Pad_Type != 'Through-hole' && B.Pad_Type != 'NPTH, mechanical') && A.Net != B.Net")
 	(constraint clearance (min 0.127mm))
 )

+(rule "JLCPCB: Pad Hole to Pad Hole Clearance (Pad with Hole, Different Nets)"
+	(condition "A.Type == 'Pad' && (A.Pad_Type == 'Through-hole' || A.Pad_Type == 'NPTH, mechanical') && B.Type == 'Pad' && (B.Pad_Type == 'Through-hole' || B.Pad_Type == 'NPTH, mechanical') && A.Net != B.Net")
+	(constraint hole_to_hole (min 0.5mm))
+)
+
+# NOTE: This is not stated specifically, but is implied by other rules.
+(rule "JLCPCB: Via/Pad to Via/Pad Clearance (Different Nets)"
+	(condition "(A.Type == 'Pad' || A.Type == 'Via') && (B.Type == 'Pad' || B.Type == 'Via') && A.Net != B.Net")
+	(constraint clearance (min 0.127mm))
+)
+
+# NOTE: This is not stated specifically, but is implied by other rules.
+(rule "JLCPCB: Via/Pad Hole to Via/Pad Hole Clearance (Same Net)"
+	(condition "(A.Type == 'Pad' || A.Type == 'Via') && (B.Type == 'Pad' || B.Type == 'Via') && A.Net == B.Net")
+	(constraint hole_to_hole (min 0.254mm))
+)
+
+(rule "JLCPCB: Via to Trace"
+	(condition "A.Type == 'Via' && B.Type == 'Track'")
+	(constraint hole_clearance (min 0.254mm))
+)
+
+(rule "JLCPCB: PTH to Trace"
+	(condition "A.Type == 'Pad' && A.Pad_Type == 'Through-hole' && A.isPlated() && B.Type == 'Track'")
+	(constraint hole_clearance (min 0.33mm))
+)
+
+(rule "JLCPCB: NPTH to Trace"
+	(condition "A.Type == 'Pad' && A.Pad_Type == 'NPTH, mechanical' && !A.isPlated() && B.Type == 'Track'")
+	(constraint hole_clearance (min 0.254mm))
+)
+
+(rule "JLCPCB: Pad to Trace"
+	(condition "A.Type == 'Pad' && (A.Pad_Type == 'Through-hole' || A.Pad_Type == 'NPTH, mechanical') && B.Type == 'Track' &&  A.Net != B.Net")
+	(constraint clearance (min 0.2mm))
+)
+
+
+# --- Minimum Trace Width and Spacing ---
+
+(rule "JLCPCB: Trace Width (Outer Layer)"
+	(layer outer)
+	(condition "A.Type == 'Track'")
+  # Choose between:
+  # 1-2 Layers (1oz)
+  # (constraint track_width (min 0.127mm))
+  # 4-6 Layers (1oz and 0.5oz)
+	(constraint track_width (min 0.09mm))
+  # 1-6 Layers (2oz)
+  # (constraint track_width (min 0.2mm))
+)
+(rule "JLCPCB: Trace Spacing (Outer Layer)"
+	(layer outer)
+	(condition "A.Type == 'Track' && B.Type == 'Track'")
+  # Choose between:
+  # 1-2 Layers (1oz)
+  # (constraint clearance (min 0.127mm))
+  # 4-6 Layers (1oz and 0.5oz)
+	(constraint clearance (min 0.09mm))
+  # 1-6 Layers (2oz)
+  # (constraint clearance (min 0.2mm))
+)
+
+(rule "JLCPCB: Trace Width (Inner Layer)"
+	(layer inner)
+	(condition "A.Type == 'Track'")
+  # Choose between:
+  # 4-6 Layers (1oz and 0.5oz)
+	(constraint track_width (min 0.09mm))
+  # 4-6 Layers (2oz)
+  # (constraint track_width (min 0.2mm))
+)
+(rule "JLCPCB: Trace Spacing (Inner Layer)"
+	(layer inner)
+	(condition "A.Type == 'Track' && B.Type == 'Track'")
+  # Choose between:
+  # 4-6 Layers (1oz and 0.5oz)
+	(constraint clearance (min 0.09mm))
+  # 4-6 Layers (2oz)
+  # (constraint clearance (min 0.2mm))
+)
+
+
+# --- Legend ---
+
+(rule "JLCPCB: Minimum Line Width"
+	(layer "?.Silkscreen")
+	(condition "A.Type == 'Text' || A.Type == 'Text Box'")
+	(constraint text_thickness (min 0.15mm))
+)
+
+(rule "JLCPCB: Minimum Text Height"
+	(layer "?.Silkscreen")
+	(condition "A.Type == 'Text' || A.Type == 'Text Box'")
+	(constraint text_height (min 1mm))
+)
+
+(rule "JLCPCB: Pad to Silkscreen"
+	(condition "A.Type == 'Pad' && ((A.existsOnLayer('F.Mask') && B.Layer == 'F.Silkscreen') || (A.existsOnLayer('B.Mask') && B.Layer == 'B.Silkscreen')) ")
+	(constraint silk_clearance (min 0.15mm))
+)
+
+
+# --- Board Outlines ---
+
+(rule "JLCPCB: Trace to Board Edge"
+	(condition "A.Type == 'Track'")
+  # Choose between:
+  # Routed
+	(constraint edge_clearance (min 0.3mm))
+  # V-Cut Panel
+	# (constraint edge_clearance (min 0.4mm))
+)
--- a/Control.kicad_pcb
+++ b/Control.kicad_pcb
--- a/Control.kicad_prl
+++ b/Control.kicad_prl
@@ -1,8 +1,8 @@
 {
  "board": {
-    "active_layer": 31,
-    "active_layer_preset": "All Layers",
-    "auto_track_width": true,
+    "active_layer": 0,
+    "active_layer_preset": "",
+    "auto_track_width": false,
    "hidden_netclasses": [],
    "hidden_nets": [
      "GND",
@@ -63,7 +63,6 @@
      33,
      34,
      35,
-      36,
      39,
      40
    ],
--- a/Control.kicad_pro
+++ b/Control.kicad_pro
@@ -444,7 +444,8 @@
      "wemos"
    ],
    "pinned_symbol_libs": [
-      "wemos"
+      "wemos",
+      "easyeda2kicad"
    ]
  },
  "meta": {
@@ -486,6 +487,23 @@
        "via_diameter": 0.6,
        "via_drill": 0.3,
        "wire_width": 6
+      },
+      {
+        "bus_width": 12,
+        "clearance": 0.2,
+        "diff_pair_gap": 0.25,
+        "diff_pair_via_gap": 0.25,
+        "diff_pair_width": 0.2,
+        "line_style": 0,
+        "microvia_diameter": 0.3,
+        "microvia_drill": 0.1,
+        "name": "DOUT",
+        "pcb_color": "rgba(0, 0, 0, 0.000)",
+        "schematic_color": "rgba(0, 0, 0, 0.000)",
+        "track_width": 0.3,
+        "via_diameter": 0.6,
+        "via_drill": 0.3,
+        "wire_width": 6
      }
    ],
    "meta": {
@@ -497,6 +515,10 @@
      {
        "netclass": "+5V",
        "pattern": "*5V"
+      },
+      {
+        "netclass": "DOUT",
+        "pattern": "DOUT"
      }
    ]
  },
--- a/Control.kicad_sch
+++ b/Control.kicad_sch
--- a/96433
+++ b/96433
--- a/1
+++ b/1
@@ -1,4 +1,5 @@
 (fp_lib_table
  (version 7)
  (lib (name "wemos")(type "KiCad")(uri "${KIPRJMOD}/library/wemos.pretty")(options "")(descr ""))
+  (lib (name "easyeda2kicad")(type "KiCad")(uri "${EASYEDA2KICAD}/easyeda2kicad.pretty")(options "")(descr ""))
 )
--- a/1
+++ b/1
@@ -1,4 +1,5 @@
 (sym_lib_table
  (version 7)
  (lib (name "wemos")(type "KiCad")(uri "${KIPRJMOD}/library/wemos.kicad_sym")(options "")(descr ""))
+  (lib (name "easyeda2kicad")(type "KiCad")(uri "${EASYEDA2KICAD}/easyeda2kicad.kicad_sym")(options "")(descr ""))
 )