move into hardware subfolder
This commit is contained in:
Peter Siegmund
219
hardware/Maerklin System Control.kicad_dru
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219
hardware/Maerklin System Control.kicad_dru
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(version 1)
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# Custom Design Rules (DRC) for KiCAD 7.0 (Stored in '<project>.kicad_dru' file).
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#
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# Matching JLCPCB capabilities: https://jlcpcb.com/capabilities/pcb-capabilities
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#
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# KiCad documentation: https://docs.kicad.org/master/id/pcbnew/pcbnew_advanced.html#custom_design_rules
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#
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# Inspiration
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# - https://gist.github.com/darkxst/f713268e5469645425eed40115fb8b49 (with comments)
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# - https://gist.github.com/denniskupec/e163d13b0a64c2044bd259f64659485e (with comments)
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# TODO new rule: NPTH pads.
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# Inner diameter of pad should be 0.4-0.5 mm larger than NPTH drill diameter.
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# JLCPCB: "We make NPTH via dry sealing film process, if customer would like a NPTH but around with pad/copper, our engineer will dig out around pad/copper about 0.2mm-0.25mm, otherwise the metal potion will be flowed into the hole and it becomes a PTH. (there will be no copper dig out optimization for single board)."
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# TODO: new rule for plated slots: min diameter/width 0.5mm
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# JLCPCB: "The minimum plated slot width is 0.5mm, which is drawn with a pad."
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# TODO new rule: non-plated slots: min diameter/width 1.0mm
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# JLCPCB: "The minimum Non-Plated Slot Width is 1.0mm, please draw the slot outline in the mechanical layer(GML or GKO)""
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# --- Drill/Hole Size ---
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(rule "JLCPCB: Drill Hole Size"
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# Choose between:
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# 1-2 Layers
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# (constraint hole_size (min 0.3mm) (max 6.3mm))
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# 4-6 Layers (more costly)
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# (constraint hole_size (min 0.15mm) (max 6.3mm))
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# 4-6 Layers (preferred)
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(constraint hole_size (min 0.2mm) (max 6.3mm))
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)
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(rule "JLCPCB: Via Hole Size"
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(condition "A.Type == 'Via'")
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# Choose between:
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# 1-2 Layers
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# (constraint hole_size (min 0.3mm))
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# 4-6 Layers (more costly)
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# (constraint hole_size (min 0.15mm))
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# 4-6 Layers (preferred)
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(constraint hole_size (min 0.2mm))
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)
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(rule "JLCPCB: Via Annular Ring"
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(condition "A.Type == 'Via'")
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# Choose between:
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# 1-6 Layers
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# (constraint annular_width (min 0.05mm))
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# 1-6 Layers (preferred)
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(constraint annular_width (min 0.075mm))
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)
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(rule "JLCPCB: PTH Hole Size"
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(condition "A.Type == 'Pad' && A.Pad_Type == 'Through-hole' && A.isPlated()")
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(constraint hole_size (min 0.2mm) (max 6.3mm))
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)
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(rule "JLCPCB: NPTH Hole Size"
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(condition "A.Type == 'Pad' && A.Pad_Type == 'NPTH, mechanical' && !A.isPlated()")
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(constraint hole_size (min 0.5mm))
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)
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# TODO: Hole to board edge ≥ 1 mm. Min. board size 10 × 10 mm.
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(rule "JLCPCB: Castellated Hole Size"
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(layer outer)
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(condition "A.Type == 'Pad' && A.Fabrication_Property == 'Castellated pad'")
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(constraint hole_size (min 0.6mm))
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)
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(rule "JLCPCB: PTH Annular Ring"
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(condition "A.Type == 'Pad' && A.Pad_Type == 'Through-hole' && A.isPlated()")
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(constraint annular_width (min 0.075mm))
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)
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(rule "JLCPCB: NPTH Annular Ring"
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(condition "A.Type == 'Pad' && A.Pad_Type == 'NPTH, mechanical' && !A.isPlated()")
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(constraint annular_width (min 0.25mm))
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)
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# An expensive 4-Wire Kelvin Test is automatically added for holes that are < 0.3mm with a diameter ≤ 0.4mm.
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(rule "JLCPCB: Avoid 4-Wire Kelvin Test"
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(condition "(A.Type == 'Via' && A.Hole < 0.3mm && A.Diameter <= 0.4mm) || (A.Type == 'Pad' && ((A.Hole_Size_X < 0.3mm && A.Size_X <= 0.4mm) || (A.Hole_Size_Y < 0.3mm && A.Size_Y <= 0.4mm)))")
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# 4-6 Layers
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(constraint annular_width (min 0.125mm))
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)
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# --- Minimum Clearance ---
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(rule "JLCPCB: Hole to Hole Clearance (Different Nets)"
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(condition "A.Net != B.Net")
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(constraint hole_to_hole (min 0.5mm))
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)
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(rule "JLCPCB: Via Hole to Via Hole Clearance (Same Net)"
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(condition "A.Type == 'Via' && B.Type == 'Via' && A.Net == B.Net")
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(constraint hole_to_hole (min 0.254mm))
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)
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(rule "JLCPCB: Pad to Pad Clearance (Pad without Hole, Different Nets)"
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(condition "A.Type == 'Pad' && (A.Pad_Type != 'Through-hole' && A.Pad_Type != 'NPTH, mechanical') && B.Type == 'Pad' && (B.Pad_Type != 'Through-hole' && B.Pad_Type != 'NPTH, mechanical') && A.Net != B.Net")
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(constraint clearance (min 0.127mm))
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)
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(rule "JLCPCB: Pad Hole to Pad Hole Clearance (Pad with Hole, Different Nets)"
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(condition "A.Type == 'Pad' && (A.Pad_Type == 'Through-hole' || A.Pad_Type == 'NPTH, mechanical') && B.Type == 'Pad' && (B.Pad_Type == 'Through-hole' || B.Pad_Type == 'NPTH, mechanical') && A.Net != B.Net")
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(constraint hole_to_hole (min 0.5mm))
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)
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# NOTE: This is not stated specifically, but is implied by other rules.
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(rule "JLCPCB: Via/Pad to Via/Pad Clearance (Different Nets)"
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(condition "(A.Type == 'Pad' || A.Type == 'Via') && (B.Type == 'Pad' || B.Type == 'Via') && A.Net != B.Net")
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(constraint clearance (min 0.127mm))
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)
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# NOTE: This is not stated specifically, but is implied by other rules.
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(rule "JLCPCB: Via/Pad Hole to Via/Pad Hole Clearance (Same Net)"
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(condition "(A.Type == 'Pad' || A.Type == 'Via') && (B.Type == 'Pad' || B.Type == 'Via') && A.Net == B.Net")
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(constraint hole_to_hole (min 0.254mm))
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)
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(rule "JLCPCB: Via to Trace"
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(condition "A.Type == 'Via' && B.Type == 'Track'")
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(constraint hole_clearance (min 0.254mm))
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)
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(rule "JLCPCB: PTH to Trace"
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(condition "A.Type == 'Pad' && A.Pad_Type == 'Through-hole' && A.isPlated() && B.Type == 'Track'")
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(constraint hole_clearance (min 0.33mm))
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)
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(rule "JLCPCB: NPTH to Trace"
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(condition "A.Type == 'Pad' && A.Pad_Type == 'NPTH, mechanical' && !A.isPlated() && B.Type == 'Track'")
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(constraint hole_clearance (min 0.254mm))
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)
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(rule "JLCPCB: Pad to Trace"
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(condition "A.Type == 'Pad' && (A.Pad_Type == 'Through-hole' || A.Pad_Type == 'NPTH, mechanical') && B.Type == 'Track' && A.Net != B.Net")
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(constraint clearance (min 0.2mm))
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)
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# --- Minimum Trace Width and Spacing ---
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(rule "JLCPCB: Trace Width (Outer Layer)"
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(layer outer)
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(condition "A.Type == 'Track'")
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# Choose between:
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# 1-2 Layers (1oz)
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# (constraint track_width (min 0.127mm))
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# 4-6 Layers (1oz and 0.5oz)
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(constraint track_width (min 0.09mm))
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# 1-6 Layers (2oz)
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# (constraint track_width (min 0.2mm))
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)
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(rule "JLCPCB: Trace Spacing (Outer Layer)"
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(layer outer)
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(condition "A.Type == 'Track' && B.Type == 'Track'")
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# Choose between:
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# 1-2 Layers (1oz)
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# (constraint clearance (min 0.127mm))
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# 4-6 Layers (1oz and 0.5oz)
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(constraint clearance (min 0.09mm))
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# 1-6 Layers (2oz)
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# (constraint clearance (min 0.2mm))
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)
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(rule "JLCPCB: Trace Width (Inner Layer)"
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(layer inner)
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(condition "A.Type == 'Track'")
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# Choose between:
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# 4-6 Layers (1oz and 0.5oz)
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(constraint track_width (min 0.09mm))
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# 4-6 Layers (2oz)
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# (constraint track_width (min 0.2mm))
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)
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(rule "JLCPCB: Trace Spacing (Inner Layer)"
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(layer inner)
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(condition "A.Type == 'Track' && B.Type == 'Track'")
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# Choose between:
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# 4-6 Layers (1oz and 0.5oz)
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(constraint clearance (min 0.09mm))
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# 4-6 Layers (2oz)
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# (constraint clearance (min 0.2mm))
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)
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# --- Legend ---
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(rule "JLCPCB: Minimum Line Width"
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(layer "?.Silkscreen")
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(condition "A.Type == 'Text' || A.Type == 'Text Box'")
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(constraint text_thickness (min 0.15mm))
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)
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(rule "JLCPCB: Minimum Text Height"
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(layer "?.Silkscreen")
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(condition "A.Type == 'Text' || A.Type == 'Text Box'")
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(constraint text_height (min 1mm))
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)
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(rule "JLCPCB: Pad to Silkscreen"
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(condition "A.Type == 'Pad' && ((A.existsOnLayer('F.Mask') && B.Layer == 'F.Silkscreen') || (A.existsOnLayer('B.Mask') && B.Layer == 'B.Silkscreen')) ")
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(constraint silk_clearance (min 0.15mm))
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)
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# --- Board Outlines ---
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(rule "JLCPCB: Trace to Board Edge"
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(condition "A.Type == 'Track'")
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# Choose between:
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# Routed
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(constraint edge_clearance (min 0.3mm))
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# V-Cut Panel
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# (constraint edge_clearance (min 0.4mm))
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)
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