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fix(cache): fixed preload ascending issue

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This commit is contained in:
armando
2026-04-13 13:11:40 +08:00
committed by Armando (Dou Yiwen)
parent 338f341110
commit 0099a7fff1
17 changed files with 154 additions and 72 deletions
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components/esp_lcd/rgb/esp_lcd_panel_rgb.c
+1 -1
View File
@@ -954,7 +954,7 @@ static IRAM_ATTR bool lcd_rgb_panel_fill_bounce_buffer(esp_rgb_panel_t *panel, u
if (panel->num_fbs > 0 && panel->flags.fb_behind_cache) {
cache_hal_preload(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_DATA,
(uint32_t)&panel->fbs[panel->bb_fb_index][panel->bounce_pos_px * bytes_per_pixel],
panel->bb_size, false);
panel->bb_size, CACHE_PRELOAD_ORDER_ASCENDING);
}
return need_yield;
}
components/hal/cache_hal.c
+2 -2
View File
@@ -328,9 +328,9 @@ uint32_t cache_hal_get_cache_line_size(uint32_t cache_level, cache_type_t type)
return line_size;
}
void cache_hal_preload(uint32_t cache_level, cache_type_t type, uint32_t vaddr, uint32_t size, bool ascending)
void cache_hal_preload(uint32_t cache_level, cache_type_t type, uint32_t vaddr, uint32_t size, cache_preload_order_t order)
{
cache_ll_preload(cache_level, type, CACHE_LL_ID_ALL, vaddr, size, ascending);
cache_ll_preload(cache_level, type, CACHE_LL_ID_ALL, vaddr, size, order);
}
void cache_hal_preload_wait_done(uint32_t cache_level, cache_type_t type)
components/hal/esp32/cache_hal_esp32.c
+1 -1
View File
@@ -77,7 +77,7 @@ bool cache_hal_invalidate_addr(uint32_t vaddr, uint32_t size)
abort();
}
void cache_hal_preload(uint32_t cache_level, cache_type_t type, uint32_t vaddr, uint32_t size, bool ascending)
void cache_hal_preload(uint32_t cache_level, cache_type_t type, uint32_t vaddr, uint32_t size, cache_preload_order_t order)
{
//not supported, for compatibility
}
components/hal/esp32c2/include/hal/cache_ll.h
+3 -2
View File
@@ -53,6 +53,7 @@ typedef enum {
CACHE_LL_PRELOAD_ARBITRARY = 2,
} cache_ll_preload_strategy_t;
/**
* @brief Initialize the cache clock
*/
@@ -222,14 +223,14 @@ static inline void cache_ll_preload_set_strategy(uint32_t cache_level, cache_typ
* @brief Preload cache (no-op; ROM has no manual preload API)
*/
__attribute__((always_inline))
static inline void cache_ll_preload(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size, bool ascending)
static inline void cache_ll_preload(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size, cache_preload_order_t order)
{
(void)cache_level;
(void)type;
(void)cache_id;
(void)vaddr;
(void)size;
(void)ascending;
(void)order;
}
/**
components/hal/esp32c3/include/hal/cache_ll.h
+10 -2
View File
@@ -52,6 +52,7 @@ typedef enum {
CACHE_LL_PRELOAD_ARBITRARY = 2,
} cache_ll_preload_strategy_t;
/**
* @brief Initialize the cache clock
*/
@@ -227,16 +228,23 @@ static inline void cache_ll_preload_set_strategy(uint32_t cache_level, cache_typ
* Starts preload for the given region and does not wait. Use
* cache_ll_preload_wait_done() to wait for completion.
* DATA type is no-op.
*
* @param cache_level level of the cache (must be CACHE_LL_LEVEL_EXT_MEM)
* @param type see `cache_type_t` (only INSTRUCTION and ALL trigger preload)
* @param cache_id id of the cache (unused on C3; pass 0 or CACHE_LL_ID_ALL)
* @param vaddr start virtual address of the preload region
* @param size size of the preload region in bytes
* @param order preload order, see `cache_preload_order_t`
*/
__attribute__((always_inline))
static inline void cache_ll_preload(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size, bool ascending)
static inline void cache_ll_preload(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size, cache_preload_order_t order)
{
(void)cache_id;
HAL_ASSERT(cache_level == CACHE_LL_LEVEL_EXT_MEM);
if (type == CACHE_TYPE_DATA) {
return;
}
Cache_Start_ICache_Preload(vaddr, size, ascending ? 0 : 1);
Cache_Start_ICache_Preload(vaddr, size, order);
}
/**
components/hal/esp32c5/include/hal/cache_ll.h
+10 -2
View File
@@ -43,6 +43,7 @@ typedef enum {
CACHE_LL_PRELOAD_ARBITRARY = 2,
} cache_ll_preload_strategy_t;
/**
* @brief Initialize the cache clock
*/
@@ -219,14 +220,21 @@ static inline void cache_ll_preload_set_strategy(uint32_t cache_level, cache_typ
* @brief Preload cache (L1 unified)
*
* Starts preload and does not wait. Use cache_ll_preload_wait_done() to wait for completion.
*
* @param cache_level level of the cache (CACHE_LL_LEVEL_EXT_MEM or CACHE_LL_LEVEL_ALL)
* @param type see `cache_type_t`
* @param cache_id id of the cache (unused; pass 0)
* @param vaddr start virtual address of the preload region
* @param size size of the preload region in bytes
* @param order preload order, see `cache_preload_order_t`
*/
__attribute__((always_inline))
static inline void cache_ll_preload(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size, bool ascending)
static inline void cache_ll_preload(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size, cache_preload_order_t order)
{
(void)cache_id;
(void)type;
HAL_ASSERT(cache_level == CACHE_LL_LEVEL_EXT_MEM);
Cache_Start_Preload(vaddr, size, ascending ? 0 : 1);
Cache_Start_Preload(vaddr, size, order);
}
/**
components/hal/esp32c6/include/hal/cache_ll.h
+10 -2
View File
@@ -43,6 +43,7 @@ typedef enum {
CACHE_LL_PRELOAD_ARBITRARY = 2,
} cache_ll_preload_strategy_t;
/**
* @brief Initialize the cache clock
*/
@@ -203,16 +204,23 @@ static inline void cache_ll_preload_set_strategy(uint32_t cache_level, cache_typ
*
* Starts preload and does not wait. Use cache_ll_preload_wait_done() to wait for completion.
* DATA type is no-op.
*
* @param cache_level level of the cache (CACHE_LL_LEVEL_EXT_MEM or CACHE_LL_LEVEL_ALL)
* @param type see `cache_type_t` (only INSTRUCTION and ALL trigger preload)
* @param cache_id id of the cache (unused; pass 0)
* @param vaddr start virtual address of the preload region
* @param size size of the preload region in bytes
* @param order preload order, see `cache_preload_order_t`
*/
__attribute__((always_inline))
static inline void cache_ll_preload(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size, bool ascending)
static inline void cache_ll_preload(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size, cache_preload_order_t order)
{
(void)cache_id;
HAL_ASSERT(cache_level == CACHE_LL_LEVEL_EXT_MEM);
if (type == CACHE_TYPE_DATA) {
return;
}
Cache_Start_ICache_Preload(vaddr, size, ascending ? 0 : 1);
Cache_Start_ICache_Preload(vaddr, size, order);
}
/**
components/hal/esp32c61/include/hal/cache_ll.h
+10 -2
View File
@@ -42,6 +42,7 @@ typedef enum {
CACHE_LL_PRELOAD_ARBITRARY = 2,
} cache_ll_preload_strategy_t;
/**
* @brief Initialize the cache clock
*/
@@ -218,14 +219,21 @@ static inline void cache_ll_preload_set_strategy(uint32_t cache_level, cache_typ
* @brief Preload cache (L1 unified)
*
* Starts preload and does not wait. Use cache_ll_preload_wait_done() to wait for completion.
*
* @param cache_level level of the cache (CACHE_LL_LEVEL_EXT_MEM or CACHE_LL_LEVEL_ALL)
* @param type see `cache_type_t`
* @param cache_id id of the cache (unused; pass 0)
* @param vaddr start virtual address of the preload region
* @param size size of the preload region in bytes
* @param order preload order, see `cache_preload_order_t`
*/
__attribute__((always_inline))
static inline void cache_ll_preload(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size, bool ascending)
static inline void cache_ll_preload(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size, cache_preload_order_t order)
{
(void)cache_id;
(void)type;
HAL_ASSERT(cache_level == CACHE_LL_LEVEL_EXT_MEM);
Cache_Start_Preload(vaddr, size, ascending ? 0 : 1);
Cache_Start_Preload(vaddr, size, order);
}
/**
components/hal/esp32h2/include/hal/cache_ll.h
+10 -2
View File
@@ -42,6 +42,7 @@ typedef enum {
CACHE_LL_PRELOAD_ARBITRARY = 2,
} cache_ll_preload_strategy_t;
/**
* @brief Initialize the cache clock
*/
@@ -201,16 +202,23 @@ static inline void cache_ll_preload_set_strategy(uint32_t cache_level, cache_typ
*
* Starts preload and does not wait. Use cache_ll_preload_wait_done() to wait for completion.
* DATA type is no-op.
*
* @param cache_level level of the cache (CACHE_LL_LEVEL_EXT_MEM or CACHE_LL_LEVEL_ALL)
* @param type see `cache_type_t` (only INSTRUCTION and ALL trigger preload)
* @param cache_id id of the cache (unused; pass 0)
* @param vaddr start virtual address of the preload region
* @param size size of the preload region in bytes
* @param order preload order, see `cache_preload_order_t`
*/
__attribute__((always_inline))
static inline void cache_ll_preload(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size, bool ascending)
static inline void cache_ll_preload(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size, cache_preload_order_t order)
{
(void)cache_id;
HAL_ASSERT(cache_level == CACHE_LL_LEVEL_EXT_MEM);
if (type == CACHE_TYPE_DATA) {
return;
}
Cache_Start_ICache_Preload(vaddr, size, ascending ? 0 : 1);
Cache_Start_ICache_Preload(vaddr, size, order);
}
/**
components/hal/esp32h21/include/hal/cache_ll.h
+10 -2
View File
@@ -43,6 +43,7 @@ typedef enum {
CACHE_LL_PRELOAD_ARBITRARY = 2,
} cache_ll_preload_strategy_t;
/**
* @brief Initialize the cache clock
*/
@@ -202,16 +203,23 @@ static inline void cache_ll_preload_set_strategy(uint32_t cache_level, cache_typ
*
* Starts preload and does not wait. Use cache_ll_preload_wait_done() to wait for completion.
* DATA type is no-op.
*
* @param cache_level level of the cache (CACHE_LL_LEVEL_EXT_MEM or CACHE_LL_LEVEL_ALL)
* @param type see `cache_type_t` (only INSTRUCTION and ALL trigger preload)
* @param cache_id id of the cache (unused; pass 0)
* @param vaddr start virtual address of the preload region
* @param size size of the preload region in bytes
* @param order preload order, see `cache_preload_order_t`
*/
__attribute__((always_inline))
static inline void cache_ll_preload(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size, bool ascending)
static inline void cache_ll_preload(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size, cache_preload_order_t order)
{
(void)cache_id;
HAL_ASSERT(cache_level == CACHE_LL_LEVEL_EXT_MEM);
if (type == CACHE_TYPE_DATA) {
return;
}
Cache_Start_ICache_Preload(vaddr, size, ascending ? 0 : 1);
Cache_Start_ICache_Preload(vaddr, size, order);
}
/**
components/hal/esp32h4/include/hal/cache_ll.h
+10 -2
View File
@@ -43,6 +43,7 @@ typedef enum {
CACHE_LL_PRELOAD_ARBITRARY = 2,
} cache_ll_preload_strategy_t;
/**
* @brief Initialize the cache clock
*/
@@ -718,9 +719,16 @@ static inline void cache_ll_preload_set_strategy(uint32_t cache_level, cache_typ
* @brief Preload cache (L1 only)
*
* Starts preload for the given map and does not wait. Use cache_ll_preload_wait_done() to wait for completion.
*
* @param cache_level level of the cache (must be CACHE_LL_LEVEL_EXT_MEM)
* @param type see `cache_type_t` (selects instruction/data/all cache map)
* @param cache_id id of the cache (unused on H4; pass 0)
* @param vaddr start virtual address of the preload region
* @param size size of the preload region in bytes
* @param order preload order, see `cache_preload_order_t`
*/
__attribute__((always_inline))
static inline void cache_ll_preload(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size, bool ascending)
static inline void cache_ll_preload(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size, cache_preload_order_t order)
{
(void)cache_id;
HAL_ASSERT(cache_level == CACHE_LL_LEVEL_EXT_MEM);
@@ -737,7 +745,7 @@ static inline void cache_ll_preload(uint32_t cache_level, cache_type_t type, uin
map = CACHE_MAP_ALL;
break;
}
Cache_Start_Preload(map, vaddr, size, ascending ? 0 : 1);
Cache_Start_Preload(map, vaddr, size, order);
}
/**
components/hal/esp32p4/include/hal/cache_ll.h
+18 -18
View File
@@ -63,6 +63,7 @@ typedef enum {
CACHE_LL_PRELOAD_ARBITRARY = 2,
} cache_ll_preload_strategy_t;
/**
* @brief Initialize the cache clock
*/
@@ -929,12 +930,11 @@ static inline void cache_ll_unfreeze_cache(uint32_t cache_level, cache_type_t ty
* @param cache_id id of the cache in this type and level (0: Core0, 1: Core1, CACHE_LL_ID_ALL: both)
* @param vaddr start virtual address of the preload region
* @param size size of the preload region in bytes
* @param ascending true: ascending (positive) order; false: descending (negative) order
* @param order preload order
*/
__attribute__((always_inline))
static inline void cache_ll_l1_icache_preload(uint32_t cache_id, uint32_t vaddr, uint32_t size, bool ascending)
static inline void cache_ll_l1_icache_preload(uint32_t cache_id, uint32_t vaddr, uint32_t size, cache_preload_order_t order)
{
uint32_t order = ascending ? 0 : 1;
if (cache_id == 0) {
Cache_Start_L1_CORE0_ICache_Preload(vaddr, size, order);
} else if (cache_id == 1) {
@@ -972,13 +972,13 @@ static inline void cache_ll_l1_icache_preload_wait_done(uint32_t cache_id)
* @param cache_id id of the cache in this type and level (0 or CACHE_LL_ID_ALL)
* @param vaddr start virtual address of the preload region
* @param size size of the preload region in bytes
* @param ascending true: ascending (positive) order; false: descending (negative) order
* @param order preload order
*/
__attribute__((always_inline))
static inline void cache_ll_l1_dcache_preload(uint32_t cache_id, uint32_t vaddr, uint32_t size, bool ascending)
static inline void cache_ll_l1_dcache_preload(uint32_t cache_id, uint32_t vaddr, uint32_t size, cache_preload_order_t order)
{
if (cache_id == 0 || cache_id == CACHE_LL_ID_ALL) {
Cache_Start_L1_DCache_Preload(vaddr, size, ascending ? 0 : 1);
Cache_Start_L1_DCache_Preload(vaddr, size, order);
}
}
@@ -1005,13 +1005,13 @@ static inline void cache_ll_l1_dcache_preload_wait_done(uint32_t cache_id)
* @param cache_id id of the cache in this type and level (0 or CACHE_LL_ID_ALL)
* @param vaddr start virtual address of the preload region
* @param size size of the preload region in bytes
* @param ascending true: ascending (positive) order; false: descending (negative) order
* @param order preload order
*/
__attribute__((always_inline))
static inline void cache_ll_l2_preload(uint32_t cache_id, uint32_t vaddr, uint32_t size, bool ascending)
static inline void cache_ll_l2_preload(uint32_t cache_id, uint32_t vaddr, uint32_t size, cache_preload_order_t order)
{
if (cache_id == 0 || cache_id == CACHE_LL_ID_ALL) {
Cache_Start_L2_Cache_Preload(vaddr, size, ascending ? 0 : 1);
Cache_Start_L2_Cache_Preload(vaddr, size, order);
}
}
@@ -1066,36 +1066,36 @@ static inline void cache_ll_preload_set_strategy(uint32_t cache_level, cache_typ
}
/**
* @brief Preload cache
* @brief Preload cache (L1 and/or L2)
*
* Starts preload for the given level/type and does not wait. Use
* cache_ll_preload_wait_done() to wait for completion.
*
* @param cache_level level of the cache (1: L1, 2: L2)
* @param cache_level level of the cache (1: L1, 2: L2, or CACHE_LL_LEVEL_ALL)
* @param type see `cache_type_t` (INSTRUCTION, DATA, or ALL)
* @param cache_id id of the cache in this type and level (0, 1, or CACHE_LL_ID_ALL)
* @param vaddr start virtual address of the preload region
* @param size size of the preload region in bytes
* @param ascending true: ascending (positive) order; false: descending (negative) order
* @param order preload order, see `cache_preload_order_t`
*/
__attribute__((always_inline))
static inline void cache_ll_preload(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size, bool ascending)
static inline void cache_ll_preload(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size, cache_preload_order_t order)
{
if (cache_level == 2 || cache_level == CACHE_LL_LEVEL_ALL) {
cache_ll_l2_preload(cache_id, vaddr, size, ascending);
cache_ll_l2_preload(cache_id, vaddr, size, order);
}
if (cache_level == 1 || cache_level == CACHE_LL_LEVEL_ALL) {
switch (type) {
case CACHE_TYPE_INSTRUCTION:
cache_ll_l1_icache_preload(cache_id, vaddr, size, ascending);
cache_ll_l1_icache_preload(cache_id, vaddr, size, order);
break;
case CACHE_TYPE_DATA:
cache_ll_l1_dcache_preload(cache_id, vaddr, size, ascending);
cache_ll_l1_dcache_preload(cache_id, vaddr, size, order);
break;
case CACHE_TYPE_ALL:
default:
cache_ll_l1_icache_preload(cache_id, vaddr, size, ascending);
cache_ll_l1_dcache_preload(cache_id, vaddr, size, ascending);
cache_ll_l1_icache_preload(cache_id, vaddr, size, order);
cache_ll_l1_dcache_preload(cache_id, vaddr, size, order);
break;
}
}
components/hal/esp32s2/include/hal/cache_ll.h
+13 -8
View File
@@ -40,6 +40,7 @@ typedef enum {
CACHE_LL_PRELOAD_ARBITRARY = 2,
} cache_ll_preload_strategy_t;
/**
* @brief Initialize the cache clock
*/
@@ -121,27 +122,31 @@ static inline void cache_ll_preload_set_strategy(uint32_t cache_level, cache_typ
}
/**
* @brief Preload cache (L1 only)
* @brief Preload cache
*
* Starts preload for the given region and does not wait. Use
* cache_ll_preload_wait_done() to wait for completion.
* @param cache_level level of the cache (must be CACHE_LL_LEVEL_EXT_MEM)
* @param type see `cache_type_t` (INSTRUCTION, DATA, or ALL)
* @param cache_id id of the cache (unused on S2; pass 0 or CACHE_LL_ID_ALL)
* @param vaddr start virtual address of the preload region
* @param size size of the preload region in bytes
* @param order preload order, see `cache_preload_order_t`
*/
__attribute__((always_inline))
static inline void cache_ll_preload(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size, bool ascending)
static inline void cache_ll_preload(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size, cache_preload_order_t order)
{
(void)cache_id;
HAL_ASSERT(cache_level == CACHE_LL_LEVEL_EXT_MEM);
switch (type) {
case CACHE_TYPE_INSTRUCTION:
Cache_Start_ICache_Preload(vaddr, size, ascending ? 0 : 1);
Cache_Start_ICache_Preload(vaddr, size, order);
break;
case CACHE_TYPE_DATA:
Cache_Start_DCache_Preload(vaddr, size, ascending ? 0 : 1);
Cache_Start_DCache_Preload(vaddr, size, order);
break;
case CACHE_TYPE_ALL:
default:
Cache_Start_ICache_Preload(vaddr, size, ascending ? 0 : 1);
Cache_Start_DCache_Preload(vaddr, size, ascending ? 0 : 1);
Cache_Start_ICache_Preload(vaddr, size, order);
Cache_Start_DCache_Preload(vaddr, size, order);
break;
}
}
components/hal/esp32s3/include/hal/cache_ll.h
+13 -12
View File
@@ -55,6 +55,7 @@ typedef enum {
CACHE_LL_PRELOAD_ARBITRARY = 2,
} cache_ll_preload_strategy_t;
/**
* @brief Initialize the cache clock
*/
@@ -158,13 +159,13 @@ static inline bool cache_ll_l1_is_dcache_preload_busy(uint32_t cache_id)
* @param cache_id id of the cache (0 or CACHE_LL_ID_ALL on S3)
* @param vaddr start virtual address for preload
* @param size_bytes size of region in bytes
* @param ascending true: ascending (order 0); false: descending (order 1)
* @param order preload order
*/
__attribute__((always_inline))
static inline void cache_ll_l1_icache_preload(uint32_t cache_id, uint32_t vaddr, uint32_t size_bytes, bool ascending)
static inline void cache_ll_l1_icache_preload(uint32_t cache_id, uint32_t vaddr, uint32_t size_bytes, cache_preload_order_t order)
{
(void)cache_id;
Cache_Start_ICache_Preload(vaddr, size_bytes, ascending ? 0 : 1);
Cache_Start_ICache_Preload(vaddr, size_bytes, order);
}
/**
@@ -173,13 +174,13 @@ static inline void cache_ll_l1_icache_preload(uint32_t cache_id, uint32_t vaddr,
* @param cache_id id of the cache (0 or CACHE_LL_ID_ALL on S3)
* @param vaddr start virtual address for preload
* @param size_bytes size of region in bytes
* @param ascending true: ascending (order 0); false: descending (order 1)
* @param order preload order
*/
__attribute__((always_inline))
static inline void cache_ll_l1_dcache_preload(uint32_t cache_id, uint32_t vaddr, uint32_t size_bytes, bool ascending)
static inline void cache_ll_l1_dcache_preload(uint32_t cache_id, uint32_t vaddr, uint32_t size_bytes, cache_preload_order_t order)
{
(void)cache_id;
Cache_Start_DCache_Preload(vaddr, size_bytes, ascending ? 0 : 1);
Cache_Start_DCache_Preload(vaddr, size_bytes, order);
}
/**
@@ -231,23 +232,23 @@ static inline void cache_ll_preload_set_strategy(uint32_t cache_level, cache_typ
* @param cache_id id of the cache (0 or CACHE_LL_ID_ALL)
* @param vaddr start virtual address for preload
* @param size size of region in bytes
* @param ascending true: ascending order; false: descending
* @param order preload order, see `cache_preload_order_t`
*/
__attribute__((always_inline))
static inline void cache_ll_preload(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size, bool ascending)
static inline void cache_ll_preload(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size, cache_preload_order_t order)
{
HAL_ASSERT(cache_level == 1);
switch (type) {
case CACHE_TYPE_INSTRUCTION:
cache_ll_l1_icache_preload(cache_id, vaddr, size, ascending);
cache_ll_l1_icache_preload(cache_id, vaddr, size, order);
break;
case CACHE_TYPE_DATA:
cache_ll_l1_dcache_preload(cache_id, vaddr, size, ascending);
cache_ll_l1_dcache_preload(cache_id, vaddr, size, order);
break;
case CACHE_TYPE_ALL:
default:
cache_ll_l1_icache_preload(cache_id, vaddr, size, ascending);
cache_ll_l1_dcache_preload(cache_id, vaddr, size, ascending);
cache_ll_l1_icache_preload(cache_id, vaddr, size, order);
cache_ll_l1_dcache_preload(cache_id, vaddr, size, order);
break;
}
}
components/hal/esp32s31/include/hal/cache_ll.h
+22 -11
View File
@@ -50,6 +50,7 @@ typedef enum {
CACHE_LL_PRELOAD_ARBITRARY = 2,
} cache_ll_preload_strategy_t;
/**
* @brief Initialize the cache clock
*/
@@ -671,12 +672,11 @@ static inline void cache_ll_unfreeze_cache(uint32_t cache_level, cache_type_t ty
* @param cache_id id of the cache in this type and level (0: Core0, 1: Core1, CACHE_LL_ID_ALL: both)
* @param vaddr start virtual address of the preload region
* @param size size of the preload region in bytes
* @param ascending true: ascending (positive) order; false: descending (negative) order
* @param order preload order
*/
__attribute__((always_inline))
static inline void cache_ll_l1_icache_preload(uint32_t cache_id, uint32_t vaddr, uint32_t size, bool ascending)
static inline void cache_ll_l1_icache_preload(uint32_t cache_id, uint32_t vaddr, uint32_t size, cache_preload_order_t order)
{
uint32_t order = ascending ? 0 : 1;
if (cache_id == 0) {
Cache_Start_L1_CORE0_ICache_Preload(vaddr, size, order);
} else if (cache_id == 1) {
@@ -714,13 +714,13 @@ static inline void cache_ll_l1_icache_preload_wait_done(uint32_t cache_id)
* @param cache_id id of the cache in this type and level (0 or CACHE_LL_ID_ALL)
* @param vaddr start virtual address of the preload region
* @param size size of the preload region in bytes
* @param ascending true: ascending (positive) order; false: descending (negative) order
* @param order preload order
*/
__attribute__((always_inline))
static inline void cache_ll_l1_dcache_preload(uint32_t cache_id, uint32_t vaddr, uint32_t size, bool ascending)
static inline void cache_ll_l1_dcache_preload(uint32_t cache_id, uint32_t vaddr, uint32_t size, cache_preload_order_t order)
{
if (cache_id == 0 || cache_id == CACHE_LL_ID_ALL) {
Cache_Start_L1_DCache_Preload(vaddr, size, ascending ? 0 : 1);
Cache_Start_L1_DCache_Preload(vaddr, size, order);
}
}
@@ -763,22 +763,29 @@ static inline void cache_ll_preload_set_strategy(uint32_t cache_level, cache_typ
/**
* @brief Preload cache
*
* @param cache_level level of the cache
* @param type see `cache_type_t`
* @param cache_id id of the cache in this type and level
* @param vaddr start virtual address for preload
* @param size size of region in bytes
* @param order preload order
*/
__attribute__((always_inline))
static inline void cache_ll_preload(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size, bool ascending)
static inline void cache_ll_preload(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size, cache_preload_order_t order)
{
if (cache_level == 1 || cache_level == CACHE_LL_LEVEL_ALL) {
switch (type) {
case CACHE_TYPE_INSTRUCTION:
cache_ll_l1_icache_preload(cache_id, vaddr, size, ascending);
cache_ll_l1_icache_preload(cache_id, vaddr, size, order);
break;
case CACHE_TYPE_DATA:
cache_ll_l1_dcache_preload(cache_id, vaddr, size, ascending);
cache_ll_l1_dcache_preload(cache_id, vaddr, size, order);
break;
case CACHE_TYPE_ALL:
default:
cache_ll_l1_icache_preload(cache_id, vaddr, size, ascending);
cache_ll_l1_dcache_preload(cache_id, vaddr, size, ascending);
cache_ll_l1_icache_preload(cache_id, vaddr, size, order);
cache_ll_l1_dcache_preload(cache_id, vaddr, size, order);
break;
}
}
@@ -786,6 +793,10 @@ static inline void cache_ll_preload(uint32_t cache_level, cache_type_t type, uin
/**
* @brief Wait until cache preload is done
*
* @param cache_level level of the cache
* @param type see `cache_type_t`
* @param cache_id id of the cache in this type and level
*/
__attribute__((always_inline))
static inline void cache_ll_preload_wait_done(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
components/hal/include/hal/cache_hal.h
+2 -2
View File
@@ -156,9 +156,9 @@ uint32_t cache_hal_get_cache_line_size(uint32_t cache_level, cache_type_t type);
* @param vaddr Start virtual address of the region to preload
* @param size Size in bytes. Should be cache-line aligned; if not,
* the actual preloaded length is rounded down to cache-line boundary.
* @param ascending true for ascending order, false for descending
* @param order preload order
*/
void cache_hal_preload(uint32_t cache_level, cache_type_t type, uint32_t vaddr, uint32_t size, bool ascending);
void cache_hal_preload(uint32_t cache_level, cache_type_t type, uint32_t vaddr, uint32_t size, cache_preload_order_t order);
/**
* @brief Wait until cache preload started by cache_hal_preload() is done
components/hal/include/hal/cache_types.h
+9 -1
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2010-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -34,6 +34,14 @@ typedef enum {
CACHE_BUS_DBUS2 = BIT(5),
} cache_bus_mask_t;
/**
* @brief Preload order
*/
typedef enum {
CACHE_PRELOAD_ORDER_ASCENDING,
CACHE_PRELOAD_ORDER_DESCENDING,
} cache_preload_order_t;
#ifdef __cplusplus
}
#endif