feat(esp_hal_pmu): move pau_hal driver into esp_hal_pmu component

components/esp_hal_pmu/CMakeLists.txt

@@ -16,6 +16,11 @@ if(EXISTS "${CMAKE_CURRENT_LIST_DIR}/${target}/rtc_cntl_hal.c")
     list(APPEND srcs "${target}/rtc_cntl_hal.c")
 endif()
 
+# Chips with PAU (Power Assist Unit) peripheral
+if(CONFIG_SOC_PAU_SUPPORTED)
+    list(APPEND srcs "${target}/pau_hal.c")
+endif()
+
 idf_component_register(SRCS ${srcs}
                        INCLUDE_DIRS ${public_include}
                        REQUIRES soc hal esp_rom

components/esp_hal_pmu/README.md

@@ -7,21 +7,23 @@
 
 The `esp_hal_pmu` component provides a **Hardware Abstraction Layer** for Power Management Unit (PMU) and legacy RTC Control (RTC_CNTL) peripherals across ESP-IDF supported targets. This HAL enables unified power management operations including sleep mode control, power domain management, wakeup configuration, and retention control across different ESP chip families.
 
-The component consolidates power management functionality from two different peripheral implementations:
+The component consolidates power management functionality from three different peripheral implementations:
 - **PMU**: Modern power management unit in newer ESP chips
 - **RTC_CNTL**: Legacy RTC control peripheral in older ESP chips
+- **PAU**: Power Assist Unit for register retention and backup/restore operations
 
 ## Architecture
 
 The HAL architecture consists of two primary layers:
 
-1. **HAL Layer (Upper)**: Defines the operational sequences and data structures required to interact with PMU/RTC_CNTL peripherals, including:
+1. **HAL Layer (Upper)**: Defines the operational sequences and data structures required to interact with PMU/RTC_CNTL/PAU peripherals, including:
    - Power domain configuration and control
    - Sleep mode management
    - Wakeup source configuration
    - Retention control (CPU, tagmem)
    - Power-up/down wait cycle configuration
    - Backup enable/disable operations
+   - REGDMA link configuration and control
 
 2. **Low-Level Layer (Bottom)**: Acts as a translation layer between the HAL and the register definitions in the `soc` component, handling:
    - Register access abstractions
@@ -53,10 +55,18 @@ The HAL architecture consists of two primary layers:
 - Sleep-to-modem backup enable/disable
 - Modem-to-active backup enable/disable
 
+### REGDMA (Register DMA) Support
+- REGDMA entry link address configuration
+- REGDMA modem link control (backup/restore)
+- REGDMA system link control
+- REGDMA extra link control
+- REGDMA timeout configuration
+- REGDMA clock configuration
+
 ## Usage
 This component is primarily used by ESP-IDF system services such as:
 - **esp_pm**: Power management framework
-- **esp_hw_support**: Hardware support layer for sleep modes and power management
+- **esp_hw_support**: Hardware support layer for sleep modes, power management, and register retention
 - **ulp**: Ultra-low-power coprocessor support
 
 For advanced developers implementing custom power management solutions, the HAL functions can be used directly. However, please note that the interfaces provided by this component are internal to ESP-IDF and are subject to change.

components/esp_hal_pmu/esp32c5/include/hal/pau_ll.h

@@ -104,7 +104,6 @@ static inline void pau_ll_clear_regdma_backup_error_intr_state(pau_dev_t *dev)
     dev->int_clr.val = 0x2;
 }
 
-
 /**
  * @brief Set the maximum number of linked lists supported by REGDMA
  * @param count: the maximum number of regdma link

components/esp_hal_pmu/include/hal/pau_hal.h

@@ -17,7 +17,6 @@ extern "C" {
 #include "hal/pau_ll.h"
 #include "hal/pau_types.h"
 
-
 typedef struct {
     pau_dev_t *dev;
 } pau_hal_context_t;

components/hal/CMakeLists.txt

@@ -124,10 +124,6 @@ elseif(NOT BOOTLOADER_BUILD)
         list(APPEND srcs "${target}/modem_clock_hal.c")
     endif()
 
-    if(CONFIG_SOC_PAU_SUPPORTED)
-        list(APPEND srcs "${target}/pau_hal.c")
-    endif()
-
     if(CONFIG_SOC_BOD_SUPPORTED)
         list(APPEND srcs "brownout_hal.c")
     endif()