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feat(soc): support esp32s31 lp_aon & rtc_wdt & rtc_timer

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wuzhenghui
2026-01-28 17:03:36 +08:00
parent 0249f682dc
commit 0b27301a09
48 changed files with 790 additions and 543 deletions
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components/bootloader_support/src/bootloader_clock_init.c
+12 -10
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2017-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -9,14 +9,7 @@
#include "soc/chip_revision.h"
#include "hal/efuse_hal.h"
#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 // TODO: IDF-5645
#include "soc/rtc_cntl_reg.h"
#else
#include "soc/lp_wdt_reg.h"
#include "soc/lp_timer_reg.h"
#include "soc/lp_analog_peri_reg.h"
#include "soc/pmu_reg.h"
#endif
#include "soc/rtc_cntl_periph.h"
#if CONFIG_IDF_TARGET_ESP32
#include "hal/clk_tree_ll.h"
@@ -163,7 +156,16 @@ __attribute__((weak)) void bootloader_clock_configure(void)
SET_PERI_REG_MASK(LP_ANALOG_PERI_LP_INT_CLR_REG, LP_ANALOG_PERI_LP_INT_CLR_REG); /* BROWN_OUT */
SET_PERI_REG_MASK(LP_WDT_INT_CLR_REG, LP_WDT_LP_WDT_INT_CLR); /* WDT */
#elif CONFIG_IDF_TARGET_ESP32S31
//ESP32S31-TODO IDF-14696
// CLR ENA
CLEAR_PERI_REG_MASK(RTC_WDT_INT_ENA_REG, RTC_WDT_SUPER_WDT_INT_ENA); /* SWD */
CLEAR_PERI_REG_MASK(LP_ANA_LP_INT_ENA_REG, LP_ANA_BOD_MODE0_LP_INT_ENA); /* BROWN_OUT */
CLEAR_PERI_REG_MASK(RTC_WDT_INT_ENA_REG, RTC_WDT_LP_WDT_INT_ENA); /* WDT */
CLEAR_PERI_REG_MASK(PMU_HP_INT_ENA_REG, PMU_SOC_WAKEUP_INT_ENA); /* SLP_REJECT */
CLEAR_PERI_REG_MASK(PMU_HP_INT_ENA_REG, PMU_SOC_SLEEP_REJECT_INT_ENA); /* SLP_WAKEUP */
// SET CLR
SET_PERI_REG_MASK(RTC_WDT_INT_CLR_REG, RTC_WDT_SUPER_WDT_INT_CLR); /* SWD */
SET_PERI_REG_MASK(LP_ANA_LP_INT_CLR_REG, LP_ANA_BOD_MODE0_LP_INT_ENA); /* BROWN_OUT */
SET_PERI_REG_MASK(RTC_WDT_INT_CLR_REG, RTC_WDT_LP_WDT_INT_CLR); /* WDT */
#else
REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);
components/bootloader_support/src/bootloader_random.c
+1 -1
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@@ -45,7 +45,7 @@
assert(buffer != NULL);
for (size_t i = 0; i < length; i++) {
#if SOC_RTC_TIMER_V2_SUPPORTED
#if !SOC_RTC_TIMER_V1
random = REG_READ(WDEV_RND_REG);
start = esp_cpu_get_cycle_count();
do {
components/esp_hal_rtc_timer/README.md
+3 -2
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@@ -8,8 +8,9 @@
The `esp_hal_rtc_timer` component provides a **unified Hardware Abstraction Layer** for RTC Timer peripherals across all ESP-IDF supported targets. This HAL abstracts hardware differences between legacy RTC timer implementations (in RTC_CNTL peripheral) and modern low-power timer implementations, providing a consistent API for wakeup timer configuration and RTC time reading across different ESP chip families.
The component consolidates timer functionality from two different hardware implementations:
- **SOC_RTC_TIMER_V1_SUPPORTED**: Legacy RTC timer functionality in RTC_CNTL peripheral (ESP32, ESP32C2, ESP32C3, ESP32S2, ESP32S3)
- **SOC_RTC_TIMER_V2_SUPPORTED**: Newer LP timer peripheral (ESP32C5, ESP32C6, ESP32C61, ESP32H2, ESP32H21, ESP32H4, ESP32P4)
- **SOC_RTC_TIMER_V1**: Legacy RTC timer functionality in RTC_CNTL peripheral for ESP32, ESP32C2, ESP32C3, ESP32S2, ESP32S3
- **SOC_RTC_TIMER_V2**: LP timer peripheral for ESP32C5, ESP32C6, ESP32C61, ESP32H2, ESP32H21, ESP32H4, ESP32P4
- **SOC_RTC_TIMER_V3**: RTC timer peripheral for ESP32S31
### Unified HAL API (All Chips)
- Wakeup timer configuration via `rtc_timer_hal_set_wakeup_time()`
components/esp_hal_rtc_timer/esp32s31/include/hal/rtc_timer_ll.h
+104 -6
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@@ -1,19 +1,18 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The LL layer for ESP32-P4 RTC_Timer register operations
// The LL layer for ESP32S31 RTC_Timer register operations
#pragma once
#include <stdlib.h>
#include <stdbool.h>
#include "soc/soc.h"
#include "soc/lp_timer_struct.h"
#include "soc/lp_timer_reg.h"
#include "soc/lp_system_reg.h"
#include "soc/rtc_timer_struct.h"
#include "soc/rtc_timer_reg.h"
#include "hal/misc.h"
#include "esp_attr.h"
@@ -21,7 +20,106 @@
extern "C" {
#endif
// TODO: ["ESP32S31"] IDF-14642
FORCE_INLINE_ATTR void rtc_timer_ll_set_alarm_target(rtc_timer_dev_t *dev, uint8_t timer_id, uint64_t value)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->target[timer_id].hi, target_hi, (value >> 32) & 0xFFFF);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->target[timer_id].lo, target_lo, value & 0xFFFFFFFF);
}
FORCE_INLINE_ATTR void rtc_timer_ll_set_target_enable(rtc_timer_dev_t *dev, uint8_t timer_id, bool en)
{
dev->target[timer_id].hi.enable = en;
}
FORCE_INLINE_ATTR uint32_t rtc_timer_ll_get_counter_value_low(rtc_timer_dev_t *dev, uint8_t timer_id)
{
return HAL_FORCE_READ_U32_REG_FIELD(dev->counter[timer_id].lo, counter_lo);
}
FORCE_INLINE_ATTR uint32_t rtc_timer_ll_get_counter_value_high(rtc_timer_dev_t *dev, uint8_t timer_id)
{
return HAL_FORCE_READ_U32_REG_FIELD(dev->counter[timer_id].hi, counter_hi);
}
FORCE_INLINE_ATTR void rtc_timer_ll_counter_snapshot(rtc_timer_dev_t *dev)
{
dev->update.main_timer_update = 1;
}
/**
* @brief Clear alarm interrupt status
*
* @param dev LP timer peripheral instance
* @param timer_id Timer ID (0 for main timer, 1 for LP timer)
*/
FORCE_INLINE_ATTR void rtc_timer_ll_clear_alarm_intr_status(rtc_timer_dev_t *dev, uint8_t timer_id)
{
if (timer_id == 0) {
dev->int_clr.soc_wakeup_int_clr = 1;
} else if (timer_id == 1) {
dev->lp_int_clr.main_timer_lp_int_clr = 1;
}
}
/**
* @brief Get interrupt raw status
*
* @param dev LP timer peripheral instance
* @param timer_id Timer ID (0 for main timer, 1 for LP timer)
* @return Interrupt raw status value
*/
FORCE_INLINE_ATTR uint32_t rtc_timer_ll_get_intr_raw(rtc_timer_dev_t *dev, uint8_t timer_id)
{
if (timer_id == 0) {
return dev->int_raw.val;
} else if (timer_id == 1) {
return dev->lp_int_raw.val;
}
return 0;
}
/**
* @brief Enable/disable alarm interrupt
*
* @param dev LP timer peripheral instance
* @param timer_id Timer ID (0 for main timer, 1 for LP timer)
* @param enable Enable or disable interrupt
*/
FORCE_INLINE_ATTR void rtc_timer_ll_alarm_intr_enable(rtc_timer_dev_t *dev, uint8_t timer_id, bool enable)
{
if (timer_id == 0) {
dev->int_ena.soc_wakeup_int_ena = enable;
} else if (timer_id == 1) {
dev->lp_int_ena.main_timer_lp_int_ena = enable;
}
}
/**
* @brief Set wakeup timer value
*
* @param timer_id Timer ID
* @param ticks Timer value in RTC slow clock ticks
*/
FORCE_INLINE_ATTR void rtc_timer_ll_set_wakeup_time(uint8_t timer_id, uint64_t ticks)
{
rtc_timer_ll_clear_alarm_intr_status(&RTC_TIMER, timer_id);
rtc_timer_ll_set_alarm_target(&RTC_TIMER, timer_id, ticks);
rtc_timer_ll_set_target_enable(&RTC_TIMER, timer_id, true);
}
/**
* @brief Get current RTC timer cycle count
*
* @param timer_id Timer ID
* @return Current RTC time in RTC slow clock ticks
*/
FORCE_INLINE_ATTR uint64_t rtc_timer_ll_get_cycle_count(uint8_t timer_id)
{
rtc_timer_ll_counter_snapshot(&RTC_TIMER);
uint32_t lo = rtc_timer_ll_get_counter_value_low(&RTC_TIMER, timer_id);
uint32_t hi = rtc_timer_ll_get_counter_value_high(&RTC_TIMER, timer_id);
return ((uint64_t)hi << 32) | lo;
}
#ifdef __cplusplus
}
components/esp_hal_wdt/esp32s31/include/hal/lpwdt_ll.h
-327
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@@ -1,327 +0,0 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <stdlib.h>
#include <stdbool.h>
#include "hal/misc.h"
#include "hal/wdt_types.h"
#include "soc/rtc_cntl_periph.h"
#include "soc/efuse_reg.h"
#include "esp_attr.h"
#include "esp_assert.h"
#include "esp32s31/rom/ets_sys.h"
// TODO: ["ESP32S31"] IDF-14636
/* The value that needs to be written to LP_WDT_WPROTECT_REG to write-enable the wdt registers */
#define LP_WDT_WKEY_VALUE 0x50D83AA1
/* The value that needs to be written to LP_WDT_SWD_WPROTECT_REG to write-enable the swd registers */
#define LP_WDT_SWD_WKEY_VALUE 0x50D83AA1
/* Possible values for RTC_CNTL_WDT_CPU_RESET_LENGTH and RTC_CNTL_WDT_SYS_RESET_LENGTH */
#define LP_WDT_RESET_LENGTH_100_NS 0
#define LP_WDT_RESET_LENGTH_200_NS 1
#define LP_WDT_RESET_LENGTH_300_NS 2
#define LP_WDT_RESET_LENGTH_400_NS 3
#define LP_WDT_RESET_LENGTH_500_NS 4
#define LP_WDT_RESET_LENGTH_800_NS 5
#define LP_WDT_RESET_LENGTH_1600_NS 6
#define LP_WDT_RESET_LENGTH_3200_NS 7
#define LP_WDT_STG_SEL_OFF 0
#define LP_WDT_STG_SEL_INT 1
#define LP_WDT_STG_SEL_RESET_CPU 2
#define LP_WDT_STG_SEL_RESET_SYSTEM 3
#define LP_WDT_STG_SEL_RESET_RTC 4
//Type check wdt_stage_action_t
ESP_STATIC_ASSERT(WDT_STAGE_ACTION_OFF == LP_WDT_STG_SEL_OFF, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
ESP_STATIC_ASSERT(WDT_STAGE_ACTION_INT == LP_WDT_STG_SEL_INT, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
ESP_STATIC_ASSERT(WDT_STAGE_ACTION_RESET_CPU == LP_WDT_STG_SEL_RESET_CPU, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
ESP_STATIC_ASSERT(WDT_STAGE_ACTION_RESET_SYSTEM == LP_WDT_STG_SEL_RESET_SYSTEM, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
ESP_STATIC_ASSERT(WDT_STAGE_ACTION_RESET_RTC == LP_WDT_STG_SEL_RESET_RTC, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
//Type check wdt_reset_sig_length_t
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_100ns == LP_WDT_RESET_LENGTH_100_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_200ns == LP_WDT_RESET_LENGTH_200_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_300ns == LP_WDT_RESET_LENGTH_300_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_400ns == LP_WDT_RESET_LENGTH_400_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_500ns == LP_WDT_RESET_LENGTH_500_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_800ns == LP_WDT_RESET_LENGTH_800_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_1_6us == LP_WDT_RESET_LENGTH_1600_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_3_2us == LP_WDT_RESET_LENGTH_3200_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
/**
* @brief Enable the RWDT
*
* @param hw Start address of the peripheral registers.
*/
FORCE_INLINE_ATTR void lpwdt_ll_enable(lp_wdt_dev_t *hw)
{
hw->config0.wdt_en = 1;
}
/**
* @brief Disable the RWDT
*
* @param hw Start address of the peripheral registers.
* @note This function does not disable the flashboot mode. Therefore, given that
* the MWDT is disabled using this function, a timeout can still occur
* if the flashboot mode is simultaneously enabled.
*/
FORCE_INLINE_ATTR void lpwdt_ll_disable(lp_wdt_dev_t *hw)
{
hw->config0.wdt_en = 0;
}
/**
* @brief Check if the RWDT is enabled
*
* @param hw Start address of the peripheral registers.
* @return True if RTC WDT is enabled
*/
FORCE_INLINE_ATTR bool lpwdt_ll_check_if_enabled(lp_wdt_dev_t *hw)
{
return (hw->config0.wdt_en) ? true : false;
}
/**
* @brief Configure a particular stage of the RWDT
*
* @param hw Start address of the peripheral registers.
* @param stage Which stage to configure
* @param timeout Number of timer ticks for the stage to timeout (see note).
* @param behavior What action to take when the stage times out
*
* @note The value of of RWDT stage 0 timeout register is special, in
* that an implicit multiplier is applied to that value to produce
* and effective timeout tick value. The multiplier is dependent
* on an EFuse value. Therefore, when configuring stage 0, the valid
* values for the timeout argument are:
* - If Efuse value is 0, any even number between [2,2*UINT32_MAX]
* - If Efuse value is 1, any multiple of 4 between [4,4*UINT32_MAX]
* - If Efuse value is 2, any multiple of 8 between [8,8*UINT32_MAX]
* - If Efuse value is 3, any multiple of 16 between [16,16*UINT32_MAX]
*/
FORCE_INLINE_ATTR void lpwdt_ll_config_stage(lp_wdt_dev_t *hw, wdt_stage_t stage, uint32_t timeout_ticks, wdt_stage_action_t behavior)
{
switch (stage) {
case WDT_STAGE0:
hw->config0.wdt_stg0 = behavior;
//Account of implicty multiplier applied to stage 0 timeout tick config value
hw->config1.val = timeout_ticks >> (1 + REG_GET_FIELD(EFUSE_RD_REPEAT_DATA1_REG, EFUSE_WDT_DELAY_SEL));
break;
case WDT_STAGE1:
hw->config0.wdt_stg1 = behavior;
hw->config2.val = timeout_ticks;
break;
case WDT_STAGE2:
hw->config0.wdt_stg2 = behavior;
hw->config3.val = timeout_ticks;
break;
case WDT_STAGE3:
hw->config0.wdt_stg3 = behavior;
hw->config4.val = timeout_ticks;
break;
default:
abort();
}
}
/**
* @brief Disable a particular stage of the RWDT
*
* @param hw Start address of the peripheral registers.
* @param stage Which stage to disable
*/
FORCE_INLINE_ATTR void lpwdt_ll_disable_stage(lp_wdt_dev_t *hw, wdt_stage_t stage)
{
switch (stage) {
case WDT_STAGE0:
hw->config0.wdt_stg0 = WDT_STAGE_ACTION_OFF;
break;
case WDT_STAGE1:
hw->config0.wdt_stg1 = WDT_STAGE_ACTION_OFF;
break;
case WDT_STAGE2:
hw->config0.wdt_stg2 = WDT_STAGE_ACTION_OFF;
break;
case WDT_STAGE3:
hw->config0.wdt_stg3 = WDT_STAGE_ACTION_OFF;
break;
default:
abort();
}
}
/**
* @brief Set the length of the CPU reset action
*
* @param hw Start address of the peripheral registers.
* @param length Length of CPU reset signal
*/
FORCE_INLINE_ATTR void lpwdt_ll_set_cpu_reset_length(lp_wdt_dev_t *hw, wdt_reset_sig_length_t length)
{
hw->config0.wdt_cpu_reset_length = length;
}
/**
* @brief Set the length of the system reset action
*
* @param hw Start address of the peripheral registers.
* @param length Length of system reset signal
*/
FORCE_INLINE_ATTR void lpwdt_ll_set_sys_reset_length(lp_wdt_dev_t *hw, wdt_reset_sig_length_t length)
{
hw->config0.wdt_sys_reset_length = length;
}
/**
* @brief Enable/Disable the RWDT flashboot mode.
*
* @param hw Start address of the peripheral registers.
* @param enable True to enable RWDT flashboot mode, false to disable RWDT flashboot mode.
*
* @note Flashboot mode is independent and can trigger a WDT timeout event if the
* WDT's enable bit is set to 0. Flashboot mode for RWDT is automatically enabled
* on flashboot, and should be disabled by software when flashbooting completes.
*/
FORCE_INLINE_ATTR void lpwdt_ll_set_flashboot_en(lp_wdt_dev_t *hw, bool enable)
{
hw->config0.wdt_flashboot_mod_en = (enable) ? 1 : 0;
}
/**
* @brief Enable/Disable the CPU0 to be reset on WDT_STAGE_ACTION_RESET_CPU
*
* @param hw Start address of the peripheral registers.
* @param enable True to enable CPU0 to be reset, false to disable.
*/
FORCE_INLINE_ATTR void lpwdt_ll_set_procpu_reset_en(lp_wdt_dev_t *hw, bool enable)
{
hw->config0.wdt_procpu_reset_en = (enable) ? 1 : 0;
}
/**
* @brief Enable/Disable the CPU1 to be reset on WDT_STAGE_ACTION_RESET_CPU
*
* @param hw Start address of the peripheral registers.
* @param enable True to enable CPU1 to be reset, false to disable.
*/
FORCE_INLINE_ATTR void lpwdt_ll_set_appcpu_reset_en(lp_wdt_dev_t *hw, bool enable)
{
hw->config0.wdt_appcpu_reset_en = (enable) ? 1 : 0;
}
/**
* @brief Enable/Disable the RWDT pause during sleep functionality
*
* @param hw Start address of the peripheral registers.
* @param enable True to enable, false to disable.
*/
FORCE_INLINE_ATTR void lpwdt_ll_set_pause_in_sleep_en(lp_wdt_dev_t *hw, bool enable)
{
hw->config0.wdt_pause_in_slp = (enable) ? 1 : 0;
}
/**
* @brief Enable/Disable chip reset on RWDT timeout.
*
* A chip reset also resets the analog portion of the chip. It will appear as a
* POWERON reset rather than an RTC reset.
*
* @param hw Start address of the peripheral registers.
* @param enable True to enable, false to disable.
*/
FORCE_INLINE_ATTR void lpwdt_ll_set_chip_reset_en(lp_wdt_dev_t *hw, bool enable)
{
// hw->config0.wdt_chip_reset_en = (enable) ? 1 : 0;
}
/**
* @brief Set width of chip reset signal
*
* @param hw Start address of the peripheral registers.
* @param width Width of chip reset signal in terms of number of RTC_SLOW_CLK cycles
*/
FORCE_INLINE_ATTR void lpwdt_ll_set_chip_reset_width(lp_wdt_dev_t *hw, uint32_t width)
{
// HAL_FORCE_MODIFY_U32_REG_FIELD(hw->config0, wdt_chip_reset_width, width);
}
/**
* @brief Feed the RWDT
*
* Resets the current timer count and current stage.
*
* @param hw Start address of the peripheral registers.
*/
FORCE_INLINE_ATTR void lpwdt_ll_feed(lp_wdt_dev_t *hw)
{
// hw->feed.rtc_wdt_feed = 1;
}
/**
* @brief Enable write protection of the RWDT registers
*
* @param hw Start address of the peripheral registers.
*/
FORCE_INLINE_ATTR void lpwdt_ll_write_protect_enable(lp_wdt_dev_t *hw)
{
hw->wprotect.val = 0;
}
/**
* @brief Disable write protection of the RWDT registers
*
* @param hw Start address of the peripheral registers.
*/
FORCE_INLINE_ATTR void lpwdt_ll_write_protect_disable(lp_wdt_dev_t *hw)
{
hw->wprotect.val = LP_WDT_WKEY_VALUE;
}
/**
* @brief Enable the RWDT interrupt.
*
* @param hw Start address of the peripheral registers.
* @param enable True to enable RWDT interrupt, false to disable.
*/
FORCE_INLINE_ATTR void lpwdt_ll_set_intr_enable(lp_wdt_dev_t *hw, bool enable)
{
hw->int_ena.lp_wdt_int_ena = (enable) ? 1 : 0;
}
/**
* @brief Check if the RWDT interrupt has been triggered
*
* @param hw Start address of the peripheral registers.
* @return True if the RWDT interrupt was triggered
*/
FORCE_INLINE_ATTR bool lpwdt_ll_check_intr_status(lp_wdt_dev_t *hw)
{
return (hw->int_st.lp_wdt_int_st) ? true : false;
}
/**
* @brief Clear the RWDT interrupt status.
*
* @param hw Start address of the peripheral registers.
*/
FORCE_INLINE_ATTR void lpwdt_ll_clear_intr_status(lp_wdt_dev_t *hw)
{
hw->int_clr.lp_wdt_int_clr = 1;
}
#ifdef __cplusplus
}
#endif
components/esp_hal_wdt/esp32s31/include/hal/rwdt_ll.h
+294 -45
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@@ -1,10 +1,8 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The LL layer for RTC(LP) watchdog register operations.
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
@@ -12,70 +10,321 @@
extern "C" {
#endif
#include "hal/lpwdt_ll.h"
#include <stdlib.h>
#include <stdbool.h>
#include "hal/misc.h"
#include "hal/wdt_types.h"
#include "soc/rtc_cntl_periph.h"
#include "soc/efuse_reg.h"
#include "esp_attr.h"
#include "esp_assert.h"
// TODO: ["ESP32S31"] IDF-14656
#include "esp32s31/rom/ets_sys.h"
typedef lp_wdt_dev_t rwdt_dev_t;
// TODO: ["ESP32S31"] IDF-14636
#define RWDT_DEV_GET() &LP_WDT
/* The value that needs to be written to RTC_WDT_WPROTECT_REG to write-enable the wdt registers */
#define RTC_WDT_WKEY_VALUE 0x50D83AA1
/* The value that needs to be written to RTC_WDT_SWD_WPROTECT_REG to write-enable the swd registers */
#define RTC_WDT_SWD_WKEY_VALUE 0x50D83AA1
#define rwdt_ll_enable(hw) \
lpwdt_ll_enable(hw)
/* Possible values for RTC_CNTL_WDT_CPU_RESET_LENGTH and RTC_CNTL_WDT_SYS_RESET_LENGTH */
#define RTC_WDT_RESET_LENGTH_100_NS 0
#define RTC_WDT_RESET_LENGTH_200_NS 1
#define RTC_WDT_RESET_LENGTH_300_NS 2
#define RTC_WDT_RESET_LENGTH_400_NS 3
#define RTC_WDT_RESET_LENGTH_500_NS 4
#define RTC_WDT_RESET_LENGTH_800_NS 5
#define RTC_WDT_RESET_LENGTH_1600_NS 6
#define RTC_WDT_RESET_LENGTH_3200_NS 7
#define rwdt_ll_disable(hw) \
lpwdt_ll_disable(hw)
#define RTC_WDT_STG_SEL_OFF 0
#define RTC_WDT_STG_SEL_INT 1
#define RTC_WDT_STG_SEL_RESET_CPU 2
#define RTC_WDT_STG_SEL_RESET_SYSTEM 3
#define RTC_WDT_STG_SEL_RESET_RTC 4
#define rwdt_ll_check_if_enabled(hw) \
lpwdt_ll_check_if_enabled(hw)
//Type check wdt_stage_action_t
ESP_STATIC_ASSERT(WDT_STAGE_ACTION_OFF == RTC_WDT_STG_SEL_OFF, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
ESP_STATIC_ASSERT(WDT_STAGE_ACTION_INT == RTC_WDT_STG_SEL_INT, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
ESP_STATIC_ASSERT(WDT_STAGE_ACTION_RESET_CPU == RTC_WDT_STG_SEL_RESET_CPU, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
ESP_STATIC_ASSERT(WDT_STAGE_ACTION_RESET_SYSTEM == RTC_WDT_STG_SEL_RESET_SYSTEM, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
ESP_STATIC_ASSERT(WDT_STAGE_ACTION_RESET_RTC == RTC_WDT_STG_SEL_RESET_RTC, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
//Type check wdt_reset_sig_length_t
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_100ns == RTC_WDT_RESET_LENGTH_100_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_200ns == RTC_WDT_RESET_LENGTH_200_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_300ns == RTC_WDT_RESET_LENGTH_300_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_400ns == RTC_WDT_RESET_LENGTH_400_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_500ns == RTC_WDT_RESET_LENGTH_500_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_800ns == RTC_WDT_RESET_LENGTH_800_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_1_6us == RTC_WDT_RESET_LENGTH_1600_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_3_2us == RTC_WDT_RESET_LENGTH_3200_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
#define rwdt_ll_config_stage(hw, stage, timeout_ticks, behavior) \
lpwdt_ll_config_stage(hw, stage, timeout_ticks, behavior)
typedef rtc_wdt_dev_t rwdt_dev_t;
#define rwdt_ll_disable_stage(hw, stage) \
lpwdt_ll_disable_stage(hw, stage)
#define RWDT_DEV_GET() &RTC_WDT
#define rwdt_ll_set_cpu_reset_length(hw, length) \
lpwdt_ll_set_cpu_reset_length(hw, length)
/**
* @brief Enable the RWDT
*
* @param hw Start address of the peripheral registers.
*/
FORCE_INLINE_ATTR void rwdt_ll_enable(rwdt_dev_t *hw)
{
hw->config0.wdt_en = 1;
}
#define rwdt_ll_set_sys_reset_length(hw, length) \
lpwdt_ll_set_sys_reset_length(hw, length)
/**
* @brief Disable the RWDT
*
* @param hw Start address of the peripheral registers.
* @note This function does not disable the flashboot mode. Therefore, given that
* the MWDT is disabled using this function, a timeout can still occur
* if the flashboot mode is simultaneously enabled.
*/
FORCE_INLINE_ATTR void rwdt_ll_disable(rwdt_dev_t *hw)
{
hw->config0.wdt_en = 0;
}
#define rwdt_ll_set_flashboot_en(hw, enable) \
lpwdt_ll_set_flashboot_en(hw, enable)
/**
* @brief Check if the RWDT is enabled
*
* @param hw Start address of the peripheral registers.
* @return True if RTC WDT is enabled
*/
FORCE_INLINE_ATTR bool rwdt_ll_check_if_enabled(rwdt_dev_t *hw)
{
return (hw->config0.wdt_en) ? true : false;
}
#define rwdt_ll_set_procpu_reset_en(hw, enable) \
lpwdt_ll_set_procpu_reset_en(hw, enable)
/**
* @brief Configure a particular stage of the RWDT
*
* @param hw Start address of the peripheral registers.
* @param stage Which stage to configure
* @param timeout Number of timer ticks for the stage to timeout (see note).
* @param behavior What action to take when the stage times out
*
* @note The value of of RWDT stage 0 timeout register is special, in
* that an implicit multiplier is applied to that value to produce
* and effective timeout tick value. The multiplier is dependent
* on an EFuse value. Therefore, when configuring stage 0, the valid
* values for the timeout argument are:
* - If Efuse value is 0, any even number between [2,2*UINT32_MAX]
* - If Efuse value is 1, any multiple of 4 between [4,4*UINT32_MAX]
* - If Efuse value is 2, any multiple of 8 between [8,8*UINT32_MAX]
* - If Efuse value is 3, any multiple of 16 between [16,16*UINT32_MAX]
*/
FORCE_INLINE_ATTR void rwdt_ll_config_stage(rwdt_dev_t *hw, wdt_stage_t stage, uint32_t timeout_ticks, wdt_stage_action_t behavior)
{
switch (stage) {
case WDT_STAGE0:
hw->config0.wdt_stg0 = behavior;
//Account of implicty multiplier applied to stage 0 timeout tick config value
hw->config1.val = timeout_ticks >> (1 + REG_GET_FIELD(EFUSE_RD_REPEAT_DATA1_REG, EFUSE_WDT_DELAY_SEL));
break;
case WDT_STAGE1:
hw->config0.wdt_stg1 = behavior;
hw->config2.val = timeout_ticks;
break;
case WDT_STAGE2:
hw->config0.wdt_stg2 = behavior;
hw->config3.val = timeout_ticks;
break;
case WDT_STAGE3:
hw->config0.wdt_stg3 = behavior;
hw->config4.val = timeout_ticks;
break;
default:
abort();
}
}
#define rwdt_ll_set_appcpu_reset_en(hw, enable) \
lpwdt_ll_set_appcpu_reset_en(hw, enable)
/**
* @brief Disable a particular stage of the RWDT
*
* @param hw Start address of the peripheral registers.
* @param stage Which stage to disable
*/
FORCE_INLINE_ATTR void rwdt_ll_disable_stage(rwdt_dev_t *hw, wdt_stage_t stage)
{
switch (stage) {
case WDT_STAGE0:
hw->config0.wdt_stg0 = WDT_STAGE_ACTION_OFF;
break;
case WDT_STAGE1:
hw->config0.wdt_stg1 = WDT_STAGE_ACTION_OFF;
break;
case WDT_STAGE2:
hw->config0.wdt_stg2 = WDT_STAGE_ACTION_OFF;
break;
case WDT_STAGE3:
hw->config0.wdt_stg3 = WDT_STAGE_ACTION_OFF;
break;
default:
abort();
}
}
#define rwdt_ll_set_pause_in_sleep_en(hw, enable) \
lpwdt_ll_set_pause_in_sleep_en(hw, enable)
/**
* @brief Set the length of the CPU reset action
*
* @param hw Start address of the peripheral registers.
* @param length Length of CPU reset signal
*/
FORCE_INLINE_ATTR void rwdt_ll_set_cpu_reset_length(rwdt_dev_t *hw, wdt_reset_sig_length_t length)
{
hw->config0.wdt_cpu_reset_length = length;
}
#define rwdt_ll_set_chip_reset_en(hw, enable) \
lpwdt_ll_set_chip_reset_en(hw, enable)
/**
* @brief Set the length of the system reset action
*
* @param hw Start address of the peripheral registers.
* @param length Length of system reset signal
*/
FORCE_INLINE_ATTR void rwdt_ll_set_sys_reset_length(rwdt_dev_t *hw, wdt_reset_sig_length_t length)
{
hw->config0.wdt_sys_reset_length = length;
}
#define rwdt_ll_set_chip_reset_width(hw, width) \
lpwdt_ll_set_chip_reset_width(hw, width)
/**
* @brief Enable/Disable the RWDT flashboot mode.
*
* @param hw Start address of the peripheral registers.
* @param enable True to enable RWDT flashboot mode, false to disable RWDT flashboot mode.
*
* @note Flashboot mode is independent and can trigger a WDT timeout event if the
* WDT's enable bit is set to 0. Flashboot mode for RWDT is automatically enabled
* on flashboot, and should be disabled by software when flashbooting completes.
*/
FORCE_INLINE_ATTR void rwdt_ll_set_flashboot_en(rwdt_dev_t *hw, bool enable)
{
hw->config0.wdt_flashboot_mod_en = (enable) ? 1 : 0;
}
#define rwdt_ll_feed(hw) \
lpwdt_ll_feed(hw)
/**
* @brief Enable/Disable the CPU0 to be reset on WDT_STAGE_ACTION_RESET_CPU
*
* @param hw Start address of the peripheral registers.
* @param enable True to enable CPU0 to be reset, false to disable.
*/
FORCE_INLINE_ATTR void rwdt_ll_set_procpu_reset_en(rwdt_dev_t *hw, bool enable)
{
hw->config0.wdt_procpu_reset_en = (enable) ? 1 : 0;
}
#define rwdt_ll_write_protect_enable(hw) \
lpwdt_ll_write_protect_enable(hw)
/**
* @brief Enable/Disable the CPU1 to be reset on WDT_STAGE_ACTION_RESET_CPU
*
* @param hw Start address of the peripheral registers.
* @param enable True to enable CPU1 to be reset, false to disable.
*/
FORCE_INLINE_ATTR void rwdt_ll_set_appcpu_reset_en(rwdt_dev_t *hw, bool enable)
{
hw->config0.wdt_appcpu_reset_en = (enable) ? 1 : 0;
}
#define rwdt_ll_write_protect_disable(hw) \
lpwdt_ll_write_protect_disable(hw)
/**
* @brief Enable/Disable the RWDT pause during sleep functionality
*
* @param hw Start address of the peripheral registers.
* @param enable True to enable, false to disable.
*/
FORCE_INLINE_ATTR void rwdt_ll_set_pause_in_sleep_en(rwdt_dev_t *hw, bool enable)
{
hw->config0.wdt_pause_in_slp = (enable) ? 1 : 0;
}
#define rwdt_ll_set_intr_enable(hw, enable) \
lpwdt_ll_set_intr_enable(hw, enable)
/**
* @brief Enable/Disable chip reset on RWDT timeout.
*
* A chip reset also resets the analog portion of the chip. It will appear as a
* POWERON reset rather than an RTC reset.
*
* @param hw Start address of the peripheral registers.
* @param enable True to enable, false to disable.
*/
FORCE_INLINE_ATTR void rwdt_ll_set_chip_reset_en(rwdt_dev_t *hw, bool enable)
{
// hw->config0.wdt_chip_reset_en = (enable) ? 1 : 0;
}
#define rwdt_ll_check_intr_status(hw) \
lpwdt_ll_check_intr_status(hw)
/**
* @brief Set width of chip reset signal
*
* @param hw Start address of the peripheral registers.
* @param width Width of chip reset signal in terms of number of RTC_SLOW_CLK cycles
*/
FORCE_INLINE_ATTR void rwdt_ll_set_chip_reset_width(rwdt_dev_t *hw, uint32_t width)
{
// HAL_FORCE_MODIFY_U32_REG_FIELD(hw->config0, wdt_chip_reset_width, width);
}
#define rwdt_ll_clear_intr_status(hw) \
lpwdt_ll_clear_intr_status(hw)
/**
* @brief Feed the RWDT
*
* Resets the current timer count and current stage.
*
* @param hw Start address of the peripheral registers.
*/
FORCE_INLINE_ATTR void rwdt_ll_feed(rwdt_dev_t *hw)
{
// hw->feed.rtc_wdt_feed = 1;
}
/**
* @brief Enable write protection of the RWDT registers
*
* @param hw Start address of the peripheral registers.
*/
FORCE_INLINE_ATTR void rwdt_ll_write_protect_enable(rwdt_dev_t *hw)
{
hw->wprotect.val = 0;
}
/**
* @brief Disable write protection of the RWDT registers
*
* @param hw Start address of the peripheral registers.
*/
FORCE_INLINE_ATTR void rwdt_ll_write_protect_disable(rwdt_dev_t *hw)
{
hw->wprotect.val = RTC_WDT_WKEY_VALUE;
}
/**
* @brief Enable the RWDT interrupt.
*
* @param hw Start address of the peripheral registers.
* @param enable True to enable RWDT interrupt, false to disable.
*/
FORCE_INLINE_ATTR void rwdt_ll_set_intr_enable(rwdt_dev_t *hw, bool enable)
{
hw->int_ena.lp_wdt_int_ena = (enable) ? 1 : 0;
}
/**
* @brief Check if the RWDT interrupt has been triggered
*
* @param hw Start address of the peripheral registers.
* @return True if the RWDT interrupt was triggered
*/
FORCE_INLINE_ATTR bool rwdt_ll_check_intr_status(rwdt_dev_t *hw)
{
return (hw->int_st.lp_wdt_int_st) ? true : false;
}
/**
* @brief Clear the RWDT interrupt status.
*
* @param hw Start address of the peripheral registers.
*/
FORCE_INLINE_ATTR void rwdt_ll_clear_intr_status(rwdt_dev_t *hw)
{
hw->int_clr.lp_wdt_int_clr = 1;
}
#ifdef __cplusplus
}
components/esp_hw_support/include/esp_private/esp_pmu.h
+1 -1
View File
@@ -75,7 +75,7 @@ typedef enum {
#define RTC_GPIO_TRIG_EN (PMU_GPIO_WAKEUP_EN)
#endif
#if SOC_RTC_TIMER_V2_SUPPORTED
#if !SOC_RTC_TIMER_V1
#define RTC_TIMER_TRIG_EN PMU_LP_TIMER_WAKEUP_EN //!< Timer wakeup
#else
#define RTC_TIMER_TRIG_EN 0
components/esp_hw_support/test_apps/rtc_clk/main/test_rtc_clk.c
+2 -2
View File
@@ -247,7 +247,7 @@ static void start_freq(soc_rtc_slow_clk_src_t required_src, uint32_t start_delay
printf("PASS. Time measurement...");
}
uint32_t fail_measure = 0;
#if SOC_RTC_TIMER_V2_SUPPORTED
#if !SOC_RTC_TIMER_V1
uint64_t clk_rtc_time;
for (int j = 0; j < 3; ++j) {
clk_rtc_time = esp_clk_rtc_time();
@@ -338,7 +338,7 @@ TEST_CASE("Test starting 'External 32kHz XTAL' on the board without it.", "[rtc_
#endif // !defined(CONFIG_IDF_CI_BUILD) || !CONFIG_SPIRAM_BANKSWITCH_ENABLE
#endif // SOC_CLK_XTAL32K_SUPPORTED
#if SOC_RTC_TIMER_V2_SUPPORTED
#if !SOC_RTC_TIMER_V1
TEST_CASE("Test rtc clk calibration compensation", "[rtc_clk]")
{
int64_t t1 = esp_rtc_get_time_us();
components/esp_rom/esp32s31/include/esp32s31/rom/rtc.h
+125 -60
View File
@@ -4,15 +4,19 @@
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _ROM_RTC_H_
#define _ROM_RTC_H_
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <stdbool.h>
#include <stdint.h>
#include "esp_assert.h"
#include "soc/soc.h"
#include "soc/lp_system_reg.h"
#include "soc/lp_clkrst_reg.h"
#include "soc/reset_reasons.h"
/** \defgroup rtc_apis, rtc registers and memory related apis
* @brief rtc apis
@@ -44,22 +48,16 @@ extern "C" {
* RTC_CNTL_STORE7_REG FAST_RTC_MEMORY_CRC
*************************************************************************************
*/
#define RTC_CNTL_STORE0_REG LP_SYSTEM_REG_LP_STORE0_REG
#define RTC_CNTL_STORE1_REG LP_SYSTEM_REG_LP_STORE1_REG
#define RTC_CNTL_STORE2_REG LP_SYSTEM_REG_LP_STORE2_REG
#define RTC_CNTL_STORE3_REG LP_SYSTEM_REG_LP_STORE3_REG
#define RTC_CNTL_STORE4_REG LP_SYSTEM_REG_LP_STORE4_REG
#define RTC_CNTL_STORE5_REG LP_SYSTEM_REG_LP_STORE5_REG
#define RTC_CNTL_STORE6_REG LP_SYSTEM_REG_LP_STORE6_REG
#define RTC_CNTL_STORE7_REG LP_SYSTEM_REG_LP_STORE7_REG
#define RTC_CNTL_STORE8_REG LP_SYSTEM_REG_LP_STORE8_REG
#define RTC_CNTL_STORE9_REG LP_SYSTEM_REG_LP_STORE9_REG
#define RTC_CNTL_STORE10_REG LP_SYSTEM_REG_LP_STORE10_REG
#define RTC_CNTL_STORE11_REG LP_SYSTEM_REG_LP_STORE11_REG
#define RTC_CNTL_STORE12_REG LP_SYSTEM_REG_LP_STORE12_REG
#define RTC_CNTL_STORE13_REG LP_SYSTEM_REG_LP_STORE13_REG
#define RTC_CNTL_STORE14_REG LP_SYSTEM_REG_LP_STORE14_REG
#define RTC_CNTL_STORE15_REG LP_SYSTEM_REG_LP_STORE15_REG
#define RTC_SLOW_CLK_CAL_REG LP_SYSTEM_REG_LP_STORE1_REG
#define RTC_BOOT_TIME_LOW_REG LP_SYSTEM_REG_LP_STORE2_REG
#define RTC_BOOT_TIME_HIGH_REG LP_SYSTEM_REG_LP_STORE3_REG
#define RTC_XTAL_FREQ_REG LP_SYSTEM_REG_LP_STORE4_REG
#define RTC_ENTRY_LENGTH_REG LP_SYSTEM_REG_LP_STORE5_REG
#define RTC_ENTRY_ADDR_REG LP_SYSTEM_REG_LP_STORE6_REG
#define RTC_RESET_CAUSE_REG LP_SYSTEM_REG_LP_STORE6_REG
#define RTC_MEMORY_CRC_REG LP_SYSTEM_REG_LP_STORE7_REG
// light sleep
/* use LP_SYS_LP_STORE8_REG to store light sleep wake stub addr and sleep mode for dualcore
*
@@ -71,53 +69,120 @@ extern "C" {
/* this MACRO is common to hpcore and lpcore
* they use different bitmask to check same value
*/
#define SLEEP_MODE_LIGHT_SLEEP 0
// hpcore use bit0 to check the mode
#define SLEEP_MODE_MASK BIT(0)
#define RTC_SLEEP_WAKE_STUB_ADDR_REG LP_SYSTEM_REG_LP_STORE8_REG
#define RTC_SLEEP_MODE_REG LP_SYSTEM_REG_LP_STORE8_REG
#define RTC_LIGHT_SLEEP_WAKE_STUB_ADDR_REG RTC_CNTL_STORE8_REG
#define RTC_LIGHT_SLEEP_RESTORE_FUNC_ADDR_MASK 0xFFFFFFFC
#define SLEEP_MODE_REG RTC_CNTL_STORE8_REG
// system
#define RTC_SLOW_CLK_CAL_REG RTC_CNTL_STORE1_REG
#define RTC_BOOT_TIME_LOW_REG RTC_CNTL_STORE2_REG
#define RTC_BOOT_TIME_HIGH_REG RTC_CNTL_STORE3_REG
#define RTC_XTAL_FREQ_REG RTC_CNTL_STORE4_REG
// deep sleep
#define RTC_ENTRY_LENGTH_REG RTC_CNTL_STORE5_REG
#define RTC_ENTRY_ADDR_REG RTC_CNTL_STORE6_REG
/* use RTC_ENTRY_ADDR_REG[0] to store if we need do stub crc check
* 0: we do not need do crc check, then RTC_MEMORY_CRC_REG and RTC_ENTRY_LENGTH_REG can be freed
* 1: we need do crc check
*/
#define RTC_DEEP_SLEEP_STUB_CHECK_CRC 0x1
#define RTC_MEMORY_CRC_REG RTC_CNTL_STORE7_REG
#define ROM_LOG_CTRL_REG RTC_XTAL_FREQ_REG
#define ROM_LOG_CTRL_REG LP_SYSTEM_REG_LP_STORE4_REG
#define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code.
/* Reset reason hint register - same as RTC_ENTRY_ADDR_REG, can be used for both
* deep sleep wake stub entry address and reset reason hint, since wake stub
* is only used for deep sleep reset.
*/
#define RTC_RESET_CAUSE_REG RTC_ENTRY_ADDR_REG
// used to check if app core need hot boot in start.S
#define APP_CORE_BOOT_ADDR_REG LP_SYS_BOOT_ADDR_HP_CORE1_REG
// used to check if we need do software retention in start.S
#define RESET_REASON_REG LP_AONCLKRST_HPCORE0_RESET_CAUSE_REG
#define RESET_REASON_MASK LP_AONCLKRST_HPCORE0_RESET_CAUSE
#define CORE0_RESET_REASON_POS LP_AONCLKRST_HPCORE0_RESET_CAUSE_S
#define RESET_REASON1_REG LP_AONCLKRST_HPCORE0_RESET_CAUSE_REG
#define RESET_REASON1_MASK LP_AONCLKRST_HPCORE0_RESET_CAUSE
#define CORE1_RESET_REASON_POS LP_AONCLKRST_HPCORE1_RESET_CAUSE_S
typedef enum {
AWAKE = 0, //<CPU ON
LIGHT_SLEEP = BIT0, //CPU waiti, PLL ON. We don't need explicitly set this mode.
DEEP_SLEEP = BIT1 //CPU OFF, PLL OFF, only specific timer could wake up
} SLEEP_MODE;
typedef enum {
SW_CLR = 0,
POWERON_RESET = 1, /**<1, Vbat power on reset*/
SW_SYS_RESET = 3, /**<3, Software reset digital core*/
PMU_SYS_PWR_DOWN_RESET = 5, /**<5, PMU HP system power down reset*/
PMU_CPU_PWR_DOWN_RESET = 6, /**<6, PMU CPU system power down reset*/
HP_SYS_HP_WDT0_RESET = 7, /**<7, HP system reset from HP watchdog0*/
HP_SYS_HP_WDT1_RESET = 8, /**<8, HP system reset from HP watchdog1*/
HP_SYS_LP_WDT_RESET = 9, /**<9, HP system reset from LP watchdog*/
HP_CORE_HP_WDT_RESET = 11, /**<11, HP core reset from HP watchdog*/
SW_CPU_RESET = 12, /**<12, software reset cpu*/
HP_CORE_LP_WDT_RESET = 13, /**<13, HP core reset from LP watchdog*/
BROWN_OUT_RESET = 15, /**<15, Reset when the vdd voltage is not stable*/
CHIP_LP_WDT_RESET = 16, /**<16, LP watchdog chip reset*/
SUPER_WDT_RESET = 18, /**<18, super watchdog reset*/
GLITCH_RTC_RESET = 19, /**<19, glitch reset*/
EFUSE_CRC_ERR_RESET = 20, /**<20, efuse ecc error reset*/
CHIP_USB_JTAG_RESET = 22, /**<22, HP usb jtag chip reset*/
CHIP_USB_UART_RESET = 23, /**<23, HP usb uart chip reset*/
JTAG_RESET = 24, /**<24, jtag reset*/
CPU_LOCKUP_RESET = 26, /**<26, cpu lockup reset*/
} RESET_REASON;
// Check if the reset reason defined in ROM is compatible with soc/reset_reasons.h
ESP_STATIC_ASSERT((soc_reset_reason_t)POWERON_RESET == RESET_REASON_CHIP_POWER_ON, "POWERON_RESET != RESET_REASON_CHIP_POWER_ON");
ESP_STATIC_ASSERT((soc_reset_reason_t)SW_SYS_RESET == RESET_REASON_CORE_SW, "SW_SYS_RESET != RESET_REASON_CORE_SW");
ESP_STATIC_ASSERT((soc_reset_reason_t)PMU_SYS_PWR_DOWN_RESET == RESET_REASON_CORE_DEEP_SLEEP, "PMU_SYS_PWR_DOWN_RESET != RESET_REASON_CORE_DEEP_SLEEP");
ESP_STATIC_ASSERT((soc_reset_reason_t)PMU_SYS_PWR_DOWN_RESET == RESET_REASON_CORE_PMU_PWR_DOWN, "PMU_SYS_PWR_DOWN_RESET != RESET_REASON_CORE_PMU_PWR_DOWN");
ESP_STATIC_ASSERT((soc_reset_reason_t)PMU_CPU_PWR_DOWN_RESET == RESET_REASON_CPU_PMU_PWR_DOWN, "PMU_CPU_PWR_DOWN_RESET != RESET_REASON_CPU_PMU_PWR_DOWN");
ESP_STATIC_ASSERT((soc_reset_reason_t)HP_SYS_HP_WDT0_RESET == RESET_REASON_CORE_MWDT0, "HP_SYS_HP_WDT0_RESET != RESET_REASON_CORE_MWDT0");
ESP_STATIC_ASSERT((soc_reset_reason_t)HP_SYS_HP_WDT1_RESET == RESET_REASON_CORE_MWDT1, "HP_SYS_HP_WDT1_RESET != RESET_REASON_CORE_MWDT1");
ESP_STATIC_ASSERT((soc_reset_reason_t)HP_SYS_LP_WDT_RESET == RESET_REASON_CORE_RWDT, "HP_SYS_LP_WDT_RESET != RESET_REASON_CORE_RWDT");
ESP_STATIC_ASSERT((soc_reset_reason_t)HP_CORE_HP_WDT_RESET == RESET_REASON_CPU_MWDT, "HP_CORE_HP_WDT_RESET != RESET_REASON_CPU_MWDT");
ESP_STATIC_ASSERT((soc_reset_reason_t)SW_CPU_RESET == RESET_REASON_CPU_SW, "SW_CPU_RESET != RESET_REASON_CPU_SW");
ESP_STATIC_ASSERT((soc_reset_reason_t)HP_CORE_LP_WDT_RESET == RESET_REASON_CPU_RWDT, "HP_CORE_LP_WDT_RESET != RESET_REASON_CPU_RWDT");
ESP_STATIC_ASSERT((soc_reset_reason_t)BROWN_OUT_RESET == RESET_REASON_SYS_BROWN_OUT, "BROWN_OUT_RESET != RESET_REASON_SYS_BROWN_OUT");
ESP_STATIC_ASSERT((soc_reset_reason_t)CHIP_LP_WDT_RESET == RESET_REASON_SYS_RWDT, "CHIP_LP_WDT_RESET != RESET_REASON_SYS_RWDT");
ESP_STATIC_ASSERT((soc_reset_reason_t)SUPER_WDT_RESET == RESET_REASON_SYS_SUPER_WDT, "SUPER_WDT_RESET != RESET_REASON_SYS_SUPER_WDT");
ESP_STATIC_ASSERT((soc_reset_reason_t)GLITCH_RTC_RESET == RESET_REASON_CORE_PWR_GLITCH, "GLITCH_RTC_RESET != RESET_REASON_CORE_PWR_GLITCH");
ESP_STATIC_ASSERT((soc_reset_reason_t)EFUSE_CRC_ERR_RESET == RESET_REASON_CORE_EFUSE_CRC, "EFUSE_CRC_ERR_RESET != RESET_REASON_CORE_EFUSE_CRC");
ESP_STATIC_ASSERT((soc_reset_reason_t)CHIP_USB_JTAG_RESET == RESET_REASON_CORE_USB_JTAG, "CHIP_USB_JTAG_RESET != RESET_REASON_CORE_USB_JTAG");
ESP_STATIC_ASSERT((soc_reset_reason_t)CHIP_USB_UART_RESET == RESET_REASON_CORE_USB_UART, "CHIP_USB_UART_RESET != RESET_REASON_CORE_USB_UART");
ESP_STATIC_ASSERT((soc_reset_reason_t)JTAG_RESET == RESET_REASON_CPU_JTAG, "JTAG_RESET != RESET_REASON_CPU_JTAG");
ESP_STATIC_ASSERT((soc_reset_reason_t)CPU_LOCKUP_RESET == RESET_REASON_CPU_LOCKUP, "CPU_LOCKUP_RESET != RESET_REASON_CPU_LOCKUP");
/**
* start.S check reset reason and sleep mode register to decide if doing software retention
*/
#define RESET_REASON_TOP_SLEEP_WAKEUP 5
#define RESET_REASON_CPU_SLEEP_WAKEUP 6 // wake up from CPU domain power-down sleep
* @brief Get the reset reason for CPU.
*
* @param int cpu_no : CPU no.
*
* @return RESET_REASON
*/
RESET_REASON rtc_get_reset_reason(int cpu_no);
/**
* @brief Suppress ROM log by setting specific RTC control register.
* @note This is not a permanent disable of ROM logging since the RTC register can not retain after chip reset.
*
* @param None
*
* @return None
*/
static inline void rtc_suppress_rom_log(void)
{
/* To disable logging in the ROM, only the least significant bit of the register is used,
* but since this register is also used to store the frequency of the main crystal (RTC_XTAL_FREQ_REG),
* you need to write to this register in the same format.
* Namely, the upper 16 bits and lower should be the same.
*/
REG_SET_BIT(LP_SYSTEM_REG_LP_STORE4_REG, RTC_DISABLE_ROM_LOG);
}
/**
* @brief Software Reset digital core.
*
* It is not recommended to use this function in esp-idf, use
* esp_restart() instead.
*
* @param None
*
* @return None
*/
void software_reset(void);
/**
* @brief Software Reset digital core.
*
* It is not recommended to use this function in esp-idf, use
* esp_restart() instead.
*
* @param int cpu_no : The CPU to reset, 0 for PRO CPU, 1 for APP CPU.
*
* @return None
*/
void software_reset_cpu(int cpu_no);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* _ROM_RTC_H_ */
components/hal/esp32s31/include/hal/lp_aon_hal.h
+19
View File
@@ -0,0 +1,19 @@
/*
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "hal/lp_sys_ll.h"
#ifdef __cplusplus
extern "C" {
#endif
#define lp_aon_hal_inform_wakeup_type(dslp) lp_sys_ll_inform_wakeup_type(dslp)
#ifdef __cplusplus
}
#endif
components/hal/esp32s31/include/hal/lp_sys_ll.h
+66
View File
@@ -0,0 +1,66 @@
/*
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The LL layer for ESP32-S31 LP_SYS register operations
#pragma once
#include <stdlib.h>
#include "esp_attr.h"
#include "soc/soc.h"
#include "soc/lp_system_struct.h"
#include "hal/misc.h"
#include "esp32s31/rom/rtc.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief ROM obtains the wake-up type through LP_SYS_STORE9_REG[0].
* Set the flag to inform
* @param true: deepsleep false: lightsleep
*/
FORCE_INLINE_ATTR void lp_sys_ll_inform_wakeup_type(bool dslp)
{
if (dslp) {
REG_SET_BIT(RTC_SLEEP_MODE_REG, BIT(0)); /* Tell rom to run deep sleep wake stub */
} else {
REG_CLR_BIT(RTC_SLEEP_MODE_REG, BIT(0)); /* Tell rom to run light sleep wake stub */
}
}
FORCE_INLINE_ATTR void lp_sys_ll_set_pau_aon_bypass(bool bypass)
{
LP_SYS.backup_dma_cfg1.aon_bypass = bypass ? 1 : 0;
}
FORCE_INLINE_ATTR void lp_sys_ll_set_pau_link_tout_thres(uint32_t tout)
{
LP_SYS.backup_dma_cfg1.link_wait_tout_thres_aon = tout;
LP_SYS.backup_dma_cfg1.link_work_tout_thres_aon = tout;
}
FORCE_INLINE_ATTR void lp_sys_ll_set_pau_link_backup_tout_thres(uint32_t tout)
{
LP_SYS.backup_dma_cfg0.link_backup_tout_thres_aon = tout;
}
FORCE_INLINE_ATTR void lp_sys_ll_set_pau_reg_read_interval(uint32_t val)
{
LP_SYS.backup_dma_cfg0.read_interval_aon = val;
}
FORCE_INLINE_ATTR void lp_sys_ll_set_pau_link_addr(uint32_t addr)
{
LP_SYS.backup_dma_cfg2.link_addr_aon = addr;
}
#ifdef __cplusplus
}
#endif
components/soc/esp32/include/soc/Kconfig.soc_caps.in
+5 -1
View File
@@ -83,7 +83,7 @@ config SOC_RTC_MEM_SUPPORTED
bool
default y
config SOC_RTC_TIMER_V1_SUPPORTED
config SOC_RTC_TIMER_SUPPORTED
bool
default y
@@ -519,6 +519,10 @@ config SOC_LP_TIMER_BIT_WIDTH_HI
int
default 16
config SOC_RTC_TIMER_V1
bool
default y
config SOC_TOUCH_SENSOR_VERSION
int
default 1
components/soc/esp32/include/soc/soc_caps.h
+2 -2
View File
@@ -86,7 +86,7 @@
#define SOC_RTC_FAST_MEM_SUPPORTED 1
#define SOC_RTC_SLOW_MEM_SUPPORTED 1
#define SOC_RTC_MEM_SUPPORTED 1
#define SOC_RTC_TIMER_V1_SUPPORTED 1
#define SOC_RTC_TIMER_SUPPORTED 1
#define SOC_I2S_SUPPORTED 1
#define SOC_I2S_I80_LCD_SUPPORTED 1
#define SOC_LCD_I80_SUPPORTED 1
@@ -262,7 +262,7 @@
/*-------------------------- LP_TIMER CAPS ----------------------------------*/
#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
#define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part
#define SOC_RTC_TIMER_SUPPORTED SOC_RTC_TIMER_V1_SUPPORTED
#define SOC_RTC_TIMER_V1 1
/*-------------------------- TOUCH SENSOR CAPS -------------------------------*/
#define SOC_TOUCH_SENSOR_VERSION (1U) /*!<Hardware version of touch sensor */
components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
+5 -1
View File
@@ -99,7 +99,7 @@ config SOC_BOD_SUPPORTED
bool
default y
config SOC_RTC_TIMER_V1_SUPPORTED
config SOC_RTC_TIMER_SUPPORTED
bool
default y
@@ -487,6 +487,10 @@ config SOC_LP_TIMER_BIT_WIDTH_HI
int
default 16
config SOC_RTC_TIMER_V1
bool
default y
config SOC_MWDT_SUPPORT_XTAL
bool
default y
components/soc/esp32c2/include/soc/soc_caps.h
+2 -2
View File
@@ -47,7 +47,7 @@
#define SOC_SECURE_BOOT_SUPPORTED 1
#define SOC_SYSTIMER_SUPPORTED 1
#define SOC_BOD_SUPPORTED 1
#define SOC_RTC_TIMER_V1_SUPPORTED 1
#define SOC_RTC_TIMER_SUPPORTED 1
#define SOC_CLK_TREE_SUPPORTED 1
#define SOC_ASSIST_DEBUG_SUPPORTED 1
#define SOC_WDT_SUPPORTED 1
@@ -229,7 +229,7 @@
/*-------------------------- LP_TIMER CAPS ----------------------------------*/
#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
#define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part
#define SOC_RTC_TIMER_SUPPORTED SOC_RTC_TIMER_V1_SUPPORTED
#define SOC_RTC_TIMER_V1 1
/*--------------------------- WATCHDOG CAPS ---------------------------------------*/
#define SOC_MWDT_SUPPORT_XTAL (1)
components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
+5 -1
View File
@@ -87,7 +87,7 @@ config SOC_RTC_MEM_SUPPORTED
bool
default y
config SOC_RTC_TIMER_V1_SUPPORTED
config SOC_RTC_TIMER_SUPPORTED
bool
default y
@@ -675,6 +675,10 @@ config SOC_LP_TIMER_BIT_WIDTH_HI
int
default 16
config SOC_RTC_TIMER_V1
bool
default y
config SOC_MWDT_SUPPORT_XTAL
bool
default y
components/soc/esp32c3/include/soc/soc_caps.h
+2 -2
View File
@@ -44,7 +44,7 @@
#define SOC_EFUSE_SUPPORTED 1
#define SOC_RTC_FAST_MEM_SUPPORTED 1
#define SOC_RTC_MEM_SUPPORTED 1
#define SOC_RTC_TIMER_V1_SUPPORTED 1
#define SOC_RTC_TIMER_SUPPORTED 1
#define SOC_I2S_SUPPORTED 1
#define SOC_RMT_SUPPORTED 1
#define SOC_SDM_SUPPORTED 1
@@ -305,7 +305,7 @@
/*-------------------------- LP_TIMER CAPS ----------------------------------*/
#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
#define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part
#define SOC_RTC_TIMER_SUPPORTED SOC_RTC_TIMER_V1_SUPPORTED
#define SOC_RTC_TIMER_V1 1
/*--------------------------- WATCHDOG CAPS ---------------------------------------*/
#define SOC_MWDT_SUPPORT_XTAL (1)
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
+5 -1
View File
@@ -203,7 +203,7 @@ config SOC_PAU_SUPPORTED
bool
default y
config SOC_RTC_TIMER_V2_SUPPORTED
config SOC_RTC_TIMER_SUPPORTED
bool
default y
@@ -1047,6 +1047,10 @@ config SOC_LP_TIMER_BIT_WIDTH_HI
int
default 16
config SOC_RTC_TIMER_V2
bool
default y
config SOC_TIMER_SUPPORT_ETM
bool
default y
components/soc/esp32c5/include/soc/soc_caps.h
+2 -2
View File
@@ -73,7 +73,7 @@
#define SOC_PMU_SUPPORTED 1
#define SOC_PMU_PVT_SUPPORTED 1
#define SOC_PAU_SUPPORTED 1
#define SOC_RTC_TIMER_V2_SUPPORTED 1
#define SOC_RTC_TIMER_SUPPORTED 1
#define SOC_LP_AON_SUPPORTED 1
#define SOC_LP_PERIPHERALS_SUPPORTED 1
#define SOC_LP_I2C_SUPPORTED 1
@@ -432,7 +432,7 @@
/*-------------------------- LP_TIMER CAPS ----------------------------------*/
#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
#define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part
#define SOC_RTC_TIMER_SUPPORTED SOC_RTC_TIMER_V2_SUPPORTED
#define SOC_RTC_TIMER_V2 1
/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
#define SOC_TIMER_SUPPORT_ETM (1)
components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
+5 -1
View File
@@ -195,7 +195,7 @@ config SOC_PAU_SUPPORTED
bool
default y
config SOC_RTC_TIMER_V2_SUPPORTED
config SOC_RTC_TIMER_SUPPORTED
bool
default y
@@ -875,6 +875,10 @@ config SOC_LP_TIMER_BIT_WIDTH_HI
int
default 16
config SOC_RTC_TIMER_V2
bool
default y
config SOC_TIMER_SUPPORT_ETM
bool
default y
components/soc/esp32c6/include/soc/soc_caps.h
+2 -2
View File
@@ -71,7 +71,7 @@
#define SOC_PMU_SUPPORTED 1
#define SOC_PMU_PVT_SUPPORTED 1
#define SOC_PAU_SUPPORTED 1
#define SOC_RTC_TIMER_V2_SUPPORTED 1
#define SOC_RTC_TIMER_SUPPORTED 1
#define SOC_LP_AON_SUPPORTED 1
#define SOC_LP_PERIPHERALS_SUPPORTED 1
#define SOC_LP_I2C_SUPPORTED 1
@@ -371,7 +371,7 @@
/*-------------------------- LP_TIMER CAPS ----------------------------------*/
#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
#define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part
#define SOC_RTC_TIMER_SUPPORTED SOC_RTC_TIMER_V2_SUPPORTED
#define SOC_RTC_TIMER_V2 1
/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
#define SOC_TIMER_SUPPORT_ETM (1)
components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
+5 -1
View File
@@ -123,7 +123,7 @@ config SOC_PMU_PVT_SUPPORTED
bool
default y
config SOC_RTC_TIMER_V2_SUPPORTED
config SOC_RTC_TIMER_SUPPORTED
bool
default y
@@ -807,6 +807,10 @@ config SOC_LP_TIMER_BIT_WIDTH_HI
int
default 16
config SOC_RTC_TIMER_V2
bool
default y
config SOC_TIMER_SUPPORT_SLEEP_RETENTION
bool
default y
components/soc/esp32c61/include/soc/soc_caps.h
+2 -2
View File
@@ -54,7 +54,7 @@
#define SOC_APM_SUPPORTED 1 /*!< Support for APM peripheral */
#define SOC_PMU_SUPPORTED 1
#define SOC_PMU_PVT_SUPPORTED 1
#define SOC_RTC_TIMER_V2_SUPPORTED 1
#define SOC_RTC_TIMER_SUPPORTED 1
#define SOC_LP_AON_SUPPORTED 1
#define SOC_CLK_TREE_SUPPORTED 1
#define SOC_ASSIST_DEBUG_SUPPORTED 1
@@ -339,7 +339,7 @@
/*-------------------------- LP_TIMER CAPS ----------------------------------*/
#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
#define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part
#define SOC_RTC_TIMER_SUPPORTED SOC_RTC_TIMER_V2_SUPPORTED
#define SOC_RTC_TIMER_V2 1
/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
#define SOC_TIMER_SUPPORT_SLEEP_RETENTION (1)
components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
+5 -1
View File
@@ -199,7 +199,7 @@ config SOC_PMU_SUPPORTED
bool
default y
config SOC_RTC_TIMER_V2_SUPPORTED
config SOC_RTC_TIMER_SUPPORTED
bool
default y
@@ -879,6 +879,10 @@ config SOC_LP_TIMER_BIT_WIDTH_HI
int
default 16
config SOC_RTC_TIMER_V2
bool
default y
config SOC_TIMER_SUPPORT_ETM
bool
default y
components/soc/esp32h2/include/soc/soc_caps.h
+2 -2
View File
@@ -88,7 +88,7 @@
#define SOC_VBAT_SUPPORTED 1
#define SOC_APM_SUPPORTED 1 /*!< Support for APM peripheral */
#define SOC_PMU_SUPPORTED 1
#define SOC_RTC_TIMER_V2_SUPPORTED 1
#define SOC_RTC_TIMER_SUPPORTED 1
#define SOC_LP_AON_SUPPORTED 1
#define SOC_PAU_SUPPORTED 1
#define SOC_CLK_TREE_SUPPORTED 1
@@ -389,7 +389,7 @@
/*-------------------------- LP_TIMER CAPS ----------------------------------*/
#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
#define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part
#define SOC_RTC_TIMER_SUPPORTED SOC_RTC_TIMER_V2_SUPPORTED
#define SOC_RTC_TIMER_V2 1
/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
#define SOC_TIMER_SUPPORT_ETM (1)
components/soc/esp32h21/include/soc/Kconfig.soc_caps.in
+5 -1
View File
@@ -111,7 +111,7 @@ config SOC_PMU_SUPPORTED
bool
default y
config SOC_RTC_TIMER_V2_SUPPORTED
config SOC_RTC_TIMER_SUPPORTED
bool
default y
@@ -699,6 +699,10 @@ config SOC_LP_TIMER_BIT_WIDTH_HI
int
default 16
config SOC_RTC_TIMER_V2
bool
default y
config SOC_TIMER_SUPPORT_ETM
bool
default y
components/soc/esp32h21/include/soc/soc_caps.h
+2 -2
View File
@@ -61,7 +61,7 @@
// #define SOC_BOD_SUPPORTED 1 //TODO: [ESP32H21] IDF-11530
// #define SOC_APM_SUPPORTED 1 //TODO: [ESP32H21] IDF-11494
#define SOC_PMU_SUPPORTED 1
#define SOC_RTC_TIMER_V2_SUPPORTED 1
#define SOC_RTC_TIMER_SUPPORTED 1
#define SOC_LP_AON_SUPPORTED 1
// #define SOC_LP_PERIPHERALS_SUPPORTED 1
#define SOC_CLK_TREE_SUPPORTED 1
@@ -366,7 +366,7 @@
/*-------------------------- LP_TIMER CAPS ----------------------------------*/
#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
#define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part
#define SOC_RTC_TIMER_SUPPORTED SOC_RTC_TIMER_V2_SUPPORTED
#define SOC_RTC_TIMER_V2 1
/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
#define SOC_TIMER_SUPPORT_ETM (1)
components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
+5 -1
View File
@@ -139,7 +139,7 @@ config SOC_PAU_SUPPORTED
bool
default y
config SOC_RTC_TIMER_V2_SUPPORTED
config SOC_RTC_TIMER_SUPPORTED
bool
default y
@@ -779,6 +779,10 @@ config SOC_LP_TIMER_BIT_WIDTH_HI
int
default 16
config SOC_RTC_TIMER_V2
bool
default y
config SOC_TIMER_SUPPORT_ETM
bool
default y
components/soc/esp32h4/include/soc/soc_caps.h
+2 -2
View File
@@ -77,7 +77,7 @@
// #define SOC_APM_SUPPORTED 1 // TODO: [ESP32H4] IDF-12256
#define SOC_PMU_SUPPORTED 1 // TODO: [ESP32H4] IDF-12286
#define SOC_PAU_SUPPORTED 1
#define SOC_RTC_TIMER_V2_SUPPORTED 1
#define SOC_RTC_TIMER_SUPPORTED 1
#define SOC_LP_AON_SUPPORTED 1
#define SOC_TOUCH_SENSOR_SUPPORTED 1
// #define SOC_LP_PERIPHERALS_SUPPORTED 1
@@ -388,7 +388,7 @@
/*-------------------------- LP_TIMER CAPS ----------------------------------*/
#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
#define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part
#define SOC_RTC_TIMER_SUPPORTED SOC_RTC_TIMER_V2_SUPPORTED
#define SOC_RTC_TIMER_V2 1
/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
#define SOC_TIMER_SUPPORT_ETM (1)
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
+5 -1
View File
@@ -267,7 +267,7 @@ config SOC_PAU_SUPPORTED
bool
default y
config SOC_RTC_TIMER_V2_SUPPORTED
config SOC_RTC_TIMER_SUPPORTED
bool
default y
@@ -1427,6 +1427,10 @@ config SOC_LP_TIMER_BIT_WIDTH_HI
int
default 16
config SOC_RTC_TIMER_V2
bool
default y
config SOC_TIMER_SUPPORT_ETM
bool
default y
components/soc/esp32p4/include/soc/soc_caps.h
+2 -2
View File
@@ -89,7 +89,7 @@
#define SOC_PVT_RETENTION_BY_REGDMA 1
#define SOC_DCDC_SUPPORTED 1
#define SOC_PAU_SUPPORTED 1 //TODO: IDF-7531
#define SOC_RTC_TIMER_V2_SUPPORTED 1
#define SOC_RTC_TIMER_SUPPORTED 1
#define SOC_ULP_LP_UART_SUPPORTED 1
#define SOC_LP_GPIO_MATRIX_SUPPORTED 1
#define SOC_LP_PERIPHERALS_SUPPORTED 1
@@ -547,7 +547,7 @@
/*-------------------------- LP_TIMER CAPS ----------------------------------*/
#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
#define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part
#define SOC_RTC_TIMER_SUPPORTED SOC_RTC_TIMER_V2_SUPPORTED
#define SOC_RTC_TIMER_V2 1
/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
#define SOC_TIMER_SUPPORT_ETM 1
components/soc/esp32s2/include/soc/Kconfig.soc_caps.in
+5 -1
View File
@@ -99,7 +99,7 @@ config SOC_RTC_MEM_SUPPORTED
bool
default y
config SOC_RTC_TIMER_V1_SUPPORTED
config SOC_RTC_TIMER_SUPPORTED
bool
default y
@@ -587,6 +587,10 @@ config SOC_LP_TIMER_BIT_WIDTH_HI
int
default 16
config SOC_RTC_TIMER_V1
bool
default y
config SOC_TOUCH_SENSOR_VERSION
int
default 2
components/soc/esp32s2/include/soc/soc_caps.h
+2 -2
View File
@@ -67,7 +67,7 @@
#define SOC_RTC_FAST_MEM_SUPPORTED 1
#define SOC_RTC_SLOW_MEM_SUPPORTED 1
#define SOC_RTC_MEM_SUPPORTED 1
#define SOC_RTC_TIMER_V1_SUPPORTED 1
#define SOC_RTC_TIMER_SUPPORTED 1
#define SOC_PSRAM_DMA_CAPABLE 1
#define SOC_XT_WDT_SUPPORTED 1
#define SOC_I2S_SUPPORTED 1
@@ -275,7 +275,7 @@
/*-------------------------- LP_TIMER CAPS ----------------------------------*/
#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
#define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part
#define SOC_RTC_TIMER_SUPPORTED SOC_RTC_TIMER_V1_SUPPORTED
#define SOC_RTC_TIMER_V1 1
/*-------------------------- TOUCH SENSOR CAPS -------------------------------*/
#define SOC_TOUCH_SENSOR_VERSION (2) /*!< Hardware version of touch sensor */
components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
+5 -1
View File
@@ -135,7 +135,7 @@ config SOC_RTC_MEM_SUPPORTED
bool
default y
config SOC_RTC_TIMER_V1_SUPPORTED
config SOC_RTC_TIMER_SUPPORTED
bool
default y
@@ -699,6 +699,10 @@ config SOC_LP_TIMER_BIT_WIDTH_HI
int
default 16
config SOC_RTC_TIMER_V1
bool
default y
config SOC_TOUCH_SENSOR_VERSION
int
default 2
components/soc/esp32s3/include/soc/soc_caps.h
+2 -2
View File
@@ -61,7 +61,7 @@
#define SOC_RTC_FAST_MEM_SUPPORTED 1
#define SOC_RTC_SLOW_MEM_SUPPORTED 1
#define SOC_RTC_MEM_SUPPORTED 1
#define SOC_RTC_TIMER_V1_SUPPORTED 1
#define SOC_RTC_TIMER_SUPPORTED 1
#define SOC_PSRAM_DMA_CAPABLE 1
#define SOC_XT_WDT_SUPPORTED 1
#define SOC_I2S_SUPPORTED 1
@@ -296,7 +296,7 @@
/*-------------------------- LP_TIMER CAPS ----------------------------------*/
#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
#define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part
#define SOC_RTC_TIMER_SUPPORTED SOC_RTC_TIMER_V1_SUPPORTED
#define SOC_RTC_TIMER_V1 1
/*-------------------------- TOUCH SENSOR CAPS -------------------------------*/
#define SOC_TOUCH_SENSOR_VERSION (2) /*!< Hardware version of touch sensor */
components/soc/esp32s31/include/soc/Kconfig.soc_caps.in
+16
View File
@@ -51,6 +51,10 @@ config SOC_SYSTIMER_SUPPORTED
bool
default y
config SOC_RTC_TIMER_SUPPORTED
bool
default y
config SOC_PSRAM_DMA_CAPABLE
bool
default y
@@ -410,3 +414,15 @@ config SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE
config SOC_RCC_IS_INDEPENDENT
bool
default y
config SOC_LP_TIMER_BIT_WIDTH_LO
int
default 32
config SOC_LP_TIMER_BIT_WIDTH_HI
int
default 16
config SOC_RTC_TIMER_V3
bool
default y
components/soc/esp32s31/include/soc/soc_caps.h
+6 -1
View File
@@ -73,7 +73,7 @@
// #define SOC_BOD_SUPPORTED 1 // TODO: [ESP32S31] IDF-14658
// #define SOC_APM_SUPPORTED 1 // TODO: [ESP32S31] IDF-14620
// #define SOC_PMU_SUPPORTED 1 // TODO: [ESP32S31] IDF-14642
// #define SOC_RTC_TIMER_V2_SUPPORTED 1 // TODO: [ESP32S31] IDF-14638
#define SOC_RTC_TIMER_SUPPORTED 1
// #define SOC_ULP_LP_UART_SUPPORTED 1 // TODO: [ESP32S31] IDF-14634
// #define SOC_LP_GPIO_MATRIX_SUPPORTED 1 // TODO: [ESP32S31] IDF-14785
// #define SOC_LP_PERIPHERALS_SUPPORTED 1 // TODO: [ESP32S31] IDF-14785
@@ -284,3 +284,8 @@
#define SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE (1) /*!< Any regi2c operation needs enable the analog i2c master clock first */
#define SOC_RCC_IS_INDEPENDENT 1 /*!< Reset and Clock Control has own registers for each module */
/*-------------------------- LP_TIMER CAPS ----------------------------------*/
#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
#define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part
#define SOC_RTC_TIMER_V3 1
components/soc/esp32s31/ld/esp32s31.peripherals.ld
+2 -2
View File
@@ -93,8 +93,8 @@ PROVIDE ( LP_IO_MUX = 0x20712000 );
PROVIDE ( LP_GPIO = 0x20713000 );
PROVIDE ( LP_INTR = 0x20714000 );
PROVIDE ( EFUSE = 0x20715000 );
PROVIDE ( LP_TIMER = 0x20800000 );
PROVIDE ( LP_WDT = 0x20801000 );
PROVIDE ( RTC_TIMER = 0x20800000 );
PROVIDE ( RTC_WDT = 0x20801000 );
PROVIDE ( LP_CLOCK_CALI0 = 0x20802000 );
PROVIDE ( LP_CLOCK_CALI1 = 0x20803000 );
PROVIDE ( LP_PWR_REG = 0x20804000 );
components/soc/esp32s31/register/soc/reg_base.h
+3 -3
View File
@@ -82,7 +82,7 @@
#define DR_REG_HP_PERI1_PMS_BASE 0x2058A000
#define DR_REG_LP_SYS_BASE 0x20700000
#define DR_REG_LP_CLKRST_BASE 0x20701000
#define DR_REG_LP_ANA_PERI_BASE 0x20702000
#define DR_REG_LP_ANA_BASE 0x20702000
#define DR_REG_HUK_BASE 0x20703000
#define DR_REG_PMU_BASE 0x20704000
#define DR_REG_TOUCH_AON_BASE 0x20705000
@@ -94,8 +94,8 @@
#define DR_REG_LP_GPIO_BASE 0x20713000
#define DR_REG_LP_INTR_BASE 0x20714000
#define DR_REG_EFUSE_BASE 0x20715000
#define DR_REG_LP_TIMER_BASE 0x20800000
#define DR_REG_LP_WDT_BASE 0x20801000
#define DR_REG_RTC_TIMER_BASE 0x20800000
#define DR_REG_RTC_WDT_BASE 0x20801000
#define DR_REG_RTCLOCKCALI0_BASE 0x20802000
#define DR_REG_RTCLOCKCALI1_BASE 0x20803000
#define DR_REG_LP_PWR_REG_BASE 0x20804000
components/soc/include/soc/rtc_cntl_periph.h
+34 -29
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2019-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2019-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
*/
@@ -29,41 +29,46 @@
#include "soc/lp_iomux_struct.h"
#endif
// TODO: IDF-5645
#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61 || CONFIG_IDF_TARGET_ESP32H4 || CONFIG_IDF_TARGET_ESP32S31
#include "soc/lp_analog_peri_reg.h"
#include "soc/lp_clkrst_reg.h"
#include "soc/lp_clkrst_struct.h"
#if SOC_RTC_TIMER_V1
#include "soc/rtc_cntl_reg.h"
#include "soc/rtc_cntl_struct.h"
#elif SOC_RTC_TIMER_V2
#include "soc/lp_timer_reg.h"
#include "soc/lp_timer_struct.h"
#elif SOC_RTC_TIMER_V3
#include "soc/rtc_timer_reg.h"
#include "soc/rtc_timer_struct.h"
#endif
#if SOC_PMU_SUPPORTED
#include "soc/pmu_reg.h"
#endif
#if SOC_LP_I2C_SUPPORTED
#include "soc/lp_i2c_reg.h"
#include "soc/lp_i2c_struct.h"
#endif
#if SOC_RTC_TIMER_V2_SUPPORTED
#include "soc/lp_timer_reg.h"
#include "soc/lp_timer_struct.h"
#endif
#if SOC_ULP_LP_UART_SUPPORTED
#include "soc/lp_uart_reg.h"
#include "soc/lp_uart_struct.h"
#endif
#include "soc/lp_wdt_reg.h"
#include "soc/lp_wdt_struct.h"
#elif CONFIG_IDF_TARGET_ESP32H2
// ESP32H2-TODO: IDF-6327
#if __has_include("soc/lp_analog_peri_reg.h")
#include "soc/lp_analog_peri_reg.h"
#include "soc/lp_clkrst_reg.h"
#include "soc/lp_clkrst_struct.h"
#include "soc/lp_timer_reg.h"
#include "soc/lp_timer_struct.h"
#include "soc/lp_wdt_reg.h"
#include "soc/lp_wdt_struct.h"
#elif CONFIG_IDF_TARGET_ESP32H21
#include "soc/lp_analog_peri_reg.h"
#include "soc/lp_clkrst_reg.h"
#include "soc/lp_clkrst_struct.h"
#include "soc/lp_wdt_reg.h"
#include "soc/lp_wdt_struct.h"
#else
#include "soc/rtc_cntl_reg.h"
#include "soc/rtc_cntl_struct.h"
#endif
#if __has_include("soc/lp_clkrst_reg.h")
#include "soc/lp_clkrst_reg.h"
#include "soc/lp_clkrst_struct.h"
#endif
#if __has_include("soc/lp_wdt_reg.h")
#include "soc/lp_wdt_reg.h"
#include "soc/lp_wdt_struct.h"
#endif
#if __has_include("soc/rtc_wdt_reg.h")
#include "soc/rtc_wdt_reg.h"
#include "soc/rtc_wdt_struct.h"
#endif
components/ulp/CMakeLists.txt
+1 -1
View File
@@ -65,7 +65,7 @@ if(CONFIG_ULP_COPROC_TYPE_LP_CORE)
list(APPEND srcs "lp_core/lp_core_i2c.c")
endif()
if(CONFIG_SOC_RTC_TIMER_V2_SUPPORTED)
if(CONFIG_SOC_RTC_TIMER_V2)
list(APPEND srcs "lp_core/shared/ulp_lp_core_lp_timer_shared.c")
endif()
components/ulp/lp_core/lp_core.c
+1 -1
View File
@@ -127,7 +127,7 @@ esp_err_t ulp_lp_core_run(ulp_lp_core_cfg_t* cfg)
}
#endif
#if SOC_RTC_TIMER_V2_SUPPORTED
#if SOC_RTC_TIMER_SUPPORTED
ulp_lp_core_memory_shared_cfg_t* shared_mem = ulp_lp_core_memory_shared_cfg_get();
if (cfg->wakeup_source & ULP_LP_CORE_WAKEUP_SOURCE_LP_TIMER) {
components/ulp/lp_core/lp_core/include/ulp_lp_core_utils.h
+1 -1
View File
@@ -141,7 +141,7 @@ static inline void ulp_lp_core_sw_intr_clear(void)
return ulp_lp_core_sw_intr_from_hp_clear();
}
#if SOC_RTC_TIMER_V2_SUPPORTED
#if SOC_RTC_TIMER_SUPPORTED
/**
* @brief Enable the LP Timer interrupt
*
components/ulp/lp_core/lp_core/lp_core_startup.c
+2 -2
View File
@@ -28,13 +28,13 @@ void lp_core_startup()
ulp_lp_core_memory_shared_cfg_t* shared_mem = ulp_lp_core_memory_shared_cfg_get();
#if SOC_RTC_TIMER_V2_SUPPORTED
#if SOC_RTC_TIMER_SUPPORTED
uint64_t sleep_duration_ticks = shared_mem->sleep_duration_ticks;
if (sleep_duration_ticks) {
ulp_lp_core_lp_timer_set_wakeup_ticks(sleep_duration_ticks);
}
#endif // SOC_RTC_TIMER_V2_SUPPORTED
#endif // SOC_RTC_TIMER_SUPPORTED
ulp_lp_core_halt();
}
components/ulp/lp_core/lp_core/lp_core_utils.c
+5 -5
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -19,7 +19,7 @@
#include "hal/lp_i2s_ll.h"
#endif
#if SOC_RTC_TIMER_V2_SUPPORTED
#if SOC_RTC_TIMER_SUPPORTED
#include "hal/rtc_timer_ll.h"
#endif
@@ -82,13 +82,13 @@ void ulp_lp_core_update_wakeup_cause(void)
}
#endif /* SOC_ETM_SUPPORTED */
#if SOC_RTC_TIMER_V2_SUPPORTED
#if SOC_RTC_TIMER_SUPPORTED
if ((lp_core_ll_get_wakeup_source() & LP_CORE_LL_WAKEUP_SOURCE_LP_TIMER) \
&& (rtc_timer_ll_get_intr_raw(&LP_TIMER, 1) & LP_TIMER_MAIN_TIMER_LP_INT_RAW)) {
lp_wakeup_cause |= LP_CORE_LL_WAKEUP_SOURCE_LP_TIMER;
rtc_timer_ll_clear_alarm_intr_status(&LP_TIMER, 1);
}
#endif /* SOC_RTC_TIMER_V2_SUPPORTED */
#endif /* SOC_RTC_TIMER_SUPPORTED */
}
@@ -196,7 +196,7 @@ void ulp_lp_core_sw_intr_from_hp_clear(void)
pmu_ll_lp_clear_sw_intr_status(&PMU);
}
#if SOC_RTC_TIMER_V2_SUPPORTED
#if SOC_RTC_TIMER_SUPPORTED
void ulp_lp_core_lp_timer_intr_enable(bool enable)
{
rtc_timer_ll_alarm_intr_enable(&LP_TIMER, 1, enable);
components/ulp/lp_core/shared/ulp_lp_core_lp_timer_shared.c
+2 -2
View File
@@ -6,7 +6,7 @@
#include "ulp_lp_core_lp_timer_shared.h"
#include "soc/soc_caps.h"
#if SOC_RTC_TIMER_V2_SUPPORTED
#if SOC_RTC_TIMER_SUPPORTED
#include "hal/rtc_timer_ll.h"
#include "hal/clk_tree_ll.h"
#include "soc/rtc.h"
@@ -45,4 +45,4 @@ uint64_t ulp_lp_core_lp_timer_calculate_sleep_ticks(uint64_t sleep_duration_us)
return (sleep_duration_us * (1 << RTC_CLK_CAL_FRACT) / clk_ll_rtc_slow_load_cal());
}
#endif // SOC_RTC_TIMER_V2_SUPPORTED
#endif // SOC_RTC_TIMER_SUPPORTED
components/ulp/test_apps/lp_core/lp_core_basic_tests/main/CMakeLists.txt
+2 -2
View File
@@ -30,7 +30,7 @@ list(APPEND app_sources "test_lp_core_prefix.c")
set(lp_core_sources "lp_core/test_main.c")
set(lp_core_sources_counter "lp_core/test_main_counter.c")
if(CONFIG_SOC_RTC_TIMER_V2_SUPPORTED)
if(CONFIG_SOC_RTC_TIMER_SUPPORTED)
set(lp_core_sources_set_timer_wakeup "lp_core/test_main_set_timer_wakeup.c")
endif()
@@ -71,7 +71,7 @@ ulp_embed_binary(lp_core_test_app "${lp_core_sources}" "${lp_core_exp_dep_srcs}"
ulp_embed_binary(lp_core_test_app_counter "${lp_core_sources_counter}" "${lp_core_exp_dep_srcs}")
ulp_embed_binary(lp_core_test_app_isr "lp_core/test_main_isr.c" "${lp_core_exp_dep_srcs}")
if(CONFIG_SOC_RTC_TIMER_V2_SUPPORTED)
if(CONFIG_SOC_RTC_TIMER_SUPPORTED)
ulp_embed_binary(lp_core_test_app_set_timer_wakeup "${lp_core_sources_set_timer_wakeup}" "${lp_core_exp_dep_srcs}")
endif()
components/ulp/test_apps/lp_core/lp_core_basic_tests/main/test_lp_core.c
+4 -4
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -13,7 +13,7 @@
#include "lp_core_test_app_counter.h"
#include "lp_core_test_app_isr.h"
#if SOC_RTC_TIMER_V2_SUPPORTED
#if SOC_RTC_TIMER_SUPPORTED
#include "lp_core_test_app_set_timer_wakeup.h"
#endif
@@ -295,7 +295,7 @@ TEST_CASE("LP core can be stopped and and started again from main CPU", "[ulp]")
}
}
#if SOC_RTC_TIMER_V2_SUPPORTED
#if SOC_RTC_TIMER_SUPPORTED
TEST_CASE("LP core can schedule next wake-up time by itself", "[ulp]")
{
int64_t start, test_duration;
@@ -342,7 +342,7 @@ TEST_CASE("LP core gpio tests", "[ulp]")
}
#endif //SOC_RTCIO_PIN_COUNT > 0
#endif // SOC_RTC_TIMER_V2_SUPPORTED
#endif // SOC_RTC_TIMER_SUPPORTED
#define ISR_TEST_ITERATIONS 100
#define IO_TEST_PIN 0