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Merge branch 'feat/esp32s31_usb_support' into 'master'

Browse Source 
feat(usb): add ESP32-S31 DWC/UTMI support

See merge request espressif/esp-idf!46329
This commit is contained in:
Igor Masar
2026-04-09 01:44:30 +08:00
parent 508ba7ae04 9ab7d5eb03
commit 0b695dbe20
30 changed files with 3097 additions and 69 deletions
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components/esp_hal_usb/CMakeLists.txt
+7 -2
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@@ -11,9 +11,14 @@ if(EXISTS "${CMAKE_CURRENT_LIST_DIR}/${target}/include")
list(APPEND includes "${target}/include")
endif()
# USB-DWC related source files and USB FSLS PHY wrapper
# USB-DWC related source files
if(CONFIG_SOC_USB_OTG_SUPPORTED)
list(APPEND srcs "usb_dwc_hal.c" "usb_wrap_hal.c" "${target}/usb_dwc_periph.c")
list(APPEND srcs "usb_dwc_hal.c" "${target}/usb_dwc_periph.c")
endif()
# USB FSLS PHY wrapper
if(CONFIG_SOC_USB_FSLS_PHY_NUM GREATER 0)
list(APPEND srcs "usb_wrap_hal.c")
endif()
# USB UTMI PHY
components/esp_hal_usb/esp32p4/include/hal/usb_utmi_ll.h
+28 -1
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -12,6 +12,10 @@
#include "soc/hp_sys_clkrst_struct.h"
#include "soc/hp_system_struct.h"
#include "soc/usb_utmi_struct.h"
#include "hal/config.h"
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
#include "soc/lp_system_struct.h"
#endif
#ifdef __cplusplus
extern "C" {
@@ -81,6 +85,29 @@ FORCE_INLINE_ATTR void _usb_utmi_ll_reset_register(void)
_usb_utmi_ll_reset_register(__VA_ARGS__); \
} while(0)
/**
* @brief Enable/disable 15k pulldown resistors on D+/D- lines
*
* In USB Host mode, 15k pulldown resistors must be connected on both D+ and D-.
* In USB Device mode, pulldown resistors must be disconnected.
*
* @note On ESP32-P4 v3+, pulldowns are no longer controlled by USB-OTG peripheral
* and must be controlled by software via LP_SYS registers.
* On earlier revisions, pulldowns are controlled by USB-OTG hardware.
*
* @param[in] enable true to connect pulldowns (Host mode), false to disconnect (Device mode)
*/
FORCE_INLINE_ATTR void usb_utmi_ll_enable_data_pulldowns(bool enable)
{
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
LP_SYS.hp_usb_otghs_phy_ctrl.hp_utmiotg_dppulldown = enable;
LP_SYS.hp_usb_otghs_phy_ctrl.hp_utmiotg_dmpulldown = enable;
#else
// On pre-v3 ESP32-P4, pulldowns are controlled by the USB-OTG peripheral
(void)enable;
#endif
}
/**
* @brief Enable precise detection of VBUS
*
components/esp_hal_usb/esp32s31/include/hal/usb_dwc_ll.h
+1104
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components/esp_hal_usb/esp32s31/include/hal/usb_utmi_ll.h
+136
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@@ -0,0 +1,136 @@
/*
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdbool.h>
#include "esp_attr.h"
#include "soc/soc.h"
#include "soc/cnnt_sys_struct.h"
#include "soc/hp_alive_sys_struct.h"
#include "soc/hp_sys_clkrst_struct.h"
#include "soc/reg_base.h"
#include "soc/usb_utmi_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
/* ---------------------------- USB PHY Control ---------------------------- */
#define USB_UTMI_LL_CNNT_SYS_REG ((volatile cnnt_dev_t *)DR_REG_CNNT_SYS_REG_BASE)
/**
* @brief Configure Low-Speed mode
*
* @param[in] hw Beginning address of the peripheral registers
* @param[in] parallel Parallel or serial LS mode
*/
FORCE_INLINE_ATTR void usb_utmi_ll_configure_ls(usb_utmi_dev_t *hw, bool parallel)
{
hw->fc_06.ls_par_en = parallel;
hw->fc_06.ls_kpalv_en = 1;
}
/* ----------------------------- RCC Functions ----------------------------- */
/**
* @brief Enable/disable bus clock for USB UTMI PHY and USB OTG HS controller
*
* @param[in] clk_en True to enable, false to disable
*/
FORCE_INLINE_ATTR void _usb_utmi_ll_enable_bus_clock(bool clk_en)
{
cnnt_sys_usb_otg20_ctrl_reg_t sys_usb_otg20_ctrl;
HP_SYS_CLKRST.usb_otghs_ctrl0.reg_usb_otghs_apb_clk_en = clk_en;
HP_SYS_CLKRST.usb_otghs_ctrl0.reg_usb_otghs_sys_clk_en = clk_en;
sys_usb_otg20_ctrl.val = USB_UTMI_LL_CNNT_SYS_REG->sys_usb_otg20_ctrl.val;
sys_usb_otg20_ctrl.sys_usb_otg20_utmifs_clk_en = clk_en;
sys_usb_otg20_ctrl.sys_usb_otg20_phyref_clk_en = clk_en;
USB_UTMI_LL_CNNT_SYS_REG->sys_usb_otg20_ctrl.val = sys_usb_otg20_ctrl.val;
// Enable/disable PHY PLL (must be force-enabled on ESP32-S31, as the default is off)
HP_ALIVE_SYS.usb_otghs_ctrl.reg_usb_otghs_phy_pll_force_en = clk_en;
HP_ALIVE_SYS.usb_otghs_ctrl.reg_usb_otghs_phy_pll_en = clk_en;
}
// HP_SYS_CLKRST.usb_otghs_ctrl0 and sys_usb_otg20_ctrl only contain USB OTG fields, no atomic wrapper needed
#define usb_utmi_ll_enable_bus_clock(...) _usb_utmi_ll_enable_bus_clock(__VA_ARGS__)
/**
* @brief Get USB UTMI bus clock status
*
* @return true if enabled, false otherwise
*/
FORCE_INLINE_ATTR bool _usb_utmi_ll_bus_clock_is_enabled(void)
{
return HP_SYS_CLKRST.usb_otghs_ctrl0.reg_usb_otghs_apb_clk_en &&
HP_SYS_CLKRST.usb_otghs_ctrl0.reg_usb_otghs_sys_clk_en &&
USB_UTMI_LL_CNNT_SYS_REG->sys_usb_otg20_ctrl.sys_usb_otg20_utmifs_clk_en &&
USB_UTMI_LL_CNNT_SYS_REG->sys_usb_otg20_ctrl.sys_usb_otg20_phyref_clk_en;
}
/**
* @brief Reset USB UTMI PHY and USB OTG HS controller
*
* @note PHY reset must be de-asserted before controller reset,
* so that the PHY is stable when the controller starts.
*/
FORCE_INLINE_ATTR void _usb_utmi_ll_reset_register(void)
{
cnnt_sys_usb_otg20_ctrl_reg_t sys_usb_otg20_ctrl;
sys_usb_otg20_ctrl.val = USB_UTMI_LL_CNNT_SYS_REG->sys_usb_otg20_ctrl.val;
// Assert all resets
sys_usb_otg20_ctrl.sys_usb_otg20_ahb_rst_en = 1;
sys_usb_otg20_ctrl.sys_usb_otg20_apb_rst_en = 1;
sys_usb_otg20_ctrl.sys_usb_otg20_phy_rst_en = 1;
USB_UTMI_LL_CNNT_SYS_REG->sys_usb_otg20_ctrl.val = sys_usb_otg20_ctrl.val;
// De-assert PHY reset first
sys_usb_otg20_ctrl.sys_usb_otg20_phy_rst_en = 0;
USB_UTMI_LL_CNNT_SYS_REG->sys_usb_otg20_ctrl.val = sys_usb_otg20_ctrl.val;
// De-assert controller resets
sys_usb_otg20_ctrl.sys_usb_otg20_ahb_rst_en = 0;
sys_usb_otg20_ctrl.sys_usb_otg20_apb_rst_en = 0;
USB_UTMI_LL_CNNT_SYS_REG->sys_usb_otg20_ctrl.val = sys_usb_otg20_ctrl.val;
}
// sys_usb_otg20_ctrl only contains USB OTG fields, no atomic wrapper needed
#define usb_utmi_ll_reset_register(...) _usb_utmi_ll_reset_register(__VA_ARGS__)
/**
* @brief Enable/disable 15k pulldown resistors on D+/D- lines
*
* In USB Host mode, 15k pulldown resistors must be connected on both D+ and D-.
* In USB Device mode, pulldown resistors must be disconnected.
*
* @param[in] enable true to connect pulldowns (Host mode), false to disconnect (Device mode)
*/
FORCE_INLINE_ATTR void usb_utmi_ll_enable_data_pulldowns(bool enable)
{
HP_ALIVE_SYS.usb_ctrl.usb_otghs_phy_dppulldown = enable;
HP_ALIVE_SYS.usb_ctrl.usb_otghs_phy_dmpulldown = enable;
}
/**
* @brief Enable precise VBUS/disconnection detection path
*
* @param[in] enable Enable/disable precise detection
*/
FORCE_INLINE_ATTR void usb_utmi_ll_enable_precise_detection(bool enable)
{
HP_ALIVE_SYS.usb_otghs_ctrl.reg_usb_otghs_phy_otg_suspendm = enable;
HP_ALIVE_SYS.usb_otghs_ctrl.reg_usb_otghs_phy_suspendm = enable;
}
#ifdef __cplusplus
}
#endif
components/esp_hal_usb/esp32s31/usb_dwc_periph.c
+24
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@@ -0,0 +1,24 @@
/*
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stddef.h>
#include "soc/interrupts.h"
#include "soc/usb_periph.h"
/* --------------------------------- Public --------------------------------- */
const usb_dwc_info_t usb_dwc_info = {
.controllers = {
[0] = {
.fsls_signals = NULL,
.otg_signals = NULL,
.internal_phy_io = NULL, // HS PHY is not mapped to any GPIO
.supported_phys = USB_PHY_INST_UTMI_0,
.irq = ETS_USB_OTGHS_INTR_SOURCE,
.irq_2nd_cpu = ETS_USB_OTGHS_ENDP_MULTI_PROC_INTR_SOURCE,
},
},
};
components/esp_hal_usb/include/hal/usb_utmi_hal.h
+11 -1
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -57,6 +57,16 @@ void _usb_utmi_hal_disable(void);
#define usb_utmi_hal_disable(...) do {(void)__DECLARE_RCC_ATOMIC_ENV; _usb_utmi_hal_disable(__VA_ARGS__);} while(0)
#endif
/**
* @brief Enable/disable 15k pulldown resistors on D+/D- lines
*
* In USB Host mode, 15k pulldown resistors must be connected on both D+ and D-.
* In USB Device mode, pulldown resistors must be disconnected.
*
* @param[in] enable true to connect pulldowns (Host mode), false to disconnect (Device mode)
*/
void usb_utmi_hal_enable_data_pulldowns(bool enable);
#endif // (SOC_USB_UTMI_PHY_NUM > 0)
#ifdef __cplusplus
components/esp_hal_usb/include/hal/usb_wrap_hal.h
+5 -5
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -8,17 +8,17 @@
#include <stdbool.h>
#include "soc/soc_caps.h"
#if (SOC_USB_OTG_PERIPH_NUM > 0)
#if (SOC_USB_FSLS_PHY_NUM > 0)
#include "soc/usb_wrap_struct.h"
#include "hal/usb_wrap_ll.h"
#endif // (SOC_USB_OTG_PERIPH_NUM > 0)
#endif // (SOC_USB_FSLS_PHY_NUM > 0)
#include "hal/usb_wrap_types.h"
#ifdef __cplusplus
extern "C" {
#endif
#if (SOC_USB_OTG_PERIPH_NUM > 0)
#if (SOC_USB_FSLS_PHY_NUM > 0)
/**
* @brief HAL context type of USB WRAP driver
@@ -112,7 +112,7 @@ static inline void usb_wrap_hal_phy_test_mode_set_signals(usb_wrap_hal_context_t
usb_wrap_ll_phy_test_mode_set_signals(hal->dev, vals);
}
#endif // (SOC_USB_OTG_PERIPH_NUM > 0)
#endif // (SOC_USB_FSLS_PHY_NUM > 0)
#ifdef __cplusplus
}
components/esp_hal_usb/include/hal/usb_wrap_types.h
+3 -3
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -13,7 +13,7 @@
extern "C" {
#endif
#if (SOC_USB_OTG_PERIPH_NUM > 0)
#if (SOC_USB_FSLS_PHY_NUM > 0)
/**
* @brief USB WRAP pull up/down resistor override values
@@ -46,7 +46,7 @@ typedef struct {
bool rx_rcv; /**< Differential receive data from D+ and D- lines */
} usb_wrap_test_mode_vals_t;
#endif // (SOC_USB_OTG_PERIPH_NUM > 0)
#endif // (SOC_USB_FSLS_PHY_NUM > 0)
#ifdef __cplusplus
}
components/esp_hal_usb/usb_dwc_hal.c
+3 -3
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@@ -109,9 +109,9 @@ static void set_defaults(usb_dwc_hal_context_t *hal)
hbstlen = 1; //Set AHB burst to INCR to workaround hardware errata
}
#endif // SOC_IS(ESP32S2)
#if SOC_IS(ESP32P4)
#if SOC_IS(ESP32P4) || SOC_IS(ESP32S31)
/*
* ESP32P4-specific initialization: Clear USB PHY suspend state set during system boot.
* ESP32P4/ESP32S31-specific initialization: Clear USB PHY suspend state set during system boot.
*
* During system initialization (see clk_gate_ll.h:periph_ll_clk_gate_set_default), the USB PHY
* is forced into suspend mode before disabling clocks to prevent USB leakage current and ensure
@@ -123,7 +123,7 @@ static void set_defaults(usb_dwc_hal_context_t *hal)
*/
usb_dwc_ll_enable_bvalid_override(hal->dev, false);
usb_dwc_ll_set_stoppclk(hal->dev, false);
#endif // SOC_IS(ESP32P4)
#endif // SOC_IS(ESP32P4) || SOC_IS(ESP32S31)
usb_dwc_ll_gahbcfg_set_hbstlen(hal->dev, hbstlen); //Set AHB burst mode
//GUSBCFG register
usb_dwc_ll_gusbcfg_dis_hnp_cap(hal->dev); //Disable HNP
components/esp_hal_usb/usb_utmi_hal.c
+6 -1
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -23,6 +23,11 @@ void _usb_utmi_hal_init(usb_utmi_hal_context_t *hal)
usb_utmi_ll_configure_ls(hal->dev, true);
}
void usb_utmi_hal_enable_data_pulldowns(bool enable)
{
usb_utmi_ll_enable_data_pulldowns(enable);
}
void _usb_utmi_hal_disable(void)
{
_usb_utmi_ll_enable_bus_clock(false);
components/esp_hal_usb/usb_wrap_hal.c
+1 -3
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@@ -1,11 +1,9 @@
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/soc_caps.h"
#include "hal/usb_wrap_ll.h"
#include "hal/usb_wrap_hal.h"
void _usb_wrap_hal_init(usb_wrap_hal_context_t *hal)
components/esp_hw_support/test_apps/usb_phy/README.md
+2 -2
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@@ -1,4 +1,4 @@
| Supported Targets | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 |
| ----------------- | -------- | -------- | -------- | -------- | --------- |
# USB: PHY sanity checks
components/esp_hw_support/test_apps/usb_phy/main/test_app_main.c
+52 -14
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: CC0-1.0
*/
@@ -8,12 +8,12 @@
#include "unity_test_runner.h"
#include "unity_test_utils_memory.h"
#include "esp_private/usb_phy.h"
#include "hal/usb_wrap_ll.h" // For USB_WRAP_LL_EXT_PHY_SUPPORTED symbol
#include "soc/soc_caps.h" // For SOC_USB_UTMI_PHY_NUM symbol
#include "soc/soc_caps.h"
#include "sdkconfig.h" // For CONFIG_IDF_TARGET_***
#if USB_WRAP_LL_EXT_PHY_SUPPORTED
#define EXT_PHY_SUPPORTED 1
#if (SOC_USB_FSLS_PHY_NUM > 0)
#include "hal/usb_wrap_ll.h"
#define EXT_PHY_SUPPORTED USB_WRAP_LL_EXT_PHY_SUPPORTED
#else
#define EXT_PHY_SUPPORTED 0
#endif
@@ -24,6 +24,18 @@
#define UTMI_PHY_SUPPORTED 0
#endif
#if CONFIG_IDF_TARGET_ESP32S31
#define INT_PHY_ALIASES_UTMI 1
#else
#define INT_PHY_ALIASES_UTMI 0
#endif
#if (SOC_USB_FSLS_PHY_NUM > 0) || INT_PHY_ALIASES_UTMI
#define INT_PHY_SUPPORTED 1
#else
#define INT_PHY_SUPPORTED 0
#endif
void setUp(void)
{
unity_utils_record_free_mem();
@@ -55,12 +67,15 @@ void app_main(void)
}
/**
* Test init and deinit of internal FSLS PHY
* Test init and deinit of the internal PHY target
*
* On UTMI-only targets, the internal PHY target can be mapped to UTMI for
* backward compatibility.
*
* 1. Init + deinit in Host mode
* 2. Init + deinit in Device mode
*/
TEST_CASE("Init internal FSLS PHY", "[phy]")
TEST_CASE("Init internal PHY target", "[phy]")
{
// Host mode
usb_phy_handle_t phy_handle = NULL;
@@ -72,9 +87,14 @@ TEST_CASE("Init internal FSLS PHY", "[phy]")
.ext_io_conf = NULL,
.otg_io_conf = NULL,
};
#if INT_PHY_SUPPORTED
TEST_ASSERT_EQUAL(ESP_OK, usb_new_phy(&phy_config, &phy_handle));
TEST_ASSERT_NOT_NULL(phy_handle);
TEST_ASSERT_EQUAL(ESP_OK, usb_del_phy(phy_handle));
#else
TEST_ASSERT_NOT_EQUAL(ESP_OK, usb_new_phy(&phy_config, &phy_handle));
TEST_ASSERT_NULL(phy_handle);
#endif
// Device mode
usb_phy_handle_t phy_handle_2 = NULL;
@@ -86,9 +106,14 @@ TEST_CASE("Init internal FSLS PHY", "[phy]")
.ext_io_conf = NULL,
.otg_io_conf = NULL,
};
#if INT_PHY_SUPPORTED
TEST_ASSERT_EQUAL(ESP_OK, usb_new_phy(&phy_config_2, &phy_handle_2));
TEST_ASSERT_NOT_NULL(phy_handle_2);
TEST_ASSERT_EQUAL(ESP_OK, usb_del_phy(phy_handle_2));
#else
TEST_ASSERT_NOT_EQUAL(ESP_OK, usb_new_phy(&phy_config_2, &phy_handle_2));
TEST_ASSERT_NULL(phy_handle_2);
#endif
}
/**
@@ -156,10 +181,14 @@ TEST_CASE("Init internal UTMI PHY", "[phy]")
}
/**
* Test init and deinit of all PHYs at the same time multiple times
* Test init and deinit of all available PHY targets multiple times
*/
TEST_CASE("Init all PHYs in a loop", "[phy]")
{
#if !INT_PHY_SUPPORTED
TEST_IGNORE_MESSAGE("Internal PHY target is not supported on this target");
#endif
for (int i = 0; i < 2; i++) {
usb_phy_handle_t phy_handle = NULL;
usb_phy_handle_t phy_handle_2 = NULL;
@@ -174,11 +203,14 @@ TEST_CASE("Init all PHYs in a loop", "[phy]")
TEST_ASSERT_EQUAL(ESP_OK, usb_new_phy(&phy_config, &phy_handle));
TEST_ASSERT_NOT_NULL(phy_handle);
// Our current targets support either UTMI or external PHY
// so if/else suffice here
#if UTMI_PHY_SUPPORTED
// UTMI-only targets can alias the internal PHY target to UTMI, in
// which case a second UTMI allocation must fail because it is the same
// physical PHY instance.
#if UTMI_PHY_SUPPORTED && !INT_PHY_ALIASES_UTMI
phy_config.target = USB_PHY_TARGET_UTMI;
#else
TEST_ASSERT_EQUAL(ESP_OK, usb_new_phy(&phy_config, &phy_handle_2));
TEST_ASSERT_NOT_NULL(phy_handle_2);
#elif EXT_PHY_SUPPORTED
phy_config.target = USB_PHY_TARGET_EXT;
const usb_phy_ext_io_conf_t ext_io_conf = { // Some random values
.vp_io_num = 1,
@@ -191,12 +223,18 @@ TEST_CASE("Init all PHYs in a loop", "[phy]")
.fs_edge_sel_io_num = 1,
};
phy_config.ext_io_conf = &ext_io_conf;
#endif
TEST_ASSERT_EQUAL(ESP_OK, usb_new_phy(&phy_config, &phy_handle_2));
TEST_ASSERT_NOT_NULL(phy_handle_2);
#elif INT_PHY_ALIASES_UTMI
phy_config.target = USB_PHY_TARGET_UTMI;
TEST_ASSERT_NOT_EQUAL(ESP_OK, usb_new_phy(&phy_config, &phy_handle_2));
TEST_ASSERT_NULL(phy_handle_2);
#endif
TEST_ASSERT_EQUAL(ESP_OK, usb_del_phy(phy_handle));
TEST_ASSERT_EQUAL(ESP_OK, usb_del_phy(phy_handle_2));
if (phy_handle_2) {
TEST_ASSERT_EQUAL(ESP_OK, usb_del_phy(phy_handle_2));
}
}
}
components/esp_hw_support/usb_phy/usb_phy.c
+49 -23
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -25,6 +25,12 @@
#include "esp_sleep.h"
#endif
#if (SOC_USB_FSLS_PHY_NUM > 0)
#define USB_PHY_FSLS_EXT_PHY_SUPPORTED USB_WRAP_LL_EXT_PHY_SUPPORTED
#else
#define USB_PHY_FSLS_EXT_PHY_SUPPORTED 0
#endif
static const char *USBPHY_TAG = "usb_phy";
#define USBPHY_NOT_INIT_ERR_STR "USB_PHY is not initialized"
@@ -37,7 +43,9 @@ struct phy_context_t {
usb_phy_status_t status; /**< PHY status */
usb_otg_mode_t otg_mode; /**< USB OTG mode */
usb_phy_ext_io_conf_t *iopins; /**< external PHY I/O pins */
#if (SOC_USB_FSLS_PHY_NUM > 0)
usb_wrap_hal_context_t wrap_hal; /**< USB WRAP HAL context */
#endif
};
typedef struct {
@@ -138,24 +146,15 @@ esp_err_t usb_phy_otg_set_mode(usb_phy_handle_t handle, usb_otg_mode_t mode)
// we support only fixed PHY to USB-DWC mapping:
// USB-DWC2.0 <-> UTMI PHY
// USB-DWC1.1 <-> FSLS PHY
#if (SOC_USB_UTMI_PHY_NUM > 0)
if (handle->target == USB_PHY_TARGET_UTMI) {
// ESP32-P4 v3 changed connection between USB-OTG peripheral and UTMI PHY.
// On v3 the 15k pulldown resistors on D+/D- are no longer controlled by USB-OTG,
// but must be controlled directly by this software driver.
#if CONFIG_IDF_TARGET_ESP32P4 && !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
#include "soc/lp_system_struct.h"
if (mode == USB_OTG_MODE_HOST) {
// Host must connect 15k pulldown resistors on D+ / D-
LP_SYS.hp_usb_otghs_phy_ctrl.hp_utmiotg_dppulldown = 1;
LP_SYS.hp_usb_otghs_phy_ctrl.hp_utmiotg_dmpulldown = 1;
} else {
// Device must not connect any pulldown resistors on D+ / D-
LP_SYS.hp_usb_otghs_phy_ctrl.hp_utmiotg_dppulldown = 0;
LP_SYS.hp_usb_otghs_phy_ctrl.hp_utmiotg_dmpulldown = 0;
}
#endif // !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
// On some targets, the 15k pulldown resistors on D+/D- are not controlled
// by the USB-OTG peripheral, but must be controlled by software.
// Host mode: connect pulldowns; Device mode: disconnect pulldowns.
usb_utmi_hal_enable_data_pulldowns(mode == USB_OTG_MODE_HOST);
return ESP_OK;
}
#endif
const usb_otg_signal_conn_t *otg_sig = usb_dwc_info.controllers[otg11_index].otg_signals;
assert(otg_sig);
@@ -164,6 +163,7 @@ esp_err_t usb_phy_otg_set_mode(usb_phy_handle_t handle, usb_otg_mode_t mode)
gpio_ll_set_input_signal_matrix_source(GPIO_LL_GET_HW(0), otg_sig->bvalid, GPIO_MATRIX_CONST_ZERO_INPUT, false);
gpio_ll_set_input_signal_matrix_source(GPIO_LL_GET_HW(0), otg_sig->vbusvalid, GPIO_MATRIX_CONST_ONE_INPUT, false); // receiving a valid Vbus from host
gpio_ll_set_input_signal_matrix_source(GPIO_LL_GET_HW(0), otg_sig->avalid, GPIO_MATRIX_CONST_ONE_INPUT, false); // HIGH to force USB host mode
#if (SOC_USB_FSLS_PHY_NUM > 0)
if (handle->target == USB_PHY_TARGET_INT) {
// Configure pull resistors for host
usb_wrap_pull_override_vals_t vals = {
@@ -174,6 +174,7 @@ esp_err_t usb_phy_otg_set_mode(usb_phy_handle_t handle, usb_otg_mode_t mode)
};
usb_wrap_hal_phy_enable_pull_override(&handle->wrap_hal, &vals);
}
#endif
} else if (mode == USB_OTG_MODE_DEVICE) {
gpio_ll_set_input_signal_matrix_source(GPIO_LL_GET_HW(0), otg_sig->iddig, GPIO_MATRIX_CONST_ONE_INPUT, false); // connected connector is mini-B side
gpio_ll_set_input_signal_matrix_source(GPIO_LL_GET_HW(0), otg_sig->bvalid, GPIO_MATRIX_CONST_ONE_INPUT, false); // HIGH to force USB device mode
@@ -233,6 +234,18 @@ esp_err_t usb_new_phy(const usb_phy_config_t *config, usb_phy_handle_t *handle_r
}
#endif
#if CONFIG_IDF_TARGET_ESP32S31
/*
* ESP32-S31 exposes only the UTMI PHY to the USB OTG controller.
* Keep backward compatibility with applications that still request
* the legacy internal PHY target by aliasing it to UTMI.
*/
if (config->controller == USB_PHY_CTRL_OTG && phy_target == USB_PHY_TARGET_INT) {
ESP_LOGW(USBPHY_TAG, "Using UTMI PHY instead of requested internal PHY");
phy_target = USB_PHY_TARGET_UTMI;
}
#endif
#if SOC_USB_UTMI_PHY_NO_POWER_OFF_ISO
if (phy_target == USB_PHY_TARGET_UTMI) {
esp_deep_sleep_register_hook(&sleep_usb_suppress_deepsleep_leakage);
@@ -243,7 +256,10 @@ esp_err_t usb_new_phy(const usb_phy_config_t *config, usb_phy_handle_t *handle_r
ESP_RETURN_ON_FALSE(phy_target < USB_PHY_TARGET_MAX, ESP_ERR_INVALID_ARG, USBPHY_TAG, "specified PHY argument is invalid");
ESP_RETURN_ON_FALSE(config->controller < USB_PHY_CTRL_MAX, ESP_ERR_INVALID_ARG, USBPHY_TAG, "specified source argument is invalid");
ESP_RETURN_ON_FALSE(phy_target != USB_PHY_TARGET_EXT || config->ext_io_conf, ESP_ERR_INVALID_ARG, USBPHY_TAG, "ext_io_conf must be provided for ext PHY");
#if !USB_WRAP_LL_EXT_PHY_SUPPORTED
#if !SOC_USB_FSLS_PHY_NUM
ESP_RETURN_ON_FALSE(phy_target != USB_PHY_TARGET_INT, ESP_ERR_NOT_SUPPORTED, USBPHY_TAG, "Internal FSLS PHY not supported on this target");
ESP_RETURN_ON_FALSE(phy_target != USB_PHY_TARGET_EXT, ESP_ERR_NOT_SUPPORTED, USBPHY_TAG, "Ext PHY not supported on this target");
#elif !USB_PHY_FSLS_EXT_PHY_SUPPORTED
ESP_RETURN_ON_FALSE(phy_target != USB_PHY_TARGET_EXT, ESP_ERR_NOT_SUPPORTED, USBPHY_TAG, "Ext PHY not supported on this target");
#endif
#if !SOC_USB_UTMI_PHY_NUM
@@ -276,20 +292,26 @@ esp_err_t usb_new_phy(const usb_phy_config_t *config, usb_phy_handle_t *handle_r
phy_context->controller = config->controller;
phy_context->status = USB_PHY_STATUS_IN_USE;
#if (SOC_USB_FSLS_PHY_NUM > 0)
if (phy_target != USB_PHY_TARGET_UTMI) {
PERIPH_RCC_ATOMIC() {
usb_wrap_hal_init(&phy_context->wrap_hal);
}
} else {
#if (SOC_USB_UTMI_PHY_NUM > 0)
usb_utmi_hal_context_t utmi_hal_context; // Unused for now
PERIPH_RCC_ATOMIC() {
usb_utmi_hal_init(&utmi_hal_context);
}
#endif
if (phy_target == USB_PHY_TARGET_UTMI) {
#if (SOC_USB_UTMI_PHY_NUM > 0)
usb_utmi_hal_context_t utmi_hal_context; // Unused for now
PERIPH_RCC_ATOMIC() {
usb_utmi_hal_init(&utmi_hal_context);
}
#endif
}
#if (SOC_USB_FSLS_PHY_NUM > 0)
}
#endif
if (config->controller == USB_PHY_CTRL_OTG) {
#if USB_WRAP_LL_EXT_PHY_SUPPORTED
#if USB_PHY_FSLS_EXT_PHY_SUPPORTED
usb_wrap_hal_phy_set_external(&phy_context->wrap_hal, (phy_target == USB_PHY_TARGET_EXT));
#endif
}
@@ -345,7 +367,9 @@ static void phy_uninstall(void)
p_phy_ctrl_obj = NULL;
PERIPH_RCC_ATOMIC() {
// Disable USB peripheral without reset the module
#if (SOC_USB_FSLS_PHY_NUM > 0)
usb_wrap_hal_disable();
#endif
#if (SOC_USB_UTMI_PHY_NUM > 0)
usb_utmi_hal_disable();
#endif
@@ -363,10 +387,12 @@ esp_err_t usb_del_phy(usb_phy_handle_t handle)
p_phy_ctrl_obj->ref_count--;
if (handle->target == USB_PHY_TARGET_EXT) {
p_phy_ctrl_obj->external_phy = NULL;
#if (SOC_USB_FSLS_PHY_NUM > 0)
} else if (handle->target == USB_PHY_TARGET_INT) {
// Clear pullup and pulldown loads on D+ / D-, and disable the pads
usb_wrap_hal_phy_disable_pull_override(&handle->wrap_hal);
p_phy_ctrl_obj->fsls_phy = NULL;
#endif
} else { // USB_PHY_TARGET_UTMI
p_phy_ctrl_obj->utmi_phy = NULL;
}
components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
+4
View File
@@ -1159,6 +1159,10 @@ config SOC_USB_OTG_PERIPH_NUM
int
default 1
config SOC_USB_FSLS_PHY_NUM
int
default 1
config SOC_ASRC_SUPPORTED
bool
default y
components/soc/esp32h4/include/soc/soc_caps.h
+1
View File
@@ -543,6 +543,7 @@
/*-------------------------- USB CAPS ----------------------------------------*/
#define SOC_USB_OTG_PERIPH_NUM (1U)
#define SOC_USB_FSLS_PHY_NUM (1U)
/*---------------------------------- ASRC CAPS ----------------------------------*/
#define SOC_ASRC_SUPPORTED (1)
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
+4
View File
@@ -1163,6 +1163,10 @@ config SOC_USB_OTG_PERIPH_NUM
int
default 2
config SOC_USB_FSLS_PHY_NUM
int
default 1
config SOC_USB_UTMI_PHY_NUM
int
default 1
components/soc/esp32p4/include/soc/soc_caps.h
+1
View File
@@ -430,6 +430,7 @@
// USB OTG Caps
#define SOC_USB_OTG_PERIPH_NUM (2U)
#define SOC_USB_FSLS_PHY_NUM (1U)
// USB PHY Caps
#define SOC_USB_UTMI_PHY_NUM (1U)
components/soc/esp32s2/include/soc/Kconfig.soc_caps.in
+4
View File
@@ -707,6 +707,10 @@ config SOC_USB_OTG_PERIPH_NUM
int
default 1
config SOC_USB_FSLS_PHY_NUM
int
default 1
config SOC_SHA_DMA_MAX_BUFFER_SIZE
int
default 3968
components/soc/esp32s2/include/soc/soc_caps.h
+1
View File
@@ -325,6 +325,7 @@
/*-------------------------- USB CAPS ----------------------------------------*/
#define SOC_USB_OTG_PERIPH_NUM (1U)
#define SOC_USB_FSLS_PHY_NUM (1U)
/*--------------------------- SHA CAPS ---------------------------------------*/
/* Max amount of bytes in a single DMA operation is 4095,
components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
+4
View File
@@ -803,6 +803,10 @@ config SOC_USB_OTG_PERIPH_NUM
int
default 1
config SOC_USB_FSLS_PHY_NUM
int
default 1
config SOC_SHA_DMA_MAX_BUFFER_SIZE
int
default 3968
components/soc/esp32s3/include/soc/soc_caps.h
+1
View File
@@ -337,6 +337,7 @@
/*-------------------------- USB CAPS ----------------------------------------*/
#define SOC_USB_OTG_PERIPH_NUM (1U)
#define SOC_USB_FSLS_PHY_NUM (1U)
/*--------------------------- SHA CAPS ---------------------------------------*/
/* Max amount of bytes in a single DMA operation is 4095,
components/soc/esp32s31/include/soc/Kconfig.soc_caps.in
+16
View File
@@ -43,6 +43,10 @@ config SOC_ASYNC_MEMCPY_SUPPORTED
bool
default y
config SOC_USB_OTG_SUPPORTED
bool
default y
config SOC_EFUSE_KEY_PURPOSE_FIELD
bool
default y
@@ -131,6 +135,18 @@ config SOC_REGI2C_SUPPORTED
bool
default y
config SOC_USB_OTG_PERIPH_NUM
int
default 1
config SOC_USB_FSLS_PHY_NUM
int
default 0
config SOC_USB_UTMI_PHY_NUM
int
default 1
config SOC_XTAL_SUPPORT_40M
bool
default y
components/soc/esp32s31/include/soc/soc_caps.h
+6 -1
View File
@@ -44,7 +44,7 @@
#define SOC_ETM_SUPPORTED 1
// #define SOC_PARLIO_SUPPORTED 1 // TODO: [ESP32S31] IDF-14711
#define SOC_ASYNC_MEMCPY_SUPPORTED 1
// #define SOC_USB_OTG_SUPPORTED 1 // TODO: [ESP32S31] IDF-14701
#define SOC_USB_OTG_SUPPORTED 1
// #define SOC_USB_SERIAL_JTAG_SUPPORTED 1 // TODO: [ESP32S31] IDF-14788
// #define SOC_TEMP_SENSOR_SUPPORTED 1 // TODO: [ESP32S31] IDF-14799
// #define SOC_SUPPORTS_SECURE_DL_MODE 1 // TODO: [ESP32S31] IDF-14629
@@ -102,6 +102,11 @@
#define SOC_CORDIC_SUPPORTED 1
#define SOC_REGI2C_SUPPORTED 1
/*-------------------------- USB CAPS ----------------------------------------*/
#define SOC_USB_OTG_PERIPH_NUM (1U)
#define SOC_USB_FSLS_PHY_NUM (0U)
#define SOC_USB_UTMI_PHY_NUM (1U)
/*-------------------------- XTAL CAPS ---------------------------------------*/
#define SOC_XTAL_SUPPORT_40M 1
components/soc/esp32s31/include/soc/usb_dwc_struct.h
+1378
View File
File diff suppressed because it is too large Load Diff
components/soc/esp32s31/ld/esp32s31.peripherals.ld
+1
View File
@@ -19,6 +19,7 @@ PROVIDE ( RMTMEM = 0x20355800 );
PROVIDE ( BITSCRAMBLER = 0x20356000 );
PROVIDE ( ASRC = 0x20357000 );
PROVIDE ( CNNT_SYS_REG = 0x20359000 );
PROVIDE ( USB_UTMI = 0x20380000 );
PROVIDE ( MCPWM0 = 0x20381000 );
PROVIDE ( MCPWM1 = 0x20382000 );
PROVIDE ( MCPWM2 = 0x20383000 );
components/soc/esp32s31/register/soc/usb_utmi_struct.h
+229
View File
@@ -0,0 +1,229 @@
/*
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* Following register description is taken from
* U2OPHYT40LL USB 2.0 OTG PHY specification v2.0
*/
typedef union {
struct {
/** clk_gate_rx : R/W; bitpos: [0]; default 2'b0;
* Clock Gating Control Signal for Rx.
* 2'b0 Lower power consumption
* 2'b1 Lowest power consumption mode
* 2'b2 Normal power consumption mode
*/
uint32_t clk_gate_rx: 2;
/** clk_gate_tx : R/W; bitpos: [2]; default: 1'b0;
* Clock Gating Control Signal for Rx.
* 1'b0 Low power consumption mode
* 1'b1 Normal power consumption mode
*/
uint32_t clk_gate_tx: 1;
/** adj_res_fs : Reserved; bitpos: [3]; default: 0;
* Fine tune the 45ohm termination resistor (FS)
* Reserved
*/
uint32_t adj_res_fs: 2;
/** adj_res_hs : R/W; bitpos: [5]; default: 3'b100;
* Fine tune the 45ohm termination resistor (HS)
* 3'b000 40 Ohm
* 3'b100 45 Ohm
* 3'b110 50 Ohm
*/
uint32_t adj_res_hs: 3;
uint32_t reserved_8: 24;
};
uint32_t val;
} usb_utmi_fc_00_reg_t;
typedef union {
struct {
/** adj_vref_sq : R/W; bitpos: [0]; default: 4'b0010;
* Squelch detection threshold voltage control bits
* 4'b0000 92 mV
* 4'b0010 124 mV
* 4'b0011 152 mV
*/
uint32_t adj_vref_sq: 4;
/** adj_pw_hs : R/W; bitpos: [4]; default: 4'b1111;
* Super power saving with reduced output swing mode control bits (for HS mode only)
* 4'b0001 100 mV output swing
* 4'b0011 200 mV output swing
* 4'b0111 300 mV output swing
* 4'b1111 400 mV output swing
*/
uint32_t adj_pw_hs: 4;
uint32_t reserved_8: 24;
};
uint32_t val;
} usb_utmi_fc_01_reg_t;
typedef union {
struct {
/** adj_iref_res : R/W; bitpos: [0]; default: 4'b0111
* Internal bias current adjustment control bits
* 4'b0000 125 uA
* 4'b0111 100 uA
* 4'b1111 78 uA
*/
uint32_t adj_iref_res: 4;
/** adj_vsw_hs : R/W; bitpos: [4]; default: 3'b100
* Output eye shape adjustment control bits
* 3'b000 320 mV
* 3'b100 400 mV
* 3'b111 460 mV
*/
uint32_t adj_vsw_hs: 3;
uint32_t reserved_7: 25;
};
uint32_t val;
} usb_utmi_fc_02_reg_t;
typedef union {
struct {
/** adj_pll : R/W; bitpos: [0]; default: 4'b0101
* PLL adjustment signal
*/
uint32_t adj_pll: 4;
/** adj_osc : R/W; bitpos: [4]; default: 3'b000
* TX Clock phase adjust signal
*/
uint32_t adj_txclk_phase: 3;
uint32_t reserved_7: 25;
};
uint32_t val;
} usb_utmi_fc_03_reg_t;
typedef union {
struct {
/** test_sel : R/W; bitpos: [0]; default: 8'b0
* The PHY has test_sel register here, which normally drives DTO (Digital Test Output) signal.
* In our implementation output of this register is left floating and DTO is driven from Probe module.
* Thus writing to this register has no effect and is renamed to 'reserved'
*/
uint32_t reserved: 8;
uint32_t reserved_8: 24;
};
uint32_t val;
} usb_utmi_fc_04_reg_t;
typedef union {
struct {
/** rxgap_fix_en : R/W; bitpos: [0]; default: 1'b1
* RXGAP fix enable
*/
uint32_t rxgap_fix_en: 1;
/** counter_sel : R/W; bitpos: [1]; default: 1'b0
* SIE_input sample enable
*/
uint32_t counter_sel: 1;
/** clk_sel : R/W; bitpos: [2]; default: 1'b0
* CLK60_30 source select
*/
uint32_t clk_sel: 1;
/** phy_mode_sel : R/W; bitpos: [3]; default: 1'b0
* PHY MODE select
*/
uint32_t phy_mode_sel: 1;
/** uni_bidi_i : R/W; bitpos: [4]; default: 1'b0
* UNI_BIDI signal
*/
uint32_t uni_bidi_i: 1;
/** short_5v : R/W; bitpos: [5]; default: 1'b0
* SHORT_5V signal
*/
uint32_t short_5v: 1;
/** short_5v_enable : R/W; bitpos: [6]; default: 1'b1
* SHORT_5V_ENABLE signal
*/
uint32_t short_5v_enable: 1;
/** usable_en : R/W; bitpos: [7]; default: 1'b1
* compare_begin delay time select
*/
uint32_t usable_en: 1;
uint32_t reserved_8: 24;
};
uint32_t val;
} usb_utmi_fc_05_reg_t;
typedef union {
struct {
/** ls_par_en : R/W; bitpos: [0]; default: 1'b0
* LS mode with parallel enable
*/
uint32_t ls_par_en: 1;
/** det_fseop_en : R/W; bitpos: [1]; default: 1'b0
* FS EOP detect enable
*/
uint32_t det_fseop_en: 1;
/** pre_hphy_lsie : R/W; bitpos: [2]; default: 1'b0
* Dis_preamble enable
*/
uint32_t pre_hphy_lsie: 1;
/** ls_kpalv_en : R/W; bitpos: [3]; default: 1'b0
* LS mode keep alive enable
*/
uint32_t ls_kpalv_en: 1;
/** hs_tx2rx_dly_cnt_sel : R/W; bitpos: [4]; default: 3'b100
* PHY High-SPeed bus turn-around time select
*/
uint32_t hs_tx2rx_dly_cnt_sel: 3;
uint32_t reserved_7: 25;
};
uint32_t val;
} usb_utmi_fc_06_reg_t;
typedef union {
struct {
/** cnt_num : R/W; bitpos: [1:0]; default: 2'b00
* 3 ms counter select
* 00: 392us (Default)
* 01: 682us
* 10: 1.36ms
* 11: 2.72ms
*/
uint32_t cnt_num: 2;
/** clk480_sel : R/W; bitpos: [2]; default: 1'b0
* CLK_480 output time select
* 0: CLK_480 is valid after a delay time when PLL is locked
* 1: CLK_480 is valid immediately after PLL is locked
*/
uint32_t clk480_sel: 1;
uint32_t reserved_3: 29;
};
uint32_t val;
} usb_utmi_fc_07_reg_t;
typedef struct usb_utmi_dev_t {
volatile usb_utmi_fc_00_reg_t fc_00;
volatile usb_utmi_fc_01_reg_t fc_01;
volatile usb_utmi_fc_02_reg_t fc_02;
volatile usb_utmi_fc_03_reg_t fc_03;
volatile usb_utmi_fc_04_reg_t fc_04;
volatile usb_utmi_fc_05_reg_t fc_05;
volatile usb_utmi_fc_06_reg_t fc_06;
volatile usb_utmi_fc_07_reg_t fc_07;
} usb_utmi_dev_t;
extern usb_utmi_dev_t USB_UTMI;
#ifndef __cplusplus
_Static_assert(sizeof(usb_utmi_dev_t) == 0x20, "Invalid size of usb_utmi_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif
docs/en/api-guides/index.rst
+2 -2
View File
@@ -21,7 +21,7 @@ API Guides
core_dump
current-consumption-measurement-modules
:ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB: deep-sleep-stub
:SOC_USB_OTG_SUPPORTED and not esp32h4: dfu
:SOC_USB_OTG_SUPPORTED and not esp32h4 and not esp32s31: dfu
error-handling
:SOC_WIFI_MESH_SUPPORT: esp-wifi-mesh
:SOC_SPIRAM_SUPPORTED: external-ram
@@ -46,7 +46,7 @@ API Guides
tools/index
unit-tests
host-apps
:SOC_USB_OTG_SUPPORTED and not esp32p4 and not esp32h4: usb-otg-console
:SOC_USB_OTG_SUPPORTED and not esp32p4 and not esp32h4 and not esp32s31: usb-otg-console
:SOC_USB_SERIAL_JTAG_SUPPORTED: usb-serial-jtag-console
:SOC_WIFI_SUPPORTED: wifi-driver/index
:SOC_WIFI_SUPPORTED: wifi-security
docs/zh_CN/api-guides/index.rst
+2 -2
View File
@@ -21,7 +21,7 @@ API 指南
core_dump
current-consumption-measurement-modules
:ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB: deep-sleep-stub
:SOC_USB_OTG_SUPPORTED and not esp32h4: dfu
:SOC_USB_OTG_SUPPORTED and not esp32h4 and not esp32s31: dfu
error-handling
:SOC_WIFI_MESH_SUPPORT: esp-wifi-mesh
:SOC_SPIRAM_SUPPORTED: external-ram
@@ -46,7 +46,7 @@ API 指南
tools/index
unit-tests
host-apps
:SOC_USB_OTG_SUPPORTED and not esp32p4 and not esp32h4: usb-otg-console
:SOC_USB_OTG_SUPPORTED and not esp32p4 and not esp32h4 and not esp32s31: usb-otg-console
:SOC_USB_SERIAL_JTAG_SUPPORTED: usb-serial-jtag-console
:SOC_WIFI_SUPPORTED: wifi-driver/index
:SOC_WIFI_SUPPORTED: wifi-security
examples/peripherals/.build-test-rules.yml
+12 -6
View File
@@ -183,9 +183,9 @@ examples/peripherals/i2s/i2s_advance/i2s_usb:
- if: SOC_I2S_SUPPORTED != 1
- if: SOC_I2C_SUPPORTED != 1
- if: SOC_USB_OTG_SUPPORTED != 1
- if: IDF_TARGET == "esp32h4"
- if: IDF_TARGET in ["esp32h4", "esp32s31"]
temporary: true
reason: usb_device_uac does not support esp32h4
reason: usb_device_uac does not support esp32h4 or esp32s31
depends_components:
- esp_driver_i2s
- esp_driver_dma
@@ -782,6 +782,9 @@ examples/peripherals/uart/uart_echo_rs485:
examples/peripherals/usb/device:
disable:
- if: SOC_USB_OTG_SUPPORTED != 1
- if: IDF_TARGET == "esp32s31"
temporary: true
reason: USB device examples do not support esp32s31 yet
disable_test:
- if: IDF_TARGET not in ["esp32s2", "esp32p4"]
temporary: true
@@ -796,9 +799,9 @@ examples/peripherals/usb/device:
examples/peripherals/usb/device/cherryusb_serial_device:
disable:
- if: (IDF_TARGET == "esp32h4") or (SOC_USB_OTG_SUPPORTED != 1)
- if: (IDF_TARGET in ["esp32h4", "esp32s31"]) or (SOC_USB_OTG_SUPPORTED != 1)
temporary: true
reason: CherryUSB does not support esp32h4
reason: CherryUSB does not support esp32h4 or esp32s31
examples/peripherals/usb/device/tusb_ncm:
disable:
@@ -816,6 +819,9 @@ examples/peripherals/usb/device/tusb_ncm:
examples/peripherals/usb/host:
disable:
- if: SOC_USB_OTG_SUPPORTED != 1
- if: IDF_TARGET == "esp32s31"
temporary: true
reason: USB host examples do not support esp32s31 yet
disable_test:
- if: IDF_TARGET not in ["esp32s3", "esp32p4"]
temporary: true
@@ -832,9 +838,9 @@ examples/peripherals/usb/host:
examples/peripherals/usb/host/cherryusb_host:
disable:
- if: (IDF_TARGET == "esp32h4") or (SOC_USB_OTG_SUPPORTED != 1)
- if: (IDF_TARGET in ["esp32h4", "esp32s31"]) or (SOC_USB_OTG_SUPPORTED != 1)
temporary: true
reason: CherryUSB does not support esp32h4
reason: CherryUSB does not support esp32h4 or esp32s31
examples/peripherals/usb_serial_jtag/usb_serial_jtag_echo:
disable: