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change(parlio_tx): use shift edge instead sample edge

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Made-with: Cursor
This commit is contained in:
Chen Jichang
2026-03-16 11:32:32 +08:00
committed by morris
parent 55e88b4e27
commit 107548e016
8 changed files with 40 additions and 31 deletions
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components/driver/parlio/include/driver/parlio_tx.h
+5 -2
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -32,7 +32,10 @@ typedef struct {
Note that, the valid signal will always occupy the MSB data bit */
size_t trans_queue_depth; /*!< Depth of internal transaction queue */
size_t max_transfer_size; /*!< Maximum transfer size in one transaction, in bytes. This decides the number of DMA nodes will be used for each transaction */
parlio_sample_edge_t sample_edge; /*!< Parallel IO sample edge */
union {
parlio_sample_edge_t sample_edge __attribute__((deprecated("Please use `shift_edge` instead"))); /*!< Parallel IO sample edge */
parlio_shift_edge_t shift_edge; /*!< Parallel IO Tx shift edge */
};
parlio_bit_pack_order_t bit_pack_order; /*!< Set the order of packing the bits into bytes (only works when `data_width` < 8) */
struct {
uint32_t clk_gate_en: 1; /*!< Enable TX clock gating,
components/driver/parlio/parlio_tx.c
+3 -3
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -369,8 +369,8 @@ esp_err_t parlio_new_tx_unit(const parlio_tx_unit_config_t *config, parlio_tx_un
if (data_width < 8) {
parlio_ll_tx_set_bit_pack_order(hal->regs, config->bit_pack_order);
}
// set sample clock edge
parlio_ll_tx_set_sample_clock_edge(hal->regs, config->sample_edge);
parlio_ll_tx_set_shift_clock_edge(hal->regs, config->shift_edge);
#if SOC_PARLIO_TX_SIZE_BY_DMA
// Always use DATA LEN EOF as the Parlio TX EOF
components/driver/test_apps/parlio/main/test_parlio_tx.c
+5 -5
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -100,7 +100,7 @@ TEST_CASE("parallel_tx_unit_trans_done_event", "[parlio_tx]")
.trans_queue_depth = 8,
.max_transfer_size = 128,
.bit_pack_order = PARLIO_BIT_PACK_ORDER_LSB,
.sample_edge = PARLIO_SAMPLE_EDGE_POS,
.shift_edge = PARLIO_SHIFT_EDGE_POS,
};
TEST_ESP_OK(parlio_new_tx_unit(&config, &tx_unit));
TEST_ESP_OK(parlio_tx_unit_enable(tx_unit));
@@ -152,7 +152,7 @@ TEST_CASE("parallel_tx_unit_enable_disable", "[parlio_tx]")
.trans_queue_depth = 64,
.max_transfer_size = 256,
.bit_pack_order = PARLIO_BIT_PACK_ORDER_LSB,
.sample_edge = PARLIO_SAMPLE_EDGE_POS,
.shift_edge = PARLIO_SHIFT_EDGE_POS,
};
TEST_ESP_OK(parlio_new_tx_unit(&config, &tx_unit));
TEST_ESP_OK(parlio_tx_unit_enable(tx_unit));
@@ -206,7 +206,7 @@ TEST_CASE("parallel_tx_unit_idle_value", "[parlio_tx]")
.trans_queue_depth = 4,
.max_transfer_size = 64,
.bit_pack_order = PARLIO_BIT_PACK_ORDER_LSB,
.sample_edge = PARLIO_SAMPLE_EDGE_POS,
.shift_edge = PARLIO_SHIFT_EDGE_POS,
.flags.io_loop_back = 1, // enable loop back by GPIO matrix, so that we can read the level of the data line by gpio driver
};
TEST_ESP_OK(parlio_new_tx_unit(&config, &tx_unit));
@@ -250,7 +250,7 @@ TEST_CASE("parallel_tx_clock_gating", "[paralio_tx]")
.trans_queue_depth = 4,
.max_transfer_size = 64,
.bit_pack_order = PARLIO_BIT_PACK_ORDER_MSB,
.sample_edge = PARLIO_SAMPLE_EDGE_POS,
.shift_edge = PARLIO_SHIFT_EDGE_POS,
.flags.clk_gate_en = true, // enable clock gating, controlled by the level of TEST_DATA7_GPIO
.flags.io_loop_back = true, // for reading the level of the clock line in IDLE state
};
components/hal/esp32c6/include/hal/parlio_ll.h
+4 -4
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -476,12 +476,12 @@ static inline void parlio_ll_tx_treat_msb_as_valid(parl_io_dev_t *dev, bool en)
}
/**
* @brief Set the sample clock edge
* @brief Set the shift clock edge
*
* @param dev Parallel IO register base address
* @param edge Sample clock edge
* @param edge Shift clock edge
*/
static inline void parlio_ll_tx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge)
static inline void parlio_ll_tx_set_shift_clock_edge(parl_io_dev_t *dev, parlio_shift_edge_t edge)
{
dev->tx_cfg0.tx_smp_edge_sel = edge;
}
components/hal/esp32h2/include/hal/parlio_ll.h
+6 -7
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -483,16 +483,15 @@ static inline void parlio_ll_tx_treat_msb_as_valid(parl_io_dev_t *dev, bool en)
}
/**
* @brief Set the sample clock edge
* @brief Set the shift clock edge
*
* @param dev Parallel IO register base address
* @param edge Sample clock edge
* @param edge Shift clock edge
*/
static inline void parlio_ll_tx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge)
static inline void parlio_ll_tx_set_shift_clock_edge(parl_io_dev_t *dev, parlio_shift_edge_t edge)
{
bool invert = edge == PARLIO_SAMPLE_EDGE_NEG;
dev->tx_clk_cfg.tx_clk_i_inv = invert;
dev->tx_clk_cfg.tx_clk_o_inv = invert;
dev->tx_clk_cfg.tx_clk_i_inv = edge;
dev->tx_clk_cfg.tx_clk_o_inv = edge;
}
/**
components/hal/esp32p4/include/hal/parlio_ll.h
+6 -7
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -626,16 +626,15 @@ static inline void parlio_ll_tx_treat_msb_as_valid(parl_io_dev_t *dev, bool en)
}
/**
* @brief Set the sample clock edge
* @brief Set the shift clock edge
*
* @param dev Parallel IO register base address
* @param edge Sample clock edge
* @param edge Shift clock edge
*/
static inline void parlio_ll_tx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge)
static inline void parlio_ll_tx_set_shift_clock_edge(parl_io_dev_t *dev, parlio_shift_edge_t edge)
{
bool invert = edge == PARLIO_SAMPLE_EDGE_NEG;
dev->tx_clk_cfg.tx_clk_i_inv = invert;
dev->tx_clk_cfg.tx_clk_o_inv = invert;
dev->tx_clk_cfg.tx_clk_i_inv = edge;
dev->tx_clk_cfg.tx_clk_o_inv = edge;
}
/**
components/hal/include/hal/parlio_types.h
+10 -2
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -16,13 +16,21 @@ extern "C" {
#endif
/**
* @brief Parallel IO sample edge
* @brief Parallel IO Rx sample edge
*/
typedef enum {
PARLIO_SAMPLE_EDGE_NEG, /*!< Sample data on falling edge of clock */
PARLIO_SAMPLE_EDGE_POS, /*!< Sample data on rising edge of clock */
} parlio_sample_edge_t;
/**
* @brief Parallel IO Tx shift edge
*/
typedef enum {
PARLIO_SHIFT_EDGE_POS, /*!< Shift data on rising edge of clock */
PARLIO_SHIFT_EDGE_NEG, /*!< Shift data on falling edge of clock */
} parlio_shift_edge_t;
/**
* @brief Parallel IO bit packing order
*
examples/peripherals/parlio/simple_rgb_led_matrix/main/rgb_led_matrix_example_main.c
+1 -1
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@@ -145,7 +145,7 @@ void app_main(void)
.output_clk_freq_hz = EXAMPLE_LED_MATRIX_PIXEL_CLOCK_HZ,
.trans_queue_depth = 32,
.max_transfer_size = EXAMPLE_LED_MATRIX_H_RES * sizeof(lv_color_t) * 2, // 2 lines as the maximum transfer size
.sample_edge = PARLIO_SAMPLE_EDGE_POS,
.shift_edge = PARLIO_SHIFT_EDGE_NEG,
};
ESP_ERROR_CHECK(parlio_new_tx_unit(&config, &tx_unit));
ESP_ERROR_CHECK(parlio_tx_unit_enable(tx_unit));