Merge branch 'change/esp_idf_flash_dpd_in_safe' into 'master'

Change: place flash dpd code in iram safe and add restart cases when rtc_clk iram opt

See merge request espressif/esp-idf!45311

components/esp_hw_support/Kconfig

@@ -226,9 +226,6 @@ menu "Hardware Settings"
 
         config ESP_SLEEP_SET_FLASH_DPD
             bool "Set SPI flash to deep power-down mode in light sleep"
-            select PM_SLP_IRAM_OPT
-            select ESP_PERIPH_CTRL_FUNC_IN_IRAM
-            select ESP_REGI2C_CTRL_FUNC_IN_IRAM
             depends on (!APP_BUILD_TYPE_PURE_RAM_APP && !ESP_SLEEP_POWER_DOWN_FLASH && !SPI_FLASH_ROM_IMPL)
             default y if (IDF_TARGET_ESP32H4 || IDF_TARGET_ESP32H21)
             default y if (IDF_TARGET_ESP32P4 && ESP32P4_SELECTS_REV_LESS_V3)

components/esp_hw_support/port/esp32h4/rtc_clk.c

@@ -169,7 +169,7 @@ static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq)
  * Must satisfy: cpu_freq = XTAL_FREQ / div.
  * Does not disable the PLL.
  */
-static void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
+FORCE_IRAM_ATTR static void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
 {
     // let f_cpu = f_ahb
     clk_ll_ahb_set_divider(1);

components/esp_hw_support/sleep_modes.c

@@ -994,6 +994,12 @@ static esp_err_t FORCE_IRAM_ATTR esp_sleep_start_safe(uint32_t sleep_flags, uint
 #endif
 #endif // !SOC_MSPI_HAS_INDEPENT_IOMUX
         }
+#endif
+#if CONFIG_ESP_SLEEP_SET_FLASH_DPD
+        if (sleep_flags & RTC_SLEEP_FLASH_DPD) {
+            //Release Flash out from deep powerdown mode
+            spi_flash_enable_deep_power_down_mode(false);
+        }
 #endif
         /* Cache Resume 1: Resume cache for continue running*/
         resume_cache();
@@ -1406,12 +1412,6 @@ static SLEEP_FN_ATTR esp_err_t esp_light_sleep_inner(uint32_t sleep_flags, uint3
         // Wait for the flash chip to start up
         esp_rom_delay_us(flash_enable_time_us);
     } else {
-#if CONFIG_ESP_SLEEP_SET_FLASH_DPD
-        if (sleep_flags & RTC_SLEEP_FLASH_DPD) {
-            //Release Flash out from deep powerdown mode
-            spi_flash_enable_deep_power_down_mode(false);
-        }
-#endif
     }
 
 #if CONFIG_ESP_SLEEP_CACHE_SAFE_ASSERTION

components/esp_hw_support/test_apps/rtc_clk/main/test_rtc_clk.c

@@ -484,3 +484,33 @@ TEST_CASE("Output 8M clock to GPIO25", "[ignore]")
     pull_out_clk(RTC_IO_DEBUG_SEL0_8M);
 }
 #endif
+
+#if !CONFIG_RTC_CLK_FUNC_IN_IRAM
+static void do_restart(void)
+{
+    esp_restart();
+}
+
+#if CONFIG_FREERTOS_NUMBER_OF_CORES > 1
+static void do_restart_from_app_cpu(void)
+{
+    xTaskCreatePinnedToCore((TaskFunction_t) &do_restart, "restart", 2048, NULL, 5, NULL, 1);
+    vTaskDelay(2);
+}
+#endif
+
+static void check_reset_reason_sw(void)
+{
+    TEST_ASSERT_EQUAL(ESP_RST_SW, esp_reset_reason());
+}
+
+TEST_CASE_MULTIPLE_STAGES("test rtc_clk in flash after restart", "[rtc_clk]",
+                          do_restart,
+                          check_reset_reason_sw);
+
+#if CONFIG_FREERTOS_NUMBER_OF_CORES > 1
+TEST_CASE_MULTIPLE_STAGES("test rtc_clk in flash after restart from APP CPU", "[rtc_clk]",
+                          do_restart_from_app_cpu,
+                          check_reset_reason_sw);
+#endif
+#endif

components/esp_hw_support/test_apps/rtc_clk/pytest_rtc_clk.py

@@ -1,4 +1,4 @@
-# SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
+# SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
 # SPDX-License-Identifier: CC0-1.0
 
 import pytest
@@ -33,3 +33,21 @@ def test_rtc_no_xtal32k(dut: IdfDut) -> None:
 @idf_parametrize('target', soc_filtered_targets('SOC_CLK_TREE_SUPPORTED == 1'), indirect=['target'])
 def test_rtc_calib_compensation_across_dslp(case_tester: CaseTester) -> None:
     case_tester.run_all_multi_stage_cases()
+
+
+@pytest.mark.flash_suspend
+@pytest.mark.temp_skip_ci(targets=['esp32h2'], reason='flash clock lose in startup')  # TODO [ESP32H2]: IDF-15212
+@pytest.mark.parametrize(
+    'config',
+    [
+        'rtc_clk_flash',
+    ],
+    indirect=True,
+)
+@idf_parametrize(
+    'target',
+    soc_filtered_targets('SOC_CLK_TREE_SUPPORTED == 1 and IDF_TARGET not in ["esp32", "esp32s2"]'),
+    indirect=['target'],
+)
+def test_rtc_clk_flash(case_tester: CaseTester) -> None:
+    case_tester.run_all_multi_stage_cases()

components/esp_hw_support/test_apps/rtc_clk/sdkconfig.ci.rtc_clk_flash

@@ -0,0 +1,4 @@
+CONFIG_RTC_CLK_FUNC_IN_IRAM=n
+CONFIG_SPI_FLASH_AUTO_SUSPEND=y
+# Now the runners are massively using xmc-c chips, to be removed when xmc-d goes massive production.
+CONFIG_SPI_FLASH_FORCE_ENABLE_XMC_C_SUSPEND=y

components/esp_system/test_apps/esp_system_unity_tests/sdkconfig.ci.default

@@ -2,3 +2,6 @@
 # Used for testing stack smashing protection
 CONFIG_COMPILER_STACK_CHECK=y
 CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP=y
+CONFIG_ESP_PERIPH_CTRL_FUNC_IN_IRAM=n
+CONFIG_RTC_CLK_FUNC_IN_IRAM=n
+CONFIG_RTC_TIME_FUNC_IN_IRAM=n