espressif/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2026-04-27 19:13:21 +00:00
Code Issues Packages Projects Releases Wiki Activity

refactor(spi_flash): move internal types to private headers and refactor initialization

Browse Source 
This commit refactors the SPI flash component to improve encapsulation and
modularity by moving internal types and functions to private headers, and
reorganizing initialization code.

Key changes:

1. Move PSRAM frequency constraint macro from soc_caps.h to mspi_ll.h
   - Rename SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED to
     MSPI_TIMING_LL_PSRAM_FREQ_AXI_CONSTRAINED
   - Move macro definition to chip-specific mspi_ll.h files (C5, C61, H4, P4, S31)
   - Update usage in clk_utils.c and esp_flash_spi_init.c
   - Remove old macro from all soc_caps.h files

2. Move internal types to private headers
   - Move esp_flash_t structure to esp_private/esp_flash_types.h
   - Move esp_flash_os_functions_t to esp_private/spi_flash_os.h
   - Update all internal files to include private headers
   - Keep forward declarations in public esp_flash.h

3. Move chip driver header to internal directory
   - Move spi_flash_chip_driver.h to esp_flash_port/spi_flash_chip_driver.h
   - Update all references to use new path
   - Add esp_private/esp_flash_types.h include to the moved header

4. Refactor initialization functions
   - Move init_flash from esp_system/startup_funcs.c to
     spi_flash/esp_flash_spi_init.c
   - Create new init_pm_flash_freq_limit function in startup_funcs.c
     to call esp_pm_flash_freq_limit_init() conditionally
   - Update system_init_fn.txt with new function locations

5. Improve API encapsulation
   - Replace direct access to esp_flash_t->size in
     esp_partition_register_external() with esp_flash_get_size() API
   - Move esp_flash_is_quad_mode from inline function to regular function
     in esp_flash_api.c

6. Update component dependencies
   - Add esp_driver_gpio to spi_flash component PRIV_REQUIRES
   - Remove unused includes and clean up header dependencies

These changes improve code organization by clearly separating public APIs
from internal implementation details, making the codebase more maintainable
and reducing the risk of breaking changes to internal structures.
This commit is contained in:
Xiao Xufeng
2025-12-18 03:50:58 +08:00
parent 7c1e88e3d4
commit 170061e971
40 changed files with 201 additions and 183 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/esp_hal_mspi/esp32c5/include/hal/mspi_ll.h
+3
View File
@@ -38,6 +38,9 @@ extern "C" {
#define MSPI_LL_CORE_CLOCK_120_MHZ 120
#define MSPI_TIMING_LL_CORE_CLOCK_MHZ_DEFAULT MSPI_LL_CORE_CLOCK_80_MHZ
// PSRAM frequency should be constrained by AXI frequency to avoid FIFO underflow.
#define MSPI_TIMING_LL_PSRAM_FREQ_AXI_CONSTRAINED 1
/*---------------------------------------------------------------
MSPI
---------------------------------------------------------------*/
components/esp_hal_mspi/esp32c61/include/hal/mspi_ll.h
+3
View File
@@ -38,6 +38,9 @@ extern "C" {
#define MSPI_LL_CORE_CLOCK_120_MHZ 120
#define MSPI_TIMING_LL_CORE_CLOCK_MHZ_DEFAULT MSPI_LL_CORE_CLOCK_80_MHZ
// PSRAM frequency should be constrained by AXI frequency to avoid FIFO underflow.
#define MSPI_TIMING_LL_PSRAM_FREQ_AXI_CONSTRAINED 1
/************************** MSPI pll clock configurations **************************/
/*
components/esp_hal_mspi/esp32h4/include/hal/mspi_ll.h
+3
View File
@@ -32,6 +32,9 @@
extern "C" {
#endif
// PSRAM frequency should be constrained by AXI frequency to avoid FIFO underflow.
#define MSPI_TIMING_LL_PSRAM_FREQ_AXI_CONSTRAINED 1
/************************** MSPI pll clock configurations **************************/
/*
* @brief Select FLASH clock source
components/esp_hal_mspi/esp32p4/include/hal/mspi_ll.h
+3
View File
@@ -46,6 +46,9 @@ extern "C" {
#define MSPI_TIMING_LL_MSPI_ID_0 0
#define MSPI_TIMING_LL_MSPI_ID_1 1
// PSRAM frequency should be constrained by AXI frequency to avoid FIFO underflow.
#define MSPI_TIMING_LL_PSRAM_FREQ_AXI_CONSTRAINED 1
#define MSPI_TIMING_LL_HP_FLASH_CORE_CLK_DIV 4
#define MSPI_TIMING_LL_LP_FLASH_CORE_CLK_DIV 6
#define MSPI_TIMING_LL_FLASH_FDUMMY_RIN_SUPPORTED 1
components/esp_hw_support/clk_utils.c
+2 -3
View File
@@ -11,7 +11,6 @@
#include "sdkconfig.h"
#include "esp_check.h"
#include "esp_log.h"
#include "soc/soc_caps.h"
#include "soc/rtc.h"
#include "hal/mspi_ll.h"
#include "hal/clk_tree_ll.h"
@@ -36,7 +35,7 @@ void esp_clk_utils_mspi_speed_mode_sync_before_cpu_freq_switching(uint32_t targe
if (target_cpu_src_freq <= clk_ll_xtal_load_freq_mhz()) {
mspi_timing_change_speed_mode_cache_safe(true);
}
#elif SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED && CONFIG_SPIRAM
#elif MSPI_TIMING_LL_PSRAM_FREQ_AXI_CONSTRAINED && CONFIG_SPIRAM
/* On chips with AXI bus, currently there is a restriction that AXI frequency (usually equals to a portion of CPU
* frequency) needs to be greater than or equal to MSPI PSRAM frequency to avoid writing MSPI FIFO overflow.
*/
@@ -58,7 +57,7 @@ void esp_clk_utils_mspi_speed_mode_sync_after_cpu_freq_switching(uint32_t target
if (target_cpu_src_freq > clk_ll_xtal_load_freq_mhz()) {
mspi_timing_change_speed_mode_cache_safe(false);
}
#elif SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED && CONFIG_SPIRAM
#elif MSPI_TIMING_LL_PSRAM_FREQ_AXI_CONSTRAINED && CONFIG_SPIRAM
/* On chips with AXI bus, currently there is a restriction that AXI frequency (usually equals to a portion of CPU
* frequency) needs to be greater than or equal to MSPI PSRAM frequency to avoid writing MSPI FIFO overflow.
*/
components/esp_partition/partition.c
+6 -1
View File
@@ -478,7 +478,12 @@ esp_err_t esp_partition_register_external(esp_flash_t *flash_chip, size_t offset
if (flash_chip == NULL) {
flash_chip = esp_flash_default_chip;
}
if (offset + size > flash_chip->size) {
uint32_t flash_size = 0;
esp_err_t ret = esp_flash_get_size(flash_chip, &flash_size);
if (ret != ESP_OK) {
return ret;
}
if (offset + size > flash_size) {
return ESP_ERR_INVALID_SIZE;
}
#endif // CONFIG_IDF_TARGET_LINUX
components/esp_system/startup_funcs.c
+10 -25
View File
@@ -16,16 +16,16 @@
#include "esp_log.h"
#include "esp_private/cache_utils.h"
#include "spi_flash_mmap.h"
#include "esp_flash_internal.h"
#include "esp_newlib.h"
#include "esp_xt_wdt.h"
#include "esp_cpu.h"
#include "esp_private/startup_internal.h"
#include "esp_private/pm_impl.h"
#include "freertos/portmacro.h"
#include "soc/soc_caps.h"
#include "hal/wdt_hal.h"
#include "hal/uart_types.h"
#include "hal/uart_ll.h"
#include "freertos/FreeRTOS.h"
#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE
#include "private/esp_coexist_internal.h"
@@ -104,29 +104,6 @@ ESP_SYSTEM_INIT_FN(init_newlib_time, CORE, BIT(0), 105)
return ESP_OK;
}
#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
ESP_SYSTEM_INIT_FN(init_flash, CORE, BIT(0), 130)
{
#if CONFIG_SPI_FLASH_ROM_IMPL
spi_flash_rom_impl_init();
#endif
esp_flash_app_init();
esp_err_t flash_ret = esp_flash_init_default_chip();
assert(flash_ret == ESP_OK);
(void)flash_ret;
#if CONFIG_SPI_FLASH_BROWNOUT_RESET
spi_flash_needs_reset_check();
#endif // CONFIG_SPI_FLASH_BROWNOUT_RESET
// The log library will call the registered callback function to check if the cache is disabled.
esp_log_util_set_cache_enabled_cb(spi_flash_cache_enabled);
#if CONFIG_PM_WORKAROUND_FREQ_LIMIT_ENABLED
esp_pm_flash_freq_limit_init();
#endif // CONFIG_PM_WORKAROUND_FREQ_LIMIT_ENABLED
return ESP_OK;
}
#endif // !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
#if CONFIG_ESP_XT_WDT
ESP_SYSTEM_INIT_FN(init_xt_wdt, CORE, BIT(0), 170)
{
@@ -146,6 +123,14 @@ ESP_SYSTEM_INIT_FN(init_pm, SECONDARY, BIT(0), 201)
}
#endif // CONFIG_PM_ENABLE
#if CONFIG_PM_WORKAROUND_FREQ_LIMIT_ENABLED
ESP_SYSTEM_INIT_FN(init_pm_flash_freq_limit, SECONDARY, BIT(0), 202)
{
esp_pm_flash_freq_limit_init();
return ESP_OK;
}
#endif // CONFIG_PM_WORKAROUND_FREQ_LIMIT_ENABLED
#if SOC_APB_BACKUP_DMA
ESP_SYSTEM_INIT_FN(init_apb_dma, SECONDARY, BIT(0), 203)
{
components/esp_system/system_init_fn.txt
+2 -1
View File
@@ -60,7 +60,7 @@ CORE: 118: init_vfs_nullfs in components/vfs/nullfs.c on BIT(0)
CORE: 119: init_vfs_console in components/esp_stdio/stdio_vfs.c on BIT(0)
CORE: 120: init_libc_stdio in components/esp_libc/src/init.c on BIT(0)
CORE: 130: init_flash in components/esp_system/startup_funcs.c on BIT(0)
CORE: 130: init_flash in components/spi_flash/esp_flash_spi_init.c on BIT(0)
CORE: 140: init_efuse in components/efuse/src/esp_efuse_startup.c on BIT(0)
CORE: 170: init_xt_wdt in components/esp_system/startup_funcs.c on BIT(0)
@@ -113,6 +113,7 @@ SECONDARY: 151: nvs_sec_provider_register_hmac_scheme in components/nvs_sec_prov
# the rest of the components which are initialized from startup_funcs.c
# [refactor-todo]: move init calls into respective components
SECONDARY: 201: init_pm in components/esp_system/startup_funcs.c on BIT(0)
SECONDARY: 202: init_pm_flash_freq_limit in components/esp_system/startup_funcs.c on BIT(0)
SECONDARY: 203: init_apb_dma in components/esp_system/startup_funcs.c on BIT(0)
SECONDARY: 204: init_coexist in components/esp_system/startup_funcs.c on BIT(0)
SECONDARY: 205: init_bootloader_offset in components/esp_system/startup_funcs.c on BIT(0)
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
-4
View File
@@ -1083,10 +1083,6 @@ config SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR
bool
default y
config SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED
bool
default y
config SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY
bool
default y
components/soc/esp32c5/include/soc/soc_caps.h
-1
View File
@@ -443,7 +443,6 @@
#define SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP (1)
#define SOC_SPI_MEM_SUPPORT_TIMING_TUNING (1)
#define SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR (1)
#define SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED (1)
#define SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY (1)
#define SOC_MEMSPI_SRC_FREQ_120M_SUPPORTED 1
components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
-4
View File
@@ -815,10 +815,6 @@ config SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR
bool
default y
config SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED
bool
default y
config SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY
bool
default y
components/soc/esp32c61/include/soc/soc_caps.h
-1
View File
@@ -341,7 +341,6 @@
#define SOC_SPI_MEM_SUPPORT_WRAP (1)
#define SOC_SPI_MEM_SUPPORT_TIMING_TUNING (1)
#define SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR (1)
#define SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED (1)
#define SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY (1)
#define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1
components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
-4
View File
@@ -675,10 +675,6 @@ config SOC_SPI_MEM_SUPPORT_WRAP
bool
default y
config SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED
bool
default y
config SOC_SYSTIMER_COUNTER_NUM
int
default 2
components/soc/esp32h4/include/soc/soc_caps.h
-1
View File
@@ -384,7 +384,6 @@
#define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1)
#define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1)
#define SOC_SPI_MEM_SUPPORT_WRAP (1)
#define SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED (1)
/*-------------------------- SYSTIMER CAPS ----------------------------------*/
#define SOC_SYSTIMER_COUNTER_NUM 2 // Number of counter units
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
-4
View File
@@ -1443,10 +1443,6 @@ config SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP
bool
default y
config SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED
bool
default y
config SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR
bool
default y
components/soc/esp32p4/include/soc/soc_caps.h
-1
View File
@@ -556,7 +556,6 @@
#define SOC_MEMSPI_TIMING_TUNING_BY_DQS (1)
#define SOC_MEMSPI_TIMING_TUNING_BY_FLASH_DELAY (1)
#define SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP (1)
#define SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED (1)
#define SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR (1)
#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT (1)
components/spi_flash/CMakeLists.txt
+3 -1
View File
@@ -55,7 +55,7 @@ else()
"spi_flash_os_func_noos.c")
list(APPEND srcs ${cache_srcs})
set(priv_requires bootloader_support soc esp_hal_gpio esp_mm)
set(priv_requires bootloader_support soc esp_hal_gpio esp_driver_gpio esp_mm)
if(${target} STREQUAL "esp32s2")
list(APPEND priv_requires esp_security)
@@ -83,4 +83,6 @@ if(NOT non_os_build AND NOT CONFIG_APP_BUILD_TYPE_PURE_RAM_APP)
# will be replaced with MMU requirements
idf_component_optional_requires(PRIVATE esp_psram)
endif()
# Force linking init_flash ESP_SYSTEM_INIT_FN to ensure it's not discarded by linker
target_link_libraries(${COMPONENT_LIB} INTERFACE "-u esp_flash_app_init")
endif()
components/spi_flash/esp_flash_api.c
+9 -2
View File
@@ -10,7 +10,7 @@
#include <string.h>
#include "esp_memory_utils.h"
#include "spi_flash_chip_driver.h"
#include "esp_flash_port/spi_flash_chip_driver.h"
#include "memspi_host_driver.h"
#include "esp_log.h"
#include "sdkconfig.h"
@@ -24,7 +24,6 @@
#include "esp_check.h"
#include "hal/efuse_hal.h"
#include "soc/chip_revision.h"
#include "esp_cpu.h"
#if CONFIG_IDF_TARGET_ESP32S2
#include "esp_crypto_lock.h" // for locking flash encryption peripheral
@@ -1592,3 +1591,11 @@ esp_err_t esp_flash_app_disable_protect(bool disable)
return esp_flash_app_enable_os_functions(esp_flash_default_chip);
}
}
bool esp_flash_is_quad_mode(const esp_flash_t *chip)
{
if (chip == NULL) {
chip = esp_flash_default_chip;
}
return (chip->read_mode == SPI_FLASH_QIO) || (chip->read_mode == SPI_FLASH_QOUT);
}
components/spi_flash/esp_flash_spi_init.c
+32 -10
View File
@@ -8,20 +8,24 @@
#include "esp_flash.h"
#include "memspi_host_driver.h"
#include "esp_flash_spi_init.h"
#include "driver/gpio.h"
#include "esp_rom_gpio.h"
#include "esp_rom_efuse.h"
#include "esp_log.h"
#include "esp_heap_caps.h"
#include "hal/spi_types.h"
#include "esp_private/spi_share_hw_ctrl.h"
#include "esp_private/mspi_intr.h"
#include "esp_ldo_regulator.h"
#include "hal/spi_flash_hal.h"
#include "spi_flash_chip_driver.h"
#include "esp_flash_port/spi_flash_chip_driver.h"
#include "hal/gpio_hal.h"
#include "esp_flash_internal.h"
#include "esp_rom_gpio.h"
#include "esp_private/spi_flash_os.h"
#include "esp_private/cache_utils.h"
#include "esp_private/log_util.h"
#include "esp_private/startup_internal.h"
#include "esp_spi_flash_counters.h"
#include "esp_rom_spiflash.h"
#include "bootloader_flash.h"
@@ -29,13 +33,10 @@
#include "esp_private/esp_clk_tree_common.h"
#include "clk_ctrl_os.h"
#include "soc/soc_caps.h"
#include "hal/mspi_ll.h"
__attribute__((unused)) static const char TAG[] = "spi_flash";
#if !CONFIG_SPI_FLASH_AUTO_SUSPEND && !CONFIG_SPI_FLASH_PLACE_FUNCTIONS_IN_IRAM
#error "CONFIG_SPI_FLASH_PLACE_FUNCTIONS_IN_IRAM cannot be disabled when CONFIG_SPI_FLASH_AUTO_SUSPEND is disabled."
#endif
#if CONFIG_SPI_FLASH_ROM_IMPL && (CONFIG_ESPTOOLPY_FLASHSIZE_32MB || CONFIG_ESPTOOLPY_FLASHSIZE_64MB || CONFIG_ESPTOOLPY_FLASHSIZE_128MB)
#error "Flash chip size equal or over 32MB memory cannot use driver in ROM"
#endif
@@ -149,7 +150,7 @@ esp_flash_t *esp_flash_default_chip = NULL;
// 1. Frequency limit workaround is enabled (CONFIG_SPI_FLASH_FREQ_LIMIT_C5_240MHZ)
// 2. Flash frequency requires timing tuning (80MHz or 120MHz, i.e., > 40MHz)
// 3. CPU frequency reduction will trigger MSPI timing tuning to enter low speed mode
// This happens when: SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED && CONFIG_SPIRAM &&
// This happens when: MSPI_TIMING_LL_PSRAM_FREQ_AXI_CONSTRAINED && CONFIG_SPIRAM &&
// (target_cpu_freq < CONFIG_SPIRAM_SPEED)
// Note: The runtime check for CPU freq < PSRAM speed is done in clk_utils.c,
// which calls mspi_timing_change_speed_mode_cache_safe(true) to enter low speed mode.
@@ -558,10 +559,6 @@ esp_err_t esp_flash_init_default_chip(void)
cfg.auto_waiti_pes = true;
#endif
#if CONFIG_SPI_FLASH_SOFTWARE_RESUME
cfg.software_resume = true;
#endif
//the host is already initialized, only do init for the data and load it to the host
esp_err_t err = memspi_host_init_pointers(&esp_flash_default_host, &cfg);
if (err != ESP_OK) {
@@ -649,3 +646,28 @@ esp_err_t esp_flash_app_init(void)
err = esp_flash_app_enable_os_functions(&default_chip);
return err;
}
#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
ESP_SYSTEM_INIT_FN(init_flash, CORE, BIT(0), 130)
{
#if CONFIG_SPI_FLASH_ROM_IMPL
spi_flash_rom_impl_init();
#endif
esp_flash_app_init();
esp_err_t flash_ret = esp_flash_init_default_chip();
assert(flash_ret == ESP_OK);
(void)flash_ret;
#if CONFIG_SPI_FLASH_BROWNOUT_RESET
spi_flash_needs_reset_check();
#endif // CONFIG_SPI_FLASH_BROWNOUT_RESET
// The log library will call the registered callback function to check if the cache is disabled.
esp_log_util_set_cache_enabled_cb(spi_flash_cache_enabled);
// Register MSPI Flash interrupt
#if MSPI_LL_INTR_EVENT_SUPPORTED && MSPI_LL_INTR_SHARED
esp_mspi_register_isr(NULL);
#endif
//else register flash standalone ISR to deal with CPU / API flash access
return ESP_OK;
}
#endif // !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
components/spi_flash/include/esp_flash.h
+2 -89
View File
@@ -10,6 +10,7 @@
#include <stdbool.h>
#include "hal/spi_flash_types.h"
#include "esp_blockdev.h"
#include "esp_bit_defs.h"
#ifdef __cplusplus
extern "C" {
@@ -28,91 +29,6 @@ typedef struct {
uint32_t size; ///< Size of the region
} esp_flash_region_t;
/** @brief OS-level integration hooks for accessing flash chips inside a running OS
*
* It's in the public header because some instances should be allocated statically in the startup
* code. May be updated according to hardware version and new flash chip feature requirements,
* shouldn't be treated as public API.
*
* For advanced developers, you may replace some of them with your implementations at your own
* risk.
*/
typedef struct {
/**
* Flags for start function
*/
/** Limit CPU frequency during flash operations (ESP32-C5 only, 240MHz).
*/
#define ESP_FLASH_START_FLAG_LIMIT_CPU_FREQ BIT(0)
/**
* Called before commencing any flash operation. Does not need to be
* recursive (ie is called at most once for each call to 'end').
*/
esp_err_t (*start)(void *arg, uint32_t flags);
/** Called after completing any flash operation. */
esp_err_t (*end)(void *arg);
/** Called before any erase/write operations to check whether the region is limited by the OS */
esp_err_t (*region_protected)(void* arg, size_t start_addr, size_t size);
/** Delay for at least 'us' microseconds. Called in between 'start' and 'end'. */
esp_err_t (*delay_us)(void *arg, uint32_t us);
/** Called for get temp buffer when buffer from application cannot be directly read into/write from. */
void *(*get_temp_buffer)(void* arg, size_t reqest_size, size_t* out_size);
/** Called for release temp buffer. */
void (*release_temp_buffer)(void* arg, void *temp_buf);
#define SPI_FLASH_YIELD_REQ_YIELD BIT(0)
#define SPI_FLASH_YIELD_REQ_SUSPEND BIT(1)
/** Yield to other tasks. Called during erase operations.
* @return ESP_OK means yield needs to be called (got an event to handle), while ESP_ERR_TIMEOUT means skip yield.*/
esp_err_t (*check_yield)(void *arg, uint32_t chip_status, uint32_t* out_request);
#define SPI_FLASH_YIELD_STA_RESUME BIT(2)
/** Yield to other tasks. Called during erase operations. */
esp_err_t (*yield)(void *arg, uint32_t* out_status);
/** Called for get system time. */
int64_t (*get_system_time)(void *arg);
#define SPI_FLASH_OS_IS_ERASING_STATUS_FLAG BIT(0)
/** Call to set flash operation status */
void (*set_flash_op_status)(uint32_t op_status);
} esp_flash_os_functions_t;
/** @brief Structure to describe a SPI flash chip connected to the system.
Structure must be initialized before use (passed to esp_flash_init()). It's in the public
header because some instances should be allocated statically in the startup code. May be
updated according to hardware version and new flash chip feature requirements, shouldn't be
treated as public API.
For advanced developers, you may replace some of them with your implementations at your own
risk.
*/
struct esp_flash_t {
spi_flash_host_inst_t* host; ///< Pointer to hardware-specific "host_driver" structure. Must be initialized before used.
const spi_flash_chip_t *chip_drv; ///< Pointer to chip-model-specific "adapter" structure. If NULL, will be detected during initialisation.
const esp_flash_os_functions_t *os_func; ///< Pointer to os-specific hook structure. Call ``esp_flash_init_os_functions()`` to setup this field, after the host is properly initialized.
void *os_func_data; ///< Pointer to argument for os-specific hooks. Left NULL and will be initialized with ``os_func``.
esp_flash_io_mode_t read_mode; ///< Configured SPI flash read mode. Set before ``esp_flash_init`` is called.
uint32_t size; ///< Size of SPI flash in bytes. If 0, size will be detected during initialisation. Note: this stands for the size in the binary image header. If you want to get the flash physical size, please call `esp_flash_get_physical_size`.
uint32_t chip_id; ///< Detected chip id.
uint32_t busy :1; ///< This flag is used to verify chip's status.
uint32_t hpm_dummy_ena :1; ///< This flag is used to verify whether flash works under HPM status.
uint32_t reserved_flags :30; ///< reserved.
int clock_source; ///< Clock source for GPSPI.
};
/** @brief Initialise SPI flash chip interface.
*
@@ -384,10 +300,7 @@ extern esp_flash_t *esp_flash_default_chip;
*
* @return true if flash works in quad mode, otherwise false
*/
static inline bool esp_flash_is_quad_mode(const esp_flash_t *chip)
{
return (chip->read_mode == SPI_FLASH_QIO) || (chip->read_mode == SPI_FLASH_QOUT);
}
bool esp_flash_is_quad_mode(const esp_flash_t *chip);
/*******************************************************************************
* BDL Functions
components/spi_flash/include/esp_flash_internal.h
+1
View File
@@ -12,6 +12,7 @@
#include "sdkconfig.h"
#include "esp_flash.h"
#include "esp_private/esp_flash_types.h"
/** Internal API, don't use in the applications */
components/spi_flash/include/spi_flash_chip_driver.h → components/spi_flash/include/esp_flash_port/spi_flash_chip_driver.h
+1 -3
View File
@@ -7,9 +7,7 @@
#pragma once
#include "esp_flash.h"
#include "esp_attr.h"
struct esp_flash_t;
typedef struct esp_flash_t esp_flash_t;
#include "esp_private/esp_flash_types.h"
typedef struct spi_flash_chip_t spi_flash_chip_t;
components/spi_flash/include/esp_private/esp_flash_types.h
+101
View File
@@ -0,0 +1,101 @@
/*
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "esp_err.h"
#include <stdint.h>
#include <stdbool.h>
#include "esp_bit_defs.h"
#include "hal/spi_flash_types.h"
#ifdef __cplusplus
extern "C" {
#endif
struct spi_flash_chip_t;
typedef struct spi_flash_chip_t spi_flash_chip_t;
/** @brief OS-level integration hooks for accessing flash chips inside a running OS
*
* This structure is used internally by the SPI flash driver and should not be used directly by applications.
* It's defined here because some instances need to be allocated statically in the startup code.
*/
typedef struct esp_flash_os_functions_t {
/**
* Flags for start function
*/
/** Limit CPU frequency during flash operations (ESP32-C5 only, 240MHz).
*/
#define ESP_FLASH_START_FLAG_LIMIT_CPU_FREQ BIT(0)
/**
* Called before commencing any flash operation. Does not need to be
* recursive (ie is called at most once for each call to 'end').
*/
esp_err_t (*start)(void *arg, uint32_t flags);
/** Called after completing any flash operation. */
esp_err_t (*end)(void *arg);
/** Called before any erase/write operations to check whether the region is limited by the OS */
esp_err_t (*region_protected)(void* arg, size_t start_addr, size_t size);
/** Delay for at least 'us' microseconds. Called in between 'start' and 'end'. */
esp_err_t (*delay_us)(void *arg, uint32_t us);
/** Called for get temp buffer when buffer from application cannot be directly read into/write from. */
void *(*get_temp_buffer)(void* arg, size_t reqest_size, size_t* out_size);
/** Called for release temp buffer. */
void (*release_temp_buffer)(void *arg, void *temp_buf);
#define SPI_FLASH_YIELD_REQ_YIELD BIT(0)
#define SPI_FLASH_YIELD_REQ_SUSPEND BIT(1)
/** Yield to other tasks. Called during erase operations.
* @return ESP_OK means yield needs to be called (got an event to handle), while ESP_ERR_TIMEOUT means skip yield.*/
esp_err_t (*check_yield)(void *arg, uint32_t chip_status, uint32_t* out_request);
#define SPI_FLASH_YIELD_STA_RESUME BIT(2)
/** Yield to other tasks. Called during erase operations. */
esp_err_t (*yield)(void *arg, uint32_t* out_status);
/** Called for get system time. */
int64_t (*get_system_time)(void *arg);
#define SPI_FLASH_OS_IS_ERASING_STATUS_FLAG BIT(0)
/** Call to set flash operation status */
void (*set_flash_op_status)(uint32_t op_status);
} esp_flash_os_functions_t;
/** @brief Structure to describe a SPI flash chip connected to the system.
*
* This structure is used internally by the SPI flash driver and should not be used directly by applications.
* It's defined here because some instances need to be allocated statically in the startup code.
*/
struct esp_flash_t {
spi_flash_host_inst_t* host; ///< Pointer to hardware-specific "host_driver" structure. Must be initialized before used.
const spi_flash_chip_t *chip_drv; ///< Pointer to chip-model-specific "adapter" structure. If NULL, will be detected during initialisation.
const esp_flash_os_functions_t *os_func; ///< Pointer to os-specific hook structure. Call ``esp_flash_init_os_functions()`` to setup this field, after the host is properly initialized.
void *os_func_data; ///< Pointer to argument for os-specific hooks. Left NULL and will be initialized with ``os_func``.
esp_flash_io_mode_t read_mode; ///< Configured SPI flash read mode. Set before ``esp_flash_init`` is called.
uint32_t size; ///< Size of SPI flash in bytes. If 0, size will be detected during initialisation. Note: this stands for the size in the binary image header. If you want to get the flash physical size, please call `esp_flash_get_physical_size`.
uint32_t chip_id; ///< Detected chip id.
uint32_t busy :1; ///< This flag is used to verify chip's status.
uint32_t hpm_dummy_ena :1; ///< This flag is used to verify whether flash works under HPM status.
uint32_t reserved_flags :30; ///< reserved.
int clock_source; ///< Clock source for GPSPI.
};
#ifdef __cplusplus
}
#endif
components/spi_flash/include/esp_private/spi_flash_os.h
+1
View File
@@ -15,6 +15,7 @@
#include "esp_rom_spiflash.h"
#include "esp_err.h"
#include "esp_flash.h"
#include "esp_private/esp_flash_types.h"
#include "hal/spi_flash_hal.h"
#include "spi_flash_override.h"
#include "soc/soc_caps.h"
components/spi_flash/include/spi_flash_chip_boya.h
+1 -1
View File
@@ -8,7 +8,7 @@
#include <stdint.h>
#include "esp_flash.h"
#include "spi_flash_chip_driver.h"
#include "esp_flash_port/spi_flash_chip_driver.h"
#include "sdkconfig.h"
#ifdef CONFIG_SPI_FLASH_SUPPORT_BOYA_CHIP
components/spi_flash/include/spi_flash_chip_gd.h
+1 -1
View File
@@ -8,7 +8,7 @@
#include <stdint.h>
#include "esp_flash.h"
#include "spi_flash_chip_driver.h"
#include "esp_flash_port/spi_flash_chip_driver.h"
#include "sdkconfig.h"
components/spi_flash/include/spi_flash_chip_generic.h
+7 -15
View File
@@ -1,22 +1,14 @@
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "esp_flash.h"
#include "spi_flash_chip_driver.h"
#include "esp_flash_port/spi_flash_chip_driver.h"
/*
@@ -346,7 +338,7 @@ esp_err_t spi_flash_common_write_status_8b_wrsr2(esp_flash_t* chip, uint32_t sr)
* Most chip QE enable follows a common pattern, though commands to read/write
* the status register may be different, as well as the position of QE bit.
*
* Registers to actually do Quad transtions and command to be sent in reading
* Registers to actually do Quad transitions and command to be sent in reading
* should also be configured via
* spi_flash_chip_generic_config_host_io_mode().
*
components/spi_flash/include/spi_flash_chip_issi.h
+1 -1
View File
@@ -8,7 +8,7 @@
#include <stdint.h>
#include "esp_flash.h"
#include "spi_flash_chip_driver.h"
#include "esp_flash_port/spi_flash_chip_driver.h"
#include "sdkconfig.h"
components/spi_flash/include/spi_flash_chip_mxic.h
+1 -1
View File
@@ -8,7 +8,7 @@
#include <stdint.h>
#include "esp_flash.h"
#include "spi_flash_chip_driver.h"
#include "esp_flash_port/spi_flash_chip_driver.h"
#include "sdkconfig.h"
/**
components/spi_flash/include/spi_flash_chip_th.h
+1 -1
View File
@@ -8,7 +8,7 @@
#include <stdint.h>
#include "esp_flash.h"
#include "spi_flash_chip_driver.h"
#include "esp_flash_port/spi_flash_chip_driver.h"
#include "sdkconfig.h"
#ifdef CONFIG_SPI_FLASH_SUPPORT_TH_CHIP
components/spi_flash/include/spi_flash_chip_winbond.h
+1 -1
View File
@@ -8,7 +8,7 @@
#include <stdint.h>
#include "esp_flash.h"
#include "spi_flash_chip_driver.h"
#include "esp_flash_port/spi_flash_chip_driver.h"
#include "sdkconfig.h"
/**
components/spi_flash/spi_flash_blockdev.c
+1 -1
View File
@@ -7,7 +7,7 @@
#include <inttypes.h>
#include <string.h>
#include "esp_flash.h"
#include "spi_flash_chip_driver.h"
#include "esp_flash_port/spi_flash_chip_driver.h"
#include "esp_heap_caps.h"
#include "esp_blockdev.h"
components/spi_flash/spi_flash_chip_drivers.c
+1 -1
View File
@@ -5,7 +5,7 @@
*/
#include <stdlib.h>
#include "spi_flash_chip_driver.h"
#include "esp_flash_port/spi_flash_chip_driver.h"
#include "spi_flash_chip_generic.h"
#include "spi_flash_chip_issi.h"
#include "spi_flash_chip_mxic.h"
components/spi_flash/spi_flash_os_func_app.c
+1
View File
@@ -10,6 +10,7 @@
#include "esp_attr.h"
#include "esp_private/system_internal.h"
#include "esp_flash.h"
#include "esp_private/esp_flash_types.h"
#include "esp_flash_partitions.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
components/spi_flash/spi_flash_os_func_noos.c
+1
View File
@@ -7,6 +7,7 @@
#include <stdarg.h>
#include "sdkconfig.h"
#include "esp_flash.h"
#include "esp_private/esp_flash_types.h"
#include "esp_attr.h"
#include "esp_rom_sys.h"
#include "esp_cpu.h"
components/spi_flash/test_apps/esp_flash_blockdev/main/test_spi_flash.c
+1 -1
View File
@@ -9,7 +9,7 @@
#include "esp_log.h"
#include "unity.h"
#include "spi_flash_chip_driver.h"
#include "esp_flash_port/spi_flash_chip_driver.h"
#include "test_flash_utils.h"
TEST_CASE("spi_flash BDL test", "[esp_flash]")
components/spi_flash/test_apps/esp_flash_freq_limit/CMakeLists.txt
-2
View File
@@ -1,8 +1,6 @@
# This is the project CMakeLists.txt file for the test subproject
cmake_minimum_required(VERSION 3.22)
set(EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/tools/test_apps/components")
# "Trim" the build. Include the minimal set of components, main, and anything it depends on. We also depend on
# esptool_py as we set CONFIG_ESPTOOLPY_... options.
set(COMPONENTS main esptool_py)
components/spi_flash/test_apps/esp_flash_freq_limit/main/test_esp_flash_freq_limit.c
+1
View File
@@ -14,6 +14,7 @@
#include <inttypes.h>
#include "unity.h"
#include "esp_flash.h"
#include "esp_private/esp_flash_types.h"
#include "soc/rtc.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
tools/ci/check_copyright_ignore.txt
-1
View File
@@ -492,7 +492,6 @@ components/soc/esp32s2/include/soc/fe_reg.h
components/soc/esp32s2/include/soc/memprot_defs.h
components/soc/esp32s2/include/soc/nrx_reg.h
components/soc/esp32s2/include/soc/soc_ulp.h
components/spi_flash/include/spi_flash_chip_generic.h
components/spi_flash/spi_flash_chip_boya.c
components/spi_flash/spi_flash_chip_issi.c
components/tcp_transport/include/esp_transport_ws.h
tools/ci/check_public_headers_exceptions.txt
-1
View File
@@ -33,7 +33,6 @@ components/spi_flash/include/spi_flash_chip_winbond.h
components/spi_flash/include/spi_flash_chip_boya.h
components/spi_flash/include/spi_flash_chip_th.h
components/spi_flash/include/memspi_host_driver.h
components/spi_flash/include/spi_flash_chip_driver.h
components/spi_flash/include/spi_flash_chip_generic.h