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refactor: remove gdma_trigger_peripheral_t

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This commit is contained in:
morris
2026-01-09 14:25:09 +08:00
parent b685c0e733
commit 1b258fc8c5
33 changed files with 411 additions and 227 deletions
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components/esp_driver_bitscrambler/src/bitscrambler_loopback.c
+1 -1
View File
@@ -47,7 +47,7 @@ static esp_err_t new_dma_channel(const gdma_channel_alloc_config_t *cfg, gdma_ch
//Note that there are chips that do not have SOC_GDMA_BUS_* defined, but those chips also do
//not have a BitScrambler.
#ifdef SOC_GDMA_BUS_AHB
if (bus == SOC_GDMA_BUS_AHB || bus == SOC_GDMA_BUS_ANY) {
if (bus == SOC_GDMA_BUS_AHB) {
ESP_RETURN_ON_ERROR(gdma_new_ahb_channel(cfg, tx_handle, rx_handle), TAG, "alloc AHB DMA channel failed");
}
#endif
components/esp_driver_i2s/i2s_common.c
+4 -4
View File
@@ -793,21 +793,21 @@ esp_err_t i2s_init_dma_intr(i2s_chan_handle_t handle, int intr_flag)
int port_id = handle->controller->id;
ESP_RETURN_ON_FALSE((port_id >= 0) && (port_id < I2S_LL_GET(INST_NUM)), ESP_ERR_INVALID_ARG, TAG, "invalid handle");
/* Set GDMA trigger module */
gdma_trigger_t trig = {.periph = GDMA_TRIG_PERIPH_I2S};
gdma_trigger_t trig = {0};
switch (port_id) {
#if I2S_LL_GET(INST_NUM) > 2
case I2S_NUM_2:
trig.instance_id = SOC_GDMA_TRIG_PERIPH_I2S2;
trig = GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_I2S, 2);
break;
#endif
#if I2S_LL_GET(INST_NUM) > 1
case I2S_NUM_1:
trig.instance_id = SOC_GDMA_TRIG_PERIPH_I2S1;
trig = GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_I2S, 1);
break;
#endif
case I2S_NUM_0:
trig.instance_id = SOC_GDMA_TRIG_PERIPH_I2S0;
trig = GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_I2S, 0);
break;
default:
ESP_LOGE(TAG, "Unsupported I2S port number");
components/esp_hal_dma/esp32c2/include/hal/gdma_ll.h
+26 -11
View File
@@ -31,7 +31,6 @@ extern "C" {
// any "valid" peripheral ID can be used for M2M mode
#define GDMA_LL_M2M_FREE_PERIPH_ID_MASK (0x185)
#define GDMA_LL_INVALID_PERIPH_ID (0x3F)
#define GDMA_LL_EVENT_TX_FIFO_UDF (1<<12)
#define GDMA_LL_EVENT_TX_FIFO_OVF (1<<11)
@@ -303,18 +302,27 @@ static inline void gdma_ll_rx_set_priority(gdma_dev_t *dev, uint32_t channel, ui
/**
* @brief Connect DMA RX channel to a given peripheral
*/
static inline void gdma_ll_rx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id)
static inline void gdma_ll_rx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, int periph_id)
{
dev->channel[channel].in.in_peri_sel.sel = periph_id;
dev->channel[channel].in.in_conf0.mem_trans_en = (periph == GDMA_TRIG_PERIPH_M2M);
dev->channel[channel].in.in_conf0.mem_trans_en = false;
}
/**
* @brief Disconnect DMA RX channel from peripheral
* @brief Connect DMA RX channel to memory (M2M mode)
*/
static inline void gdma_ll_rx_disconnect_from_periph(gdma_dev_t *dev, uint32_t channel)
static inline void gdma_ll_rx_connect_to_mem(gdma_dev_t *dev, uint32_t channel, int dummy_id)
{
dev->channel[channel].in.in_peri_sel.sel = GDMA_LL_INVALID_PERIPH_ID;
dev->channel[channel].in.in_peri_sel.sel = dummy_id;
dev->channel[channel].in.in_conf0.mem_trans_en = true;
}
/**
* @brief Disconnect DMA RX channel from either peripheral or memory
*/
static inline void gdma_ll_rx_disconnect_all(gdma_dev_t *dev, uint32_t channel)
{
dev->channel[channel].in.in_peri_sel.sel = 0x3F;
dev->channel[channel].in.in_conf0.mem_trans_en = false;
}
@@ -520,18 +528,25 @@ static inline void gdma_ll_tx_set_priority(gdma_dev_t *dev, uint32_t channel, ui
/**
* @brief Connect DMA TX channel to a given peripheral
*/
static inline void gdma_ll_tx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id)
static inline void gdma_ll_tx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, int periph_id)
{
(void)periph;
dev->channel[channel].out.out_peri_sel.sel = periph_id;
}
/**
* @brief Disconnect DMA TX channel from peripheral
* @brief Connect DMA TX channel to memory (M2M mode)
*/
static inline void gdma_ll_tx_disconnect_from_periph(gdma_dev_t *dev, uint32_t channel)
static inline void gdma_ll_tx_connect_to_mem(gdma_dev_t *dev, uint32_t channel, int dummy_id)
{
dev->channel[channel].out.out_peri_sel.sel = GDMA_LL_INVALID_PERIPH_ID;
dev->channel[channel].out.out_peri_sel.sel = dummy_id;
}
/**
* @brief Disconnect DMA TX channel from either peripheral or memory
*/
static inline void gdma_ll_tx_disconnect_all(gdma_dev_t *dev, uint32_t channel)
{
dev->channel[channel].out.out_peri_sel.sel = 0x3F;
}
#ifdef __cplusplus
components/esp_hal_dma/esp32c3/include/hal/gdma_ll.h
+26 -11
View File
@@ -31,7 +31,6 @@ extern "C" {
// any "valid" peripheral ID can be used for M2M mode
#define GDMA_LL_M2M_FREE_PERIPH_ID_MASK (0x1CD)
#define GDMA_LL_INVALID_PERIPH_ID (0x3F)
#define GDMA_LL_EVENT_TX_FIFO_UDF (1<<12)
#define GDMA_LL_EVENT_TX_FIFO_OVF (1<<11)
@@ -303,18 +302,27 @@ static inline void gdma_ll_rx_set_priority(gdma_dev_t *dev, uint32_t channel, ui
/**
* @brief Connect DMA RX channel to a given peripheral
*/
static inline void gdma_ll_rx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id)
static inline void gdma_ll_rx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, int periph_id)
{
dev->channel[channel].in.in_peri_sel.sel = periph_id;
dev->channel[channel].in.in_conf0.mem_trans_en = (periph == GDMA_TRIG_PERIPH_M2M);
dev->channel[channel].in.in_conf0.mem_trans_en = false;
}
/**
* @brief Disconnect DMA RX channel from peripheral
* @brief Connect DMA RX channel to memory (M2M mode)
*/
static inline void gdma_ll_rx_disconnect_from_periph(gdma_dev_t *dev, uint32_t channel)
static inline void gdma_ll_rx_connect_to_mem(gdma_dev_t *dev, uint32_t channel, int dummy_id)
{
dev->channel[channel].in.in_peri_sel.sel = GDMA_LL_INVALID_PERIPH_ID;
dev->channel[channel].in.in_peri_sel.sel = dummy_id;
dev->channel[channel].in.in_conf0.mem_trans_en = true;
}
/**
* @brief Disconnect DMA RX channel from all peripherals
*/
static inline void gdma_ll_rx_disconnect_all(gdma_dev_t *dev, uint32_t channel)
{
dev->channel[channel].in.in_peri_sel.sel = 0x3F;
dev->channel[channel].in.in_conf0.mem_trans_en = false;
}
@@ -520,18 +528,25 @@ static inline void gdma_ll_tx_set_priority(gdma_dev_t *dev, uint32_t channel, ui
/**
* @brief Connect DMA TX channel to a given peripheral
*/
static inline void gdma_ll_tx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id)
static inline void gdma_ll_tx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, int periph_id)
{
(void)periph;
dev->channel[channel].out.out_peri_sel.sel = periph_id;
}
/**
* @brief Disconnect DMA TX channel from peripheral
* @brief Connect DMA TX channel to memory (M2M mode)
*/
static inline void gdma_ll_tx_disconnect_from_periph(gdma_dev_t *dev, uint32_t channel)
static inline void gdma_ll_tx_connect_to_mem(gdma_dev_t *dev, uint32_t channel, int dummy_id)
{
dev->channel[channel].out.out_peri_sel.sel = GDMA_LL_INVALID_PERIPH_ID;
dev->channel[channel].out.out_peri_sel.sel = dummy_id;
}
/**
* @brief Disconnect DMA TX channel from all peripherals
*/
static inline void gdma_ll_tx_disconnect_all(gdma_dev_t *dev, uint32_t channel)
{
dev->channel[channel].out.out_peri_sel.sel = 0x3F;
}
#ifdef __cplusplus
components/esp_hal_dma/esp32c5/include/hal/ahb_dma_ll.h
+26 -11
View File
@@ -29,7 +29,6 @@ extern "C" {
// for M2M mode, hardware will automatically assign peri_sel ID depends on the channel number (ch0: 10, ch1: 11, ch2: 12)
#define AHB_DMA_LL_M2M_FREE_PERIPH_ID_MASK (0x1C00)
#define AHB_DMA_LL_INVALID_PERIPH_ID (0x3F)
#define GDMA_LL_EVENT_TX_FIFO_UDF (1<<5)
#define GDMA_LL_EVENT_TX_FIFO_OVF (1<<4)
@@ -388,18 +387,27 @@ static inline void ahb_dma_ll_rx_set_priority(ahb_dma_dev_t *dev, uint32_t chann
/**
* @brief Connect DMA RX channel to a given peripheral
*/
static inline void ahb_dma_ll_rx_connect_to_periph(ahb_dma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id)
static inline void ahb_dma_ll_rx_connect_to_periph(ahb_dma_dev_t *dev, uint32_t channel, int periph_id)
{
dev->channel[channel].in.in_peri_sel.peri_in_sel_chn = periph_id;
dev->channel[channel].in.in_conf0.mem_trans_en_chn = (periph == GDMA_TRIG_PERIPH_M2M);
dev->channel[channel].in.in_conf0.mem_trans_en_chn = false;
}
/**
* @brief Disconnect DMA RX channel from peripheral
* @brief Connect DMA RX channel to memory (M2M mode)
*/
static inline void ahb_dma_ll_rx_disconnect_from_periph(ahb_dma_dev_t *dev, uint32_t channel)
static inline void ahb_dma_ll_rx_connect_to_mem(ahb_dma_dev_t *dev, uint32_t channel, int dummy_id)
{
dev->channel[channel].in.in_peri_sel.peri_in_sel_chn = AHB_DMA_LL_INVALID_PERIPH_ID;
dev->channel[channel].in.in_peri_sel.peri_in_sel_chn = dummy_id;
dev->channel[channel].in.in_conf0.mem_trans_en_chn = true;
}
/**
* @brief Disconnect DMA RX channel from all peripherals
*/
static inline void ahb_dma_ll_rx_disconnect_all(ahb_dma_dev_t *dev, uint32_t channel)
{
dev->channel[channel].in.in_peri_sel.peri_in_sel_chn = 0x3F;
dev->channel[channel].in.in_conf0.mem_trans_en_chn = false;
}
@@ -656,18 +664,25 @@ static inline void ahb_dma_ll_tx_set_priority(ahb_dma_dev_t *dev, uint32_t chann
/**
* @brief Connect DMA TX channel to a given peripheral
*/
static inline void ahb_dma_ll_tx_connect_to_periph(ahb_dma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id)
static inline void ahb_dma_ll_tx_connect_to_periph(ahb_dma_dev_t *dev, uint32_t channel, int periph_id)
{
(void)periph;
dev->channel[channel].out.out_peri_sel.peri_out_sel_chn = periph_id;
}
/**
* @brief Disconnect DMA TX channel from peripheral
* @brief Connect DMA TX channel to memory (M2M mode)
*/
static inline void ahb_dma_ll_tx_disconnect_from_periph(ahb_dma_dev_t *dev, uint32_t channel)
static inline void ahb_dma_ll_tx_connect_to_mem(ahb_dma_dev_t *dev, uint32_t channel, int dummy_id)
{
dev->channel[channel].out.out_peri_sel.peri_out_sel_chn = AHB_DMA_LL_INVALID_PERIPH_ID;
dev->channel[channel].out.out_peri_sel.peri_out_sel_chn = dummy_id;
}
/**
* @brief Disconnect DMA TX channel from all peripherals
*/
static inline void ahb_dma_ll_tx_disconnect_all(ahb_dma_dev_t *dev, uint32_t channel)
{
dev->channel[channel].out.out_peri_sel.peri_out_sel_chn = 0x3F;
}
/**
components/esp_hal_dma/esp32c6/include/hal/gdma_ll.h
+26 -11
View File
@@ -32,7 +32,6 @@ extern "C" {
// any "dummy" peripheral ID can be used for M2M mode
#define GDMA_LL_M2M_FREE_PERIPH_ID_MASK (0xFC32)
#define GDMA_LL_INVALID_PERIPH_ID (0x3F)
#define GDMA_LL_EVENT_TX_FIFO_UDF (1<<5)
#define GDMA_LL_EVENT_TX_FIFO_OVF (1<<4)
@@ -337,18 +336,27 @@ static inline void gdma_ll_rx_set_priority(gdma_dev_t *dev, uint32_t channel, ui
/**
* @brief Connect DMA RX channel to a given peripheral
*/
static inline void gdma_ll_rx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id)
static inline void gdma_ll_rx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, int periph_id)
{
dev->channel[channel].in.in_peri_sel.peri_in_sel = periph_id;
dev->channel[channel].in.in_conf0.mem_trans_en = (periph == GDMA_TRIG_PERIPH_M2M);
dev->channel[channel].in.in_conf0.mem_trans_en = false;
}
/**
* @brief Disconnect DMA RX channel from peripheral
* @brief Connect DMA RX channel to memory (M2M mode)
*/
static inline void gdma_ll_rx_disconnect_from_periph(gdma_dev_t *dev, uint32_t channel)
static inline void gdma_ll_rx_connect_to_mem(gdma_dev_t *dev, uint32_t channel, int dummy_id)
{
dev->channel[channel].in.in_peri_sel.peri_in_sel = GDMA_LL_INVALID_PERIPH_ID;
dev->channel[channel].in.in_peri_sel.peri_in_sel = dummy_id;
dev->channel[channel].in.in_conf0.mem_trans_en = true;
}
/**
* @brief Disconnect DMA RX channel from peripheral/memory
*/
static inline void gdma_ll_rx_disconnect_all(gdma_dev_t *dev, uint32_t channel)
{
dev->channel[channel].in.in_peri_sel.peri_in_sel = 0x3F;
dev->channel[channel].in.in_conf0.mem_trans_en = false;
}
@@ -564,18 +572,25 @@ static inline void gdma_ll_tx_set_priority(gdma_dev_t *dev, uint32_t channel, ui
/**
* @brief Connect DMA TX channel to a given peripheral
*/
static inline void gdma_ll_tx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id)
static inline void gdma_ll_tx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, int periph_id)
{
(void)periph;
dev->channel[channel].out.out_peri_sel.peri_out_sel = periph_id;
}
/**
* @brief Disconnect DMA TX channel from peripheral
* @brief Connect DMA TX channel to memory (M2M mode)
*/
static inline void gdma_ll_tx_disconnect_from_periph(gdma_dev_t *dev, uint32_t channel)
static inline void gdma_ll_tx_connect_to_mem(gdma_dev_t *dev, uint32_t channel, int dummy_id)
{
dev->channel[channel].out.out_peri_sel.peri_out_sel = GDMA_LL_INVALID_PERIPH_ID;
dev->channel[channel].out.out_peri_sel.peri_out_sel = dummy_id;
}
/**
* @brief Disconnect DMA TX channel from peripheral/memory
*/
static inline void gdma_ll_tx_disconnect_all(gdma_dev_t *dev, uint32_t channel)
{
dev->channel[channel].out.out_peri_sel.peri_out_sel = 0x3F;
}
/**
components/esp_hal_dma/esp32c61/include/hal/ahb_dma_ll.h
+26 -11
View File
@@ -29,7 +29,6 @@ extern "C" {
// any "dummy" peripheral ID can be used for M2M mode
#define AHB_DMA_LL_M2M_FREE_PERIPH_ID_MASK (0xFE75)
#define AHB_DMA_LL_INVALID_PERIPH_ID (0x3F)
#define GDMA_LL_EVENT_TX_FIFO_UDF (1<<5)
#define GDMA_LL_EVENT_TX_FIFO_OVF (1<<4)
@@ -380,18 +379,27 @@ static inline void ahb_dma_ll_rx_set_priority(ahb_dma_dev_t *dev, uint32_t chann
/**
* @brief Connect DMA RX channel to a given peripheral
*/
static inline void ahb_dma_ll_rx_connect_to_periph(ahb_dma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id)
static inline void ahb_dma_ll_rx_connect_to_periph(ahb_dma_dev_t *dev, uint32_t channel, int periph_id)
{
dev->channel[channel].in.in_peri_sel.peri_in_sel_chn = periph_id;
dev->channel[channel].in.in_conf0.mem_trans_en_chn = (periph == GDMA_TRIG_PERIPH_M2M);
dev->channel[channel].in.in_conf0.mem_trans_en_chn = false;
}
/**
* @brief Disconnect DMA RX channel from peripheral
* @brief Connect DMA RX channel to memory (M2M mode)
*/
static inline void ahb_dma_ll_rx_disconnect_from_periph(ahb_dma_dev_t *dev, uint32_t channel)
static inline void ahb_dma_ll_rx_connect_to_mem(ahb_dma_dev_t *dev, uint32_t channel, int dummy_id)
{
dev->channel[channel].in.in_peri_sel.peri_in_sel_chn = AHB_DMA_LL_INVALID_PERIPH_ID;
dev->channel[channel].in.in_peri_sel.peri_in_sel_chn = dummy_id;
dev->channel[channel].in.in_conf0.mem_trans_en_chn = true;
}
/**
* @brief Disconnect DMA RX channel from peripheral/memory
*/
static inline void ahb_dma_ll_rx_disconnect_all(ahb_dma_dev_t *dev, uint32_t channel)
{
dev->channel[channel].in.in_peri_sel.peri_in_sel_chn = 0x3F;
dev->channel[channel].in.in_conf0.mem_trans_en_chn = false;
}
@@ -648,18 +656,25 @@ static inline void ahb_dma_ll_tx_set_priority(ahb_dma_dev_t *dev, uint32_t chann
/**
* @brief Connect DMA TX channel to a given peripheral
*/
static inline void ahb_dma_ll_tx_connect_to_periph(ahb_dma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id)
static inline void ahb_dma_ll_tx_connect_to_periph(ahb_dma_dev_t *dev, uint32_t channel, int periph_id)
{
(void)periph;
dev->channel[channel].out.out_peri_sel.peri_out_sel_chn = periph_id;
}
/**
* @brief Disconnect DMA TX channel from peripheral
* @brief Connect DMA TX channel to memory (M2M mode)
*/
static inline void ahb_dma_ll_tx_disconnect_from_periph(ahb_dma_dev_t *dev, uint32_t channel)
static inline void ahb_dma_ll_tx_connect_to_mem(ahb_dma_dev_t *dev, uint32_t channel, int dummy_id)
{
dev->channel[channel].out.out_peri_sel.peri_out_sel_chn = AHB_DMA_LL_INVALID_PERIPH_ID;
dev->channel[channel].out.out_peri_sel.peri_out_sel_chn = dummy_id;
}
/**
* @brief Disconnect DMA TX channel from peripheral/memory
*/
static inline void ahb_dma_ll_tx_disconnect_all(ahb_dma_dev_t *dev, uint32_t channel)
{
dev->channel[channel].out.out_peri_sel.peri_out_sel_chn = 0x3F;
}
/**
components/esp_hal_dma/esp32h2/include/hal/gdma_ll.h
+26 -11
View File
@@ -32,7 +32,6 @@ extern "C" {
// any "dummy" peripheral ID can be used for M2M mode
#define GDMA_LL_M2M_FREE_PERIPH_ID_MASK (0xFC32)
#define GDMA_LL_INVALID_PERIPH_ID (0x3F)
#define GDMA_LL_EVENT_TX_FIFO_UDF (1<<5)
#define GDMA_LL_EVENT_TX_FIFO_OVF (1<<4)
@@ -337,18 +336,27 @@ static inline void gdma_ll_rx_set_priority(gdma_dev_t *dev, uint32_t channel, ui
/**
* @brief Connect DMA RX channel to a given peripheral
*/
static inline void gdma_ll_rx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id)
static inline void gdma_ll_rx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, int periph_id)
{
dev->channel[channel].in.in_peri_sel.peri_in_sel = periph_id;
dev->channel[channel].in.in_conf0.mem_trans_en = (periph == GDMA_TRIG_PERIPH_M2M);
dev->channel[channel].in.in_conf0.mem_trans_en = false;
}
/**
* @brief Disconnect DMA RX channel from peripheral
* @brief Connect DMA RX channel to memory (M2M mode)
*/
static inline void gdma_ll_rx_disconnect_from_periph(gdma_dev_t *dev, uint32_t channel)
static inline void gdma_ll_rx_connect_to_mem(gdma_dev_t *dev, uint32_t channel, int dummy_id)
{
dev->channel[channel].in.in_peri_sel.peri_in_sel = GDMA_LL_INVALID_PERIPH_ID;
dev->channel[channel].in.in_peri_sel.peri_in_sel = dummy_id;
dev->channel[channel].in.in_conf0.mem_trans_en = true;
}
/**
* @brief Disconnect DMA RX channel from all peripherals
*/
static inline void gdma_ll_rx_disconnect_all(gdma_dev_t *dev, uint32_t channel)
{
dev->channel[channel].in.in_peri_sel.peri_in_sel = 0x3F;
dev->channel[channel].in.in_conf0.mem_trans_en = false;
}
@@ -564,18 +572,25 @@ static inline void gdma_ll_tx_set_priority(gdma_dev_t *dev, uint32_t channel, ui
/**
* @brief Connect DMA TX channel to a given peripheral
*/
static inline void gdma_ll_tx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id)
static inline void gdma_ll_tx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, int periph_id)
{
(void)periph;
dev->channel[channel].out.out_peri_sel.peri_out_sel = periph_id;
}
/**
* @brief Disconnect DMA TX channel from peripheral
* @brief Connect DMA TX channel to memory (M2M mode)
*/
static inline void gdma_ll_tx_disconnect_from_periph(gdma_dev_t *dev, uint32_t channel)
static inline void gdma_ll_tx_connect_to_mem(gdma_dev_t *dev, uint32_t channel, int dummy_id)
{
dev->channel[channel].out.out_peri_sel.peri_out_sel = GDMA_LL_INVALID_PERIPH_ID;
dev->channel[channel].out.out_peri_sel.peri_out_sel = dummy_id;
}
/**
* @brief Disconnect DMA TX channel from all peripherals
*/
static inline void gdma_ll_tx_disconnect_all(gdma_dev_t *dev, uint32_t channel)
{
dev->channel[channel].out.out_peri_sel.peri_out_sel = 0x3F;
}
/**
components/esp_hal_dma/esp32h21/include/hal/gdma_ll.h
+26 -11
View File
@@ -32,7 +32,6 @@ extern "C" {
// any "dummy" peripheral ID can be used for M2M mode
#define GDMA_LL_M2M_FREE_PERIPH_ID_MASK (0xFC32)
#define GDMA_LL_INVALID_PERIPH_ID (0x3F)
#define GDMA_LL_EVENT_TX_FIFO_UDF (1<<5)
#define GDMA_LL_EVENT_TX_FIFO_OVF (1<<4)
@@ -337,18 +336,27 @@ static inline void gdma_ll_rx_set_priority(gdma_dev_t *dev, uint32_t channel, ui
/**
* @brief Connect DMA RX channel to a given peripheral
*/
static inline void gdma_ll_rx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id)
static inline void gdma_ll_rx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, int periph_id)
{
dev->channel[channel].in.in_peri_sel.peri_in_sel_chn = periph_id;
dev->channel[channel].in.in_conf0.mem_trans_en_chn = (periph == GDMA_TRIG_PERIPH_M2M);
dev->channel[channel].in.in_conf0.mem_trans_en_chn = false;
}
/**
* @brief Disconnect DMA RX channel from peripheral
* @brief Connect DMA RX channel to memory (M2M mode)
*/
static inline void gdma_ll_rx_disconnect_from_periph(gdma_dev_t *dev, uint32_t channel)
static inline void gdma_ll_rx_connect_to_mem(gdma_dev_t *dev, uint32_t channel, int dummy_id)
{
dev->channel[channel].in.in_peri_sel.peri_in_sel_chn = GDMA_LL_INVALID_PERIPH_ID;
dev->channel[channel].in.in_peri_sel.peri_in_sel_chn = dummy_id;
dev->channel[channel].in.in_conf0.mem_trans_en_chn = true;
}
/**
* @brief Disconnect DMA RX channel from all peripherals
*/
static inline void gdma_ll_rx_disconnect_all(gdma_dev_t *dev, uint32_t channel)
{
dev->channel[channel].in.in_peri_sel.peri_in_sel_chn = 0x3F;
dev->channel[channel].in.in_conf0.mem_trans_en_chn = false;
}
@@ -564,18 +572,25 @@ static inline void gdma_ll_tx_set_priority(gdma_dev_t *dev, uint32_t channel, ui
/**
* @brief Connect DMA TX channel to a given peripheral
*/
static inline void gdma_ll_tx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id)
static inline void gdma_ll_tx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, int periph_id)
{
(void)periph;
dev->channel[channel].out.out_peri_sel.peri_out_sel_chn = periph_id;
}
/**
* @brief Disconnect DMA TX channel from peripheral
* @brief Connect DMA TX channel to memory (M2M mode)
*/
static inline void gdma_ll_tx_disconnect_from_periph(gdma_dev_t *dev, uint32_t channel)
static inline void gdma_ll_tx_connect_to_mem(gdma_dev_t *dev, uint32_t channel, int dummy_id)
{
dev->channel[channel].out.out_peri_sel.peri_out_sel_chn = GDMA_LL_INVALID_PERIPH_ID;
dev->channel[channel].out.out_peri_sel.peri_out_sel_chn = dummy_id;
}
/**
* @brief Disconnect DMA TX channel from all peripherals
*/
static inline void gdma_ll_tx_disconnect_all(gdma_dev_t *dev, uint32_t channel)
{
dev->channel[channel].out.out_peri_sel.peri_out_sel_chn = 0x3F;
}
/**
components/esp_hal_dma/esp32h4/include/hal/ahb_dma_ll.h
+26 -11
View File
@@ -28,7 +28,6 @@ extern "C" {
// any "dummy" peripheral ID can be used for M2M mode
#define AHB_DMA_LL_M2M_FREE_PERIPH_ID_MASK (0xFC00)
#define AHB_DMA_LL_INVALID_PERIPH_ID (0x3F)
#define GDMA_LL_EVENT_TX_FIFO_UDF (1<<5)
#define GDMA_LL_EVENT_TX_FIFO_OVF (1<<4)
@@ -392,18 +391,27 @@ static inline void ahb_dma_ll_rx_set_priority(ahb_dma_dev_t *dev, uint32_t chann
/**
* @brief Connect DMA RX channel to a given peripheral
*/
static inline void ahb_dma_ll_rx_connect_to_periph(ahb_dma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id)
static inline void ahb_dma_ll_rx_connect_to_periph(ahb_dma_dev_t *dev, uint32_t channel, int periph_id)
{
dev->channel[channel].in.in_peri_sel.dma_peri_in_sel_chn = periph_id;
dev->channel[channel].in.in_conf0.dma_mem_trans_en_chn = (periph == GDMA_TRIG_PERIPH_M2M);
dev->channel[channel].in.in_conf0.dma_mem_trans_en_chn = false;
}
/**
* @brief Disconnect DMA RX channel from peripheral
* @brief Connect DMA RX channel to memory (M2M mode)
*/
static inline void ahb_dma_ll_rx_disconnect_from_periph(ahb_dma_dev_t *dev, uint32_t channel)
static inline void ahb_dma_ll_rx_connect_to_mem(ahb_dma_dev_t *dev, uint32_t channel, int dummy_id)
{
dev->channel[channel].in.in_peri_sel.dma_peri_in_sel_chn = AHB_DMA_LL_INVALID_PERIPH_ID;
dev->channel[channel].in.in_peri_sel.dma_peri_in_sel_chn = dummy_id;
dev->channel[channel].in.in_conf0.dma_mem_trans_en_chn = true;
}
/**
* @brief Disconnect DMA RX channel from all peripherals
*/
static inline void ahb_dma_ll_rx_disconnect_all(ahb_dma_dev_t *dev, uint32_t channel)
{
dev->channel[channel].in.in_peri_sel.dma_peri_in_sel_chn = 0x3F;
dev->channel[channel].in.in_conf0.dma_mem_trans_en_chn = false;
}
@@ -644,18 +652,25 @@ static inline void ahb_dma_ll_tx_set_priority(ahb_dma_dev_t *dev, uint32_t chann
/**
* @brief Connect DMA TX channel to a given peripheral
*/
static inline void ahb_dma_ll_tx_connect_to_periph(ahb_dma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id)
static inline void ahb_dma_ll_tx_connect_to_periph(ahb_dma_dev_t *dev, uint32_t channel, int periph_id)
{
(void)periph;
dev->channel[channel].out.out_peri_sel.dma_peri_out_sel_chn = periph_id;
}
/**
* @brief Disconnect DMA TX channel from peripheral
* @brief Connect DMA TX channel to memory (M2M mode)
*/
static inline void ahb_dma_ll_tx_disconnect_from_periph(ahb_dma_dev_t *dev, uint32_t channel)
static inline void ahb_dma_ll_tx_connect_to_mem(ahb_dma_dev_t *dev, uint32_t channel, int dummy_id)
{
dev->channel[channel].out.out_peri_sel.dma_peri_out_sel_chn = AHB_DMA_LL_INVALID_PERIPH_ID;
dev->channel[channel].out.out_peri_sel.dma_peri_out_sel_chn = dummy_id;
}
/**
* @brief Disconnect DMA TX channel from all peripherals
*/
static inline void ahb_dma_ll_tx_disconnect_all(ahb_dma_dev_t *dev, uint32_t channel)
{
dev->channel[channel].out.out_peri_sel.dma_peri_out_sel_chn = 0x3F;
}
/**
components/esp_hal_dma/esp32p4/include/hal/ahb_dma_ll.h
+24 -9
View File
@@ -24,7 +24,6 @@ extern "C" {
// any "dummy" peripheral ID can be used for M2M mode
#define AHB_DMA_LL_M2M_FREE_PERIPH_ID_MASK (0xFAC2)
#define AHB_DMA_LL_INVALID_PERIPH_ID (0x3F)
///////////////////////////////////// Common /////////////////////////////////////////
/**
@@ -325,16 +324,25 @@ static inline void ahb_dma_ll_rx_set_priority(ahb_dma_dev_t *dev, uint32_t chann
/**
* @brief Connect DMA RX channel to a given peripheral
*/
static inline void ahb_dma_ll_rx_connect_to_periph(ahb_dma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id)
static inline void ahb_dma_ll_rx_connect_to_periph(ahb_dma_dev_t *dev, uint32_t channel, int periph_id)
{
dev->channel[channel].in.in_peri_sel.peri_in_sel_chn = periph_id;
dev->channel[channel].in.in_conf0.mem_trans_en_chn = (periph == GDMA_TRIG_PERIPH_M2M);
dev->channel[channel].in.in_conf0.mem_trans_en_chn = false;
}
/**
* @brief Disconnect DMA RX channel from peripheral
* @brief Connect DMA RX channel to memory (M2M mode)
*/
static inline void ahb_dma_ll_rx_disconnect_from_periph(ahb_dma_dev_t *dev, uint32_t channel)
static inline void ahb_dma_ll_rx_connect_to_mem(ahb_dma_dev_t *dev, uint32_t channel, int dummy_id)
{
dev->channel[channel].in.in_peri_sel.peri_in_sel_chn = dummy_id;
dev->channel[channel].in.in_conf0.mem_trans_en_chn = true;
}
/**
* @brief Disconnect DMA RX channel from all peripherals
*/
static inline void ahb_dma_ll_rx_disconnect_all(ahb_dma_dev_t *dev, uint32_t channel)
{
dev->channel[channel].in.in_peri_sel.peri_in_sel_chn = 0x3F;
dev->channel[channel].in.in_conf0.mem_trans_en_chn = false;
@@ -606,16 +614,23 @@ static inline void ahb_dma_ll_tx_set_priority(ahb_dma_dev_t *dev, uint32_t chann
/**
* @brief Connect DMA TX channel to a given peripheral
*/
static inline void ahb_dma_ll_tx_connect_to_periph(ahb_dma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id)
static inline void ahb_dma_ll_tx_connect_to_periph(ahb_dma_dev_t *dev, uint32_t channel, int periph_id)
{
(void)periph;
dev->channel[channel].out.out_peri_sel.peri_out_sel_chn = periph_id;
}
/**
* @brief Disconnect DMA TX channel from peripheral
* @brief Connect DMA TX channel to memory (M2M mode)
*/
static inline void ahb_dma_ll_tx_disconnect_from_periph(ahb_dma_dev_t *dev, uint32_t channel)
static inline void ahb_dma_ll_tx_connect_to_mem(ahb_dma_dev_t *dev, uint32_t channel, int dummy_id)
{
dev->channel[channel].out.out_peri_sel.peri_out_sel_chn = dummy_id;
}
/**
* @brief Disconnect DMA TX channel from all peripherals
*/
static inline void ahb_dma_ll_tx_disconnect_all(ahb_dma_dev_t *dev, uint32_t channel)
{
dev->channel[channel].out.out_peri_sel.peri_out_sel_chn = 0x3F;
}
components/esp_hal_dma/esp32p4/include/hal/axi_dma_ll.h
+24 -9
View File
@@ -24,7 +24,6 @@ extern "C" {
// any "dummy" peripheral ID can be used for M2M mode
#define AXI_DMA_LL_M2M_FREE_PERIPH_ID_MASK (0xFFC0)
#define AXI_DMA_LL_INVALID_PERIPH_ID (0x3F)
///////////////////////////////////// Common /////////////////////////////////////////
/**
@@ -267,16 +266,25 @@ static inline void axi_dma_ll_rx_set_priority(axi_dma_dev_t *dev, uint32_t chann
/**
* @brief Connect DMA RX channel to a given peripheral
*/
static inline void axi_dma_ll_rx_connect_to_periph(axi_dma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id)
static inline void axi_dma_ll_rx_connect_to_periph(axi_dma_dev_t *dev, uint32_t channel, int periph_id)
{
dev->in[channel].conf.in_peri_sel.peri_in_sel_chn = periph_id;
dev->in[channel].conf.in_conf0.mem_trans_en_chn = (periph == GDMA_TRIG_PERIPH_M2M);
dev->in[channel].conf.in_conf0.mem_trans_en_chn = false;
}
/**
* @brief Disconnect DMA RX channel from peripheral
* @brief Connect DMA RX channel to memory (M2M mode)
*/
static inline void axi_dma_ll_rx_disconnect_from_periph(axi_dma_dev_t *dev, uint32_t channel)
static inline void axi_dma_ll_rx_connect_to_mem(axi_dma_dev_t *dev, uint32_t channel, int dummy_id)
{
dev->in[channel].conf.in_peri_sel.peri_in_sel_chn = dummy_id;
dev->in[channel].conf.in_conf0.mem_trans_en_chn = true;
}
/**
* @brief Disconnect DMA RX channel from all peripherals
*/
static inline void axi_dma_ll_rx_disconnect_all(axi_dma_dev_t *dev, uint32_t channel)
{
dev->in[channel].conf.in_peri_sel.peri_in_sel_chn = 0x3F;
dev->in[channel].conf.in_conf0.mem_trans_en_chn = false;
@@ -502,16 +510,23 @@ static inline void axi_dma_ll_tx_set_priority(axi_dma_dev_t *dev, uint32_t chann
/**
* @brief Connect DMA TX channel to a given peripheral
*/
static inline void axi_dma_ll_tx_connect_to_periph(axi_dma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id)
static inline void axi_dma_ll_tx_connect_to_periph(axi_dma_dev_t *dev, uint32_t channel, int periph_id)
{
(void)periph;
dev->out[channel].conf.out_peri_sel.peri_out_sel_chn = periph_id;
}
/**
* @brief Disconnect DMA TX channel from peripheral
* @brief Connect DMA TX channel to memory (M2M mode)
*/
static inline void axi_dma_ll_tx_disconnect_from_periph(axi_dma_dev_t *dev, uint32_t channel)
static inline void axi_dma_ll_tx_connect_to_mem(axi_dma_dev_t *dev, uint32_t channel, int dummy_id)
{
dev->out[channel].conf.out_peri_sel.peri_out_sel_chn = dummy_id;
}
/**
* @brief Disconnect DMA TX channel from all peripherals
*/
static inline void axi_dma_ll_tx_disconnect_all(axi_dma_dev_t *dev, uint32_t channel)
{
dev->out[channel].conf.out_peri_sel.peri_out_sel_chn = 0x3F;
}
components/esp_hal_dma/esp32s3/include/hal/gdma_ll.h
+26 -11
View File
@@ -32,7 +32,6 @@ extern "C" {
// any "valid" peripheral ID can be used for M2M mode
#define GDMA_LL_M2M_FREE_PERIPH_ID_MASK (0x3FF)
#define GDMA_LL_INVALID_PERIPH_ID (0x3F)
#define GDMA_LL_EVENT_TX_L3_FIFO_UDF (1<<7)
#define GDMA_LL_EVENT_TX_L3_FIFO_OVF (1<<6)
@@ -371,18 +370,27 @@ static inline void gdma_ll_rx_set_priority(gdma_dev_t *dev, uint32_t channel, ui
/**
* @brief Connect DMA RX channel to a given peripheral
*/
static inline void gdma_ll_rx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id)
static inline void gdma_ll_rx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, int periph_id)
{
dev->channel[channel].in.peri_sel.sel = periph_id;
dev->channel[channel].in.conf0.mem_trans_en = (periph == GDMA_TRIG_PERIPH_M2M);
dev->channel[channel].in.conf0.mem_trans_en = false;
}
/**
* @brief Disconnect DMA RX channel from peripheral
* @brief Connect DMA RX channel to memory (M2M mode)
*/
static inline void gdma_ll_rx_disconnect_from_periph(gdma_dev_t *dev, uint32_t channel)
static inline void gdma_ll_rx_connect_to_mem(gdma_dev_t *dev, uint32_t channel, int dummy_id)
{
dev->channel[channel].in.peri_sel.sel = GDMA_LL_INVALID_PERIPH_ID;
dev->channel[channel].in.peri_sel.sel = dummy_id;
dev->channel[channel].in.conf0.mem_trans_en = true;
}
/**
* @brief Disconnect DMA RX channel from peripheral/memory
*/
static inline void gdma_ll_rx_disconnect_all(gdma_dev_t *dev, uint32_t channel)
{
dev->channel[channel].in.peri_sel.sel = 0x3F;
dev->channel[channel].in.conf0.mem_trans_en = false;
}
@@ -630,18 +638,25 @@ static inline void gdma_ll_tx_set_priority(gdma_dev_t *dev, uint32_t channel, ui
/**
* @brief Connect DMA TX channel to a given peripheral
*/
static inline void gdma_ll_tx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id)
static inline void gdma_ll_tx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, int periph_id)
{
(void)periph;
dev->channel[channel].out.peri_sel.sel = periph_id;
}
/**
* @brief Disconnect DMA TX channel from peripheral
* @brief Connect DMA TX channel to memory (M2M mode)
*/
static inline void gdma_ll_tx_disconnect_from_periph(gdma_dev_t *dev, uint32_t channel)
static inline void gdma_ll_tx_connect_to_mem(gdma_dev_t *dev, uint32_t channel, int dummy_id)
{
dev->channel[channel].out.peri_sel.sel = GDMA_LL_INVALID_PERIPH_ID;
dev->channel[channel].out.peri_sel.sel = dummy_id;
}
/**
* @brief Disconnect DMA TX channel from all peripherals
*/
static inline void gdma_ll_tx_disconnect_all(gdma_dev_t *dev, uint32_t channel)
{
dev->channel[channel].out.peri_sel.sel = 0x3F;
}
#ifdef __cplusplus
components/esp_hal_dma/gdma_hal_ahb_v1.c
+17 -9
View File
@@ -60,23 +60,30 @@ void gdma_ahb_hal_set_priority(gdma_hal_context_t *hal, int chan_id, gdma_channe
}
}
void gdma_ahb_hal_connect_peri(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, gdma_trigger_peripheral_t periph, int periph_sub_id)
void gdma_ahb_hal_connect_peri(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, int periph_id)
{
if (dir == GDMA_CHANNEL_DIRECTION_RX) {
gdma_ll_rx_reset_channel(hal->dev, chan_id); // reset channel
gdma_ll_rx_connect_to_periph(hal->dev, chan_id, periph, periph_sub_id);
gdma_ll_rx_connect_to_periph(hal->dev, chan_id, periph_id);
} else {
gdma_ll_tx_reset_channel(hal->dev, chan_id); // reset channel
gdma_ll_tx_connect_to_periph(hal->dev, chan_id, periph, periph_sub_id);
gdma_ll_tx_connect_to_periph(hal->dev, chan_id, periph_id);
}
}
void gdma_ahb_hal_disconnect_peri(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
void gdma_ahb_hal_connect_mem(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, int dummy_id)
{
if (dir == GDMA_CHANNEL_DIRECTION_RX) {
gdma_ll_rx_disconnect_from_periph(hal->dev, chan_id);
gdma_ll_rx_connect_to_mem(hal->dev, chan_id, dummy_id);
} else {
gdma_ll_tx_disconnect_from_periph(hal->dev, chan_id);
gdma_ll_tx_connect_to_mem(hal->dev, chan_id, dummy_id);
}
}
void gdma_ahb_hal_disconnect_all(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
{
if (dir == GDMA_CHANNEL_DIRECTION_RX) {
gdma_ll_rx_disconnect_all(hal->dev, chan_id);
} else {
gdma_ll_tx_disconnect_all(hal->dev, chan_id);
}
}
@@ -184,7 +191,8 @@ void gdma_ahb_hal_init(gdma_hal_context_t *hal, const gdma_hal_config_t *config)
hal->reset = gdma_ahb_hal_reset;
hal->set_priority = gdma_ahb_hal_set_priority;
hal->connect_peri = gdma_ahb_hal_connect_peri;
hal->disconnect_peri = gdma_ahb_hal_disconnect_peri;
hal->connect_mem = gdma_ahb_hal_connect_mem;
hal->disconnect_all = gdma_ahb_hal_disconnect_all;
hal->enable_burst = gdma_ahb_hal_enable_burst;
hal->set_strategy = gdma_ahb_hal_set_strategy;
hal->enable_intr = gdma_ahb_hal_enable_intr;
components/esp_hal_dma/gdma_hal_ahb_v2.c
+17 -9
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@@ -61,23 +61,30 @@ void gdma_ahb_hal_set_priority(gdma_hal_context_t *hal, int chan_id, gdma_channe
}
}
void gdma_ahb_hal_connect_peri(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, gdma_trigger_peripheral_t periph, int periph_sub_id)
void gdma_ahb_hal_connect_peri(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, int periph_id)
{
if (dir == GDMA_CHANNEL_DIRECTION_RX) {
ahb_dma_ll_rx_reset_channel(hal->ahb_dma_dev, chan_id); // reset channel
ahb_dma_ll_rx_connect_to_periph(hal->ahb_dma_dev, chan_id, periph, periph_sub_id);
ahb_dma_ll_rx_connect_to_periph(hal->ahb_dma_dev, chan_id, periph_id);
} else {
ahb_dma_ll_tx_reset_channel(hal->ahb_dma_dev, chan_id); // reset channel
ahb_dma_ll_tx_connect_to_periph(hal->ahb_dma_dev, chan_id, periph, periph_sub_id);
ahb_dma_ll_tx_connect_to_periph(hal->ahb_dma_dev, chan_id, periph_id);
}
}
void gdma_ahb_hal_disconnect_peri(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
void gdma_ahb_hal_connect_mem(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, int dummy_id)
{
if (dir == GDMA_CHANNEL_DIRECTION_RX) {
ahb_dma_ll_rx_disconnect_from_periph(hal->ahb_dma_dev, chan_id);
ahb_dma_ll_rx_connect_to_mem(hal->ahb_dma_dev, chan_id, dummy_id);
} else {
ahb_dma_ll_tx_disconnect_from_periph(hal->ahb_dma_dev, chan_id);
ahb_dma_ll_tx_connect_to_mem(hal->ahb_dma_dev, chan_id, dummy_id);
}
}
void gdma_ahb_hal_disconnect_all(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
{
if (dir == GDMA_CHANNEL_DIRECTION_RX) {
ahb_dma_ll_rx_disconnect_all(hal->ahb_dma_dev, chan_id);
} else {
ahb_dma_ll_tx_disconnect_all(hal->ahb_dma_dev, chan_id);
}
}
@@ -253,7 +260,8 @@ void gdma_ahb_hal_init(gdma_hal_context_t *hal, const gdma_hal_config_t *config)
hal->reset = gdma_ahb_hal_reset;
hal->set_priority = gdma_ahb_hal_set_priority;
hal->connect_peri = gdma_ahb_hal_connect_peri;
hal->disconnect_peri = gdma_ahb_hal_disconnect_peri;
hal->connect_mem = gdma_ahb_hal_connect_mem;
hal->disconnect_all = gdma_ahb_hal_disconnect_all;
hal->enable_burst = gdma_ahb_hal_enable_burst;
hal->set_strategy = gdma_ahb_hal_set_strategy;
hal->enable_intr = gdma_ahb_hal_enable_intr;
components/esp_hal_dma/gdma_hal_axi.c
+17 -9
View File
@@ -61,23 +61,30 @@ void gdma_axi_hal_set_priority(gdma_hal_context_t *hal, int chan_id, gdma_channe
}
}
void gdma_axi_hal_connect_peri(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, gdma_trigger_peripheral_t periph, int periph_sub_id)
void gdma_axi_hal_connect_peri(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, int periph_id)
{
if (dir == GDMA_CHANNEL_DIRECTION_RX) {
axi_dma_ll_rx_reset_channel(hal->axi_dma_dev, chan_id); // reset channel
axi_dma_ll_rx_connect_to_periph(hal->axi_dma_dev, chan_id, periph, periph_sub_id);
axi_dma_ll_rx_connect_to_periph(hal->axi_dma_dev, chan_id, periph_id);
} else {
axi_dma_ll_tx_reset_channel(hal->axi_dma_dev, chan_id); // reset channel
axi_dma_ll_tx_connect_to_periph(hal->axi_dma_dev, chan_id, periph, periph_sub_id);
axi_dma_ll_tx_connect_to_periph(hal->axi_dma_dev, chan_id, periph_id);
}
}
void gdma_axi_hal_disconnect_peri(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
void gdma_axi_hal_connect_mem(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, int dummy_id)
{
if (dir == GDMA_CHANNEL_DIRECTION_RX) {
axi_dma_ll_rx_disconnect_from_periph(hal->axi_dma_dev, chan_id);
axi_dma_ll_rx_connect_to_mem(hal->axi_dma_dev, chan_id, dummy_id);
} else {
axi_dma_ll_tx_disconnect_from_periph(hal->axi_dma_dev, chan_id);
axi_dma_ll_tx_connect_to_mem(hal->axi_dma_dev, chan_id, dummy_id);
}
}
void gdma_axi_hal_disconnect_all(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
{
if (dir == GDMA_CHANNEL_DIRECTION_RX) {
axi_dma_ll_rx_disconnect_all(hal->axi_dma_dev, chan_id);
} else {
axi_dma_ll_tx_disconnect_all(hal->axi_dma_dev, chan_id);
}
}
@@ -249,7 +256,8 @@ void gdma_axi_hal_init(gdma_hal_context_t *hal, const gdma_hal_config_t *config)
hal->reset = gdma_axi_hal_reset;
hal->set_priority = gdma_axi_hal_set_priority;
hal->connect_peri = gdma_axi_hal_connect_peri;
hal->disconnect_peri = gdma_axi_hal_disconnect_peri;
hal->connect_mem = gdma_axi_hal_connect_mem;
hal->disconnect_all = gdma_axi_hal_disconnect_all;
hal->enable_burst = gdma_axi_hal_enable_burst;
hal->set_strategy = gdma_axi_hal_set_strategy;
hal->enable_intr = gdma_axi_hal_enable_intr;
components/esp_hal_dma/gdma_hal_top.c
+9 -4
View File
@@ -38,14 +38,19 @@ void gdma_hal_set_priority(gdma_hal_context_t *hal, int chan_id, gdma_channel_di
hal->set_priority(hal, chan_id, dir, priority);
}
void gdma_hal_connect_peri(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, gdma_trigger_peripheral_t periph, int periph_sub_id)
void gdma_hal_connect_peri(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, int periph_id)
{
hal->connect_peri(hal, chan_id, dir, periph, periph_sub_id);
hal->connect_peri(hal, chan_id, dir, periph_id);
}
void gdma_hal_disconnect_peri(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
void gdma_hal_connect_mem(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, int dummy_id)
{
hal->disconnect_peri(hal, chan_id, dir);
hal->connect_mem(hal, chan_id, dir, dummy_id);
}
void gdma_hal_disconnect_all(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
{
hal->disconnect_all(hal, chan_id, dir);
}
void gdma_hal_enable_burst(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_data_burst, bool en_desc_burst)
components/esp_hal_dma/include/hal/gdma_hal.h
+7 -4
View File
@@ -80,8 +80,9 @@ struct gdma_hal_context_t {
void (*append)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir); /// Append a descriptor to the channel
void (*reset)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir); /// Reset the channel
void (*set_priority)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t priority); /// Set the channel priority
void (*connect_peri)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, gdma_trigger_peripheral_t periph, int periph_sub_id); /// Connect the channel to a peripheral
void (*disconnect_peri)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir); /// Disconnect the channel from a peripheral
void (*connect_peri)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, int periph_id); /// Connect the channel to a peripheral
void (*connect_mem)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, int dummy_id); /// Connect the channel to memory (for M2M)
void (*disconnect_all)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir); /// Disconnect the channel from all peripherals/memory
void (*enable_burst)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_data_burst, bool en_desc_burst); /// Enable burst mode
void (*set_burst_size)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t burst_sz); /// Set burst transfer size
void (*set_strategy)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_owner_check, bool en_desc_write_back, bool eof_till_popped); /// Set some misc strategy of the channel behaviour
@@ -116,9 +117,11 @@ void gdma_hal_reset(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction
void gdma_hal_set_priority(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t priority);
void gdma_hal_connect_peri(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, gdma_trigger_peripheral_t periph, int periph_sub_id);
void gdma_hal_connect_peri(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, int periph_id);
void gdma_hal_disconnect_peri(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir);
void gdma_hal_connect_mem(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, int dummy_id);
void gdma_hal_disconnect_all(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir);
void gdma_hal_enable_burst(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_data_burst, bool en_desc_burst);
components/esp_hal_dma/include/hal/gdma_hal_ahb.h
+4 -2
View File
@@ -22,9 +22,11 @@ void gdma_ahb_hal_reset(gdma_hal_context_t *hal, int chan_id, gdma_channel_direc
void gdma_ahb_hal_set_priority(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t priority);
void gdma_ahb_hal_connect_peri(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, gdma_trigger_peripheral_t periph, int periph_sub_id);
void gdma_ahb_hal_connect_peri(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, int periph_id);
void gdma_ahb_hal_disconnect_peri(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir);
void gdma_ahb_hal_connect_mem(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, int dummy_id);
void gdma_ahb_hal_disconnect_all(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir);
void gdma_ahb_hal_enable_burst(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_data_burst, bool en_desc_burst);
components/esp_hal_dma/include/hal/gdma_hal_axi.h
+4 -2
View File
@@ -22,9 +22,11 @@ void gdma_axi_hal_reset(gdma_hal_context_t *hal, int chan_id, gdma_channel_direc
void gdma_axi_hal_set_priority(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t priority);
void gdma_axi_hal_connect_peri(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, gdma_trigger_peripheral_t periph, int periph_sub_id);
void gdma_axi_hal_connect_peri(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, int periph_id);
void gdma_axi_hal_disconnect_peri(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir);
void gdma_axi_hal_connect_mem(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, int dummy_id);
void gdma_axi_hal_disconnect_all(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir);
void gdma_axi_hal_enable_burst(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_data_burst, bool en_desc_burst);
components/esp_hw_support/dma/async_memcpy_gdma.c
+2
View File
@@ -122,6 +122,8 @@ static esp_err_t esp_async_memcpy_install_gdma_template(const async_memcpy_confi
gdma_channel_alloc_config_t channel_config = {0};
ESP_GOTO_ON_ERROR(new_channel_func(&channel_config, &mcp_gdma->tx_channel, &mcp_gdma->rx_channel), err, TAG, "failed to alloc GDMA channels");
gdma_reset(mcp_gdma->tx_channel);
gdma_reset(mcp_gdma->rx_channel);
// get a free DMA trigger ID for memory copy
gdma_trigger_t m2m_trigger = GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_M2M, 0);
uint32_t free_m2m_id_mask = 0;
components/esp_hw_support/dma/gdma.c
+7 -2
View File
@@ -333,7 +333,12 @@ esp_err_t gdma_connect(gdma_channel_handle_t dma_chan, gdma_trigger_t trig_perip
}
ESP_RETURN_ON_FALSE(!periph_conflict, ESP_ERR_INVALID_STATE, TAG, "peripheral %d is already used by another channel", trig_periph.instance_id);
gdma_hal_connect_peri(hal, pair->pair_id, dma_chan->direction, trig_periph.periph, trig_periph.instance_id);
if (trig_periph.bus_id == SOC_GDMA_TRIG_PERIPH_M2M0_BUS) {
// M2M transfer
gdma_hal_connect_mem(hal, pair->pair_id, dma_chan->direction, trig_periph.instance_id);
} else {
gdma_hal_connect_peri(hal, pair->pair_id, dma_chan->direction, trig_periph.instance_id);
}
dma_chan->periph_id = trig_periph.instance_id;
return ESP_OK;
}
@@ -362,7 +367,7 @@ esp_err_t gdma_disconnect(gdma_channel_handle_t dma_chan)
}
}
gdma_hal_disconnect_peri(hal, pair->pair_id, dma_chan->direction);
gdma_hal_disconnect_all(hal, pair->pair_id, dma_chan->direction);
dma_chan->periph_id = GDMA_INVALID_PERIPH_TRIG;
return ESP_OK;
components/esp_hw_support/dma/include/esp_private/gdma.h
+3 -6
View File
@@ -82,19 +82,16 @@ typedef struct {
*
*/
typedef struct {
gdma_trigger_peripheral_t periph; /*!< Target peripheral which will trigger DMA operations */
int instance_id; /*!< Peripheral instance ID. Supported IDs are listed in `hal/gdma_channel.h`, e.g. SOC_GDMA_TRIG_PERIPH_UHCI0 */
int bus_id; /*!< Which system bus should the DMA attached to */
} gdma_trigger_t;
/**
* @brief Helper macro to initialize GDMA trigger
* @note value of `peri` must be selected from `gdma_trigger_peripheral_t` enum.
* e.g. GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_I2S,0)
*
* @example
* GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_SPI,2)
*/
#define GDMA_MAKE_TRIGGER(peri, id) \
(gdma_trigger_t) { .periph = peri, .instance_id = SOC_##peri##id, .bus_id = SOC_##peri##id##_BUS }
#define GDMA_MAKE_TRIGGER(peri, id) (gdma_trigger_t) {.instance_id = SOC_##peri##id, .bus_id = SOC_##peri##id##_BUS }
/**
* @brief A collection of strategy item that each GDMA channel could apply
components/esp_hw_support/test_apps/dma/main/test_gdma.c
-4
View File
@@ -67,12 +67,10 @@ TEST_CASE("GDMA channel allocation", "[GDMA]")
TEST_ESP_OK(gdma_new_ahb_channel(&channel_config, NULL, &rx_channels[0]));
gdma_trigger_t fake_ahb_trigger1 = {
.periph = 1,
.bus_id = SOC_GDMA_BUS_AHB,
.instance_id = 0,
};
gdma_trigger_t fake_ahb_trigger2 = {
.periph = 2,
.bus_id = SOC_GDMA_BUS_AHB,
.instance_id = 1,
};
@@ -126,12 +124,10 @@ TEST_CASE("GDMA channel allocation", "[GDMA]")
TEST_ESP_OK(gdma_new_axi_channel(&channel_config, NULL, &rx_channels[0]));
gdma_trigger_t fake_axi_trigger1 = {
.periph = 1,
.bus_id = SOC_GDMA_BUS_AXI,
.instance_id = 0,
};
gdma_trigger_t fake_axi_trigger2 = {
.periph = 2,
.bus_id = SOC_GDMA_BUS_AXI,
.instance_id = 1,
};
components/hal/include/hal/gdma_types.h
-20
View File
@@ -14,26 +14,6 @@
extern "C" {
#endif
/**
* @brief Enumeration of peripherals which have the DMA capability
* @note Some peripheral might not be available on certain chip, please refer to `soc_caps.h` for detail.
*/
typedef enum {
GDMA_TRIG_PERIPH_M2M, /*!< GDMA trigger peripheral: M2M */
GDMA_TRIG_PERIPH_UHCI, /*!< GDMA trigger peripheral: UHCI */
GDMA_TRIG_PERIPH_SPI, /*!< GDMA trigger peripheral: SPI */
GDMA_TRIG_PERIPH_I2S, /*!< GDMA trigger peripheral: I2S */
GDMA_TRIG_PERIPH_AES, /*!< GDMA trigger peripheral: AES */
GDMA_TRIG_PERIPH_SHA, /*!< GDMA trigger peripheral: SHA */
GDMA_TRIG_PERIPH_ADC, /*!< GDMA trigger peripheral: ADC */
GDMA_TRIG_PERIPH_DAC, /*!< GDMA trigger peripheral: DAC */
GDMA_TRIG_PERIPH_LCD, /*!< GDMA trigger peripheral: LCD */
GDMA_TRIG_PERIPH_CAM, /*!< GDMA trigger peripheral: CAM */
GDMA_TRIG_PERIPH_RMT, /*!< GDMA trigger peripheral: RMT */
GDMA_TRIG_PERIPH_PARLIO, /*!< GDMA trigger peripheral: PARLIO */
GDMA_TRIG_PERIPH_I3C, /*!< GDMA trigger peripheral: I3C */
} gdma_trigger_peripheral_t;
/**
* @brief Enumeration of GDMA channel direction
*/
components/hal/test_apps/tee/components/pms_and_cpu_intr/src/common/test_setup_utils.c
+6 -6
View File
@@ -96,8 +96,8 @@ void test_switch_lp_mem_speed(bool high_speed)
#define dma_ll_tx_connect_to_periph DMA_LL_FUNC(tx_connect_to_periph)
#define dma_ll_rx_reset_channel DMA_LL_FUNC(rx_reset_channel)
#define dma_ll_rx_connect_to_periph DMA_LL_FUNC(rx_connect_to_periph)
#define dma_ll_tx_disconnect_from_periph DMA_LL_FUNC(tx_disconnect_from_periph)
#define dma_ll_rx_disconnect_from_periph DMA_LL_FUNC(rx_disconnect_from_periph)
#define dma_ll_tx_disconnect_all DMA_LL_FUNC(tx_disconnect_all)
#define dma_ll_rx_disconnect_all DMA_LL_FUNC(rx_disconnect_all)
#define dma_ll_tx_set_desc_addr DMA_LL_FUNC(tx_set_desc_addr)
#define dma_ll_tx_start DMA_LL_FUNC(tx_start)
#define dma_ll_rx_set_desc_addr DMA_LL_FUNC(rx_set_desc_addr)
@@ -181,8 +181,8 @@ void test_gdma_init(void)
dma_ll_tx_set_priority(&TEST_DMA_DEV, TEST_DMA_CHN_NUM, 1);
dma_ll_rx_set_priority(&TEST_DMA_DEV, TEST_DMA_CHN_NUM, 1);
dma_ll_tx_connect_to_periph(&TEST_DMA_DEV, TEST_DMA_CHN_NUM, SOC_GDMA_TRIG_PERIPH_SPI2, SOC_GDMA_TRIG_PERIPH_SPI2);
dma_ll_rx_connect_to_periph(&TEST_DMA_DEV, TEST_DMA_CHN_NUM, SOC_GDMA_TRIG_PERIPH_SPI2, SOC_GDMA_TRIG_PERIPH_SPI2);
dma_ll_tx_connect_to_periph(&TEST_DMA_DEV, TEST_DMA_CHN_NUM, SOC_GDMA_TRIG_PERIPH_SPI2);
dma_ll_rx_connect_to_periph(&TEST_DMA_DEV, TEST_DMA_CHN_NUM, SOC_GDMA_TRIG_PERIPH_SPI2);
TEST_DMA_DEV.channel[TEST_DMA_CHN_NUM].in.in_conf0.DMA_MEM_TRANS_EN_FIELD = 1;
dma_ll_tx_enable_interrupt(&TEST_DMA_DEV, TEST_DMA_CHN_NUM, GDMA_LL_EVENT_TX_EOF, true);
@@ -194,8 +194,8 @@ void test_gdma_deinit(void)
dma_ll_tx_stop(&TEST_DMA_DEV, TEST_DMA_CHN_NUM);
dma_ll_rx_stop(&TEST_DMA_DEV, TEST_DMA_CHN_NUM);
dma_ll_tx_disconnect_from_periph(&TEST_DMA_DEV, TEST_DMA_CHN_NUM);
dma_ll_rx_disconnect_from_periph(&TEST_DMA_DEV, TEST_DMA_CHN_NUM);
dma_ll_tx_disconnect_all(&TEST_DMA_DEV, TEST_DMA_CHN_NUM);
dma_ll_rx_disconnect_all(&TEST_DMA_DEV, TEST_DMA_CHN_NUM);
dma_ll_tx_reset_channel(&TEST_DMA_DEV, TEST_DMA_CHN_NUM);
dma_ll_rx_reset_channel(&TEST_DMA_DEV, TEST_DMA_CHN_NUM);
components/mbedtls/esp_tee/esp_tee_crypto_shared_gdma.c
+17 -15
View File
@@ -36,10 +36,12 @@
#define dma_ll_rx_enable_descriptor_burst DMA_LL_FUNC(rx_enable_descriptor_burst)
#define dma_ll_tx_reset_channel DMA_LL_FUNC(tx_reset_channel)
#define dma_ll_tx_connect_to_periph DMA_LL_FUNC(tx_connect_to_periph)
#define dma_ll_tx_connect_to_memory DMA_LL_FUNC(tx_connect_to_mem)
#define dma_ll_rx_reset_channel DMA_LL_FUNC(rx_reset_channel)
#define dma_ll_rx_connect_to_periph DMA_LL_FUNC(rx_connect_to_periph)
#define dma_ll_tx_disconnect_from_periph DMA_LL_FUNC(tx_disconnect_from_periph)
#define dma_ll_rx_disconnect_from_periph DMA_LL_FUNC(rx_disconnect_from_periph)
#define dma_ll_rx_connect_to_memory DMA_LL_FUNC(rx_connect_to_mem)
#define dma_ll_tx_disconnect_all DMA_LL_FUNC(tx_disconnect_all)
#define dma_ll_rx_disconnect_all DMA_LL_FUNC(rx_disconnect_all)
#define dma_ll_tx_set_desc_addr DMA_LL_FUNC(tx_set_desc_addr)
#define dma_ll_tx_start DMA_LL_FUNC(tx_start)
#define dma_ll_rx_set_desc_addr DMA_LL_FUNC(rx_set_desc_addr)
@@ -72,23 +74,23 @@ static void crypto_shared_gdma_init(void)
dma_ll_rx_enable_descriptor_burst(&DMA_DEV, TEE_CRYPTO_GDMA_CH, true);
dma_ll_tx_reset_channel(&DMA_DEV, TEE_CRYPTO_GDMA_CH);
dma_ll_tx_connect_to_periph(&DMA_DEV, TEE_CRYPTO_GDMA_CH, GDMA_TRIG_PERIPH_M2M, SOC_GDMA_TRIG_PERIPH_M2M0);
dma_ll_tx_connect_to_memory(&DMA_DEV, TEE_CRYPTO_GDMA_CH, SOC_GDMA_TRIG_PERIPH_M2M0);
dma_ll_rx_reset_channel(&DMA_DEV, TEE_CRYPTO_GDMA_CH);
dma_ll_rx_connect_to_periph(&DMA_DEV, TEE_CRYPTO_GDMA_CH, GDMA_TRIG_PERIPH_M2M, SOC_GDMA_TRIG_PERIPH_M2M0);
dma_ll_rx_connect_to_memory(&DMA_DEV, TEE_CRYPTO_GDMA_CH, SOC_GDMA_TRIG_PERIPH_M2M0);
}
esp_err_t esp_tee_crypto_shared_gdma_start(const crypto_dma_desc_t *input, const crypto_dma_desc_t *output, gdma_trigger_peripheral_t periph)
esp_err_t esp_tee_crypto_shared_gdma_start(const crypto_dma_desc_t *input, const crypto_dma_desc_t *output, crypto_dma_user_t periph)
{
int periph_inst_id = SOC_GDMA_TRIG_PERIPH_M2M0;
switch (periph) {
#if SOC_SHA_SUPPORTED
case GDMA_TRIG_PERIPH_SHA:
case CRYPTO_DMA_USER_SHA:
periph_inst_id = SOC_GDMA_TRIG_PERIPH_SHA0;
break;
#endif
#if SOC_AES_SUPPORTED
case GDMA_TRIG_PERIPH_AES:
case CRYPTO_DMA_USER_AES:
periph_inst_id = SOC_GDMA_TRIG_PERIPH_AES0;
break;
#endif
@@ -98,14 +100,14 @@ esp_err_t esp_tee_crypto_shared_gdma_start(const crypto_dma_desc_t *input, const
crypto_shared_gdma_init();
dma_ll_tx_disconnect_from_periph(&DMA_DEV, TEE_CRYPTO_GDMA_CH);
dma_ll_rx_disconnect_from_periph(&DMA_DEV, TEE_CRYPTO_GDMA_CH);
dma_ll_tx_disconnect_all(&DMA_DEV, TEE_CRYPTO_GDMA_CH);
dma_ll_rx_disconnect_all(&DMA_DEV, TEE_CRYPTO_GDMA_CH);
dma_ll_tx_reset_channel(&DMA_DEV, TEE_CRYPTO_GDMA_CH);
dma_ll_tx_connect_to_periph(&DMA_DEV, TEE_CRYPTO_GDMA_CH, periph, periph_inst_id);
dma_ll_tx_connect_to_periph(&DMA_DEV, TEE_CRYPTO_GDMA_CH, periph_inst_id);
dma_ll_rx_reset_channel(&DMA_DEV, TEE_CRYPTO_GDMA_CH);
dma_ll_rx_connect_to_periph(&DMA_DEV, TEE_CRYPTO_GDMA_CH, periph, periph_inst_id);
dma_ll_rx_connect_to_periph(&DMA_DEV, TEE_CRYPTO_GDMA_CH, periph_inst_id);
dma_ll_tx_set_desc_addr(&DMA_DEV, TEE_CRYPTO_GDMA_CH, (intptr_t)input);
dma_ll_tx_start(&DMA_DEV, TEE_CRYPTO_GDMA_CH);
@@ -121,8 +123,8 @@ void esp_tee_crypto_shared_gdma_free(void)
dma_ll_tx_stop(&DMA_DEV, TEE_CRYPTO_GDMA_CH);
dma_ll_rx_stop(&DMA_DEV, TEE_CRYPTO_GDMA_CH);
dma_ll_tx_disconnect_from_periph(&DMA_DEV, TEE_CRYPTO_GDMA_CH);
dma_ll_rx_disconnect_from_periph(&DMA_DEV, TEE_CRYPTO_GDMA_CH);
dma_ll_tx_disconnect_all(&DMA_DEV, TEE_CRYPTO_GDMA_CH);
dma_ll_rx_disconnect_all(&DMA_DEV, TEE_CRYPTO_GDMA_CH);
dma_ll_tx_set_priority(&DMA_DEV, TEE_CRYPTO_GDMA_CH, 0);
dma_ll_rx_set_priority(&DMA_DEV, TEE_CRYPTO_GDMA_CH, 0);
@@ -138,7 +140,7 @@ void esp_tee_crypto_shared_gdma_free(void)
#if SOC_AES_SUPPORTED
esp_err_t esp_aes_dma_start(const crypto_dma_desc_t *input, const crypto_dma_desc_t *output)
{
return esp_tee_crypto_shared_gdma_start(input, output, GDMA_TRIG_PERIPH_AES);
return esp_tee_crypto_shared_gdma_start(input, output, CRYPTO_DMA_USER_AES);
}
bool esp_aes_dma_done(const crypto_dma_desc_t *output)
@@ -152,6 +154,6 @@ bool esp_aes_dma_done(const crypto_dma_desc_t *output)
#if SOC_SHA_SUPPORTED
esp_err_t esp_sha_dma_start(const crypto_dma_desc_t *input)
{
return esp_tee_crypto_shared_gdma_start(input, NULL, GDMA_TRIG_PERIPH_SHA);
return esp_tee_crypto_shared_gdma_start(input, NULL, CRYPTO_DMA_USER_SHA);
}
#endif
components/mbedtls/esp_tee/esp_tee_crypto_shared_gdma.h
+2 -3
View File
@@ -19,11 +19,10 @@ extern "C" {
*
* @param input Input linked list descriptor (crypto_dma_desc_t *)
* @param output Output linked list descriptor (crypto_dma_desc_t *)
* @param periph Crypto peripheral to connect the DMA to, either GDMA_TRIG_PERIPH_AES or
* GDMA_TRIG_PERIPH_SHA
* @param periph Crypto peripheral to connect the DMA to, either CRYPTO_DMA_USER_AES or CRYPTO_DMA_USER_SHA
* @return esp_err_t ESP_OK on success, ESP_ERR_INVALID_ARG if invalid peripheral specified
*/
esp_err_t esp_tee_crypto_shared_gdma_start(const crypto_dma_desc_t *input, const crypto_dma_desc_t *output, gdma_trigger_peripheral_t periph);
esp_err_t esp_tee_crypto_shared_gdma_start(const crypto_dma_desc_t *input, const crypto_dma_desc_t *output, crypto_dma_user_t periph);
/**
* @brief Frees the TEE-specific shared crypto DMA channel.
components/mbedtls/port/aes/dma/esp_aes_gdma_impl.c
+1 -1
View File
@@ -10,7 +10,7 @@
esp_err_t esp_aes_dma_start(const crypto_dma_desc_t *input, const crypto_dma_desc_t *output)
{
return esp_crypto_shared_gdma_start_axi_ahb(input, output, GDMA_TRIG_PERIPH_AES);
return esp_crypto_shared_gdma_start_axi_ahb(input, output, CRYPTO_DMA_USER_AES);
}
bool esp_aes_dma_done(const crypto_dma_desc_t *output)
components/mbedtls/port/crypto_shared_gdma/esp_crypto_shared_gdma.c
+3 -3
View File
@@ -134,7 +134,7 @@ static bool check_dma_descs_need_ext_mem_ecc_aes_access(const crypto_dma_desc_t
}
#endif /* (SOC_GDMA_EXT_MEM_ENC_ALIGNMENT && SOC_AXI_GDMA_SUPPORTED) */
esp_err_t esp_crypto_shared_gdma_start_axi_ahb(const crypto_dma_desc_t *input, const crypto_dma_desc_t *output, gdma_trigger_peripheral_t peripheral)
esp_err_t esp_crypto_shared_gdma_start_axi_ahb(const crypto_dma_desc_t *input, const crypto_dma_desc_t *output, crypto_dma_user_t peripheral)
{
int rx_ch_id = 0;
@@ -151,12 +151,12 @@ esp_err_t esp_crypto_shared_gdma_start_axi_ahb(const crypto_dma_desc_t *input, c
gdma_disconnect(s_tx_channel);
#ifdef SOC_SHA_SUPPORTED
if (peripheral == GDMA_TRIG_PERIPH_SHA) {
if (peripheral == CRYPTO_DMA_USER_SHA) {
gdma_connect(s_tx_channel, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_SHA, 0));
} else
#endif // SOC_SHA_SUPPORTED
#ifdef SOC_AES_SUPPORTED
if (peripheral == GDMA_TRIG_PERIPH_AES) {
if (peripheral == CRYPTO_DMA_USER_AES) {
gdma_connect(s_tx_channel, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_AES, 0));
} else
#endif // SOC_AES_SUPPORTED
components/mbedtls/port/include/esp_crypto_dma.h
+5 -2
View File
@@ -15,10 +15,13 @@
#endif /* SOC_GDMA_SUPPORTED */
#ifdef __cplusplus
extern "C"
{
extern "C" {
#endif
typedef enum {
CRYPTO_DMA_USER_AES, // DMA user for AES peripheral
CRYPTO_DMA_USER_SHA, // DMA user for SHA peripheral
} crypto_dma_user_t;
#if (SOC_AES_SUPPORT_DMA) || (SOC_SHA_SUPPORT_DMA)
components/mbedtls/port/include/esp_crypto_shared_gdma.h
+2 -3
View File
@@ -25,11 +25,10 @@ extern "C" {
*
* @param input Input linked list descriptor (crypto_dma_desc_t *)
* @param output Output linked list descriptor (crypto_dma_desc_t *)
* @param peripheral Crypto peripheral to connect the DMA to, either GDMA_TRIG_PERIPH_AES or
* GDMA_TRIG_PERIPH_SHA
* @param peripheral Crypto peripheral to connect the DMA to, either CRYPTO_DMA_USER_AES or CRYPTO_DMA_USER_SHA
* @return esp_err_t ESP_FAIL if no GDMA channel available
*/
esp_err_t esp_crypto_shared_gdma_start_axi_ahb(const crypto_dma_desc_t *input, const crypto_dma_desc_t *output, gdma_trigger_peripheral_t peripheral);
esp_err_t esp_crypto_shared_gdma_start_axi_ahb(const crypto_dma_desc_t *input, const crypto_dma_desc_t *output, crypto_dma_user_t peripheral);
#if SOC_AXI_GDMA_SUPPORTED
/**
components/mbedtls/port/sha/core/esp_sha_gdma_impl.c
+1 -1
View File
@@ -9,5 +9,5 @@
esp_err_t esp_sha_dma_start(const crypto_dma_desc_t *input)
{
return esp_crypto_shared_gdma_start_axi_ahb(input, NULL, GDMA_TRIG_PERIPH_SHA);
return esp_crypto_shared_gdma_start_axi_ahb(input, NULL, CRYPTO_DMA_USER_SHA);
}