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Merge branch 'refactor/remove_completed_todos' into 'master'

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refactor(global): remove completed todos in the codebase

See merge request espressif/esp-idf!44188
This commit is contained in:
morris
2025-12-16 14:21:25 +08:00
parent cbcc2ded3e 291554cd09
commit 1f04dbb31b
61 changed files with 49 additions and 157 deletions
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components/bootloader_support/src/esp32c61/bootloader_soc.c
+1 -1
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@@ -11,9 +11,9 @@
#include "hal/regi2c_ctrl.h"
#include "soc/regi2c_saradc.h"
//Not supported but common bootloader calls the function. Do nothing
void bootloader_ana_clock_glitch_reset_config(bool enable)
{
// TODO: IDF-9274
(void)enable;
}
components/driver/sdkconfig.rename
-5
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@@ -1,5 +0,0 @@
# sdkconfig replacement configurations for deprecated options formatted as
# CONFIG_DEPRECATED_OPTION CONFIG_NEW_OPTION
CONFIG_ADC2_DISABLE_DAC CONFIG_ADC_DISABLE_DAC
CONFIG_MCPWM_ISR_IN_IRAM CONFIG_MCPWM_ISR_IRAM_SAFE
components/driver/test_apps/touch_sensor_v2/main/test_touch_v2.c
+1 -1
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@@ -1922,7 +1922,7 @@ esp_err_t test_touch_sleep_pad_interrupt_wakeup_deep_sleep(touch_pad_t sleep_pad
return ESP_OK;
}
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3) //TODO: IDF-5218
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3) //TODO: IDF-14963
#include <sys/time.h>
#include "esp_sleep.h"
components/efuse/esp32c2/esp_efuse_rtc_calib.c
+1 -1
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@@ -14,7 +14,7 @@
int esp_efuse_rtc_calib_get_ver(void)
{
uint32_t blk_ver_major = 0;
esp_efuse_read_field_blob(ESP_EFUSE_BLK_VERSION_MAJOR, &blk_ver_major, ESP_EFUSE_BLK_VERSION_MAJOR[0]->bit_count); // IDF-5366
esp_efuse_read_field_blob(ESP_EFUSE_BLK_VERSION_MAJOR, &blk_ver_major, ESP_EFUSE_BLK_VERSION_MAJOR[0]->bit_count);
uint32_t cali_version = (blk_ver_major == 0) ? ESP_EFUSE_ADC_CALIB_VER : 0;
if (!cali_version) {
components/efuse/esp32c3/esp_efuse_rtc_calib.c
+1 -1
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@@ -12,7 +12,7 @@
int esp_efuse_rtc_calib_get_ver(void)
{
uint32_t blk_ver_major = 0;
esp_efuse_read_field_blob(ESP_EFUSE_BLK_VERSION_MAJOR, &blk_ver_major, ESP_EFUSE_BLK_VERSION_MAJOR[0]->bit_count); // IDF-5366
esp_efuse_read_field_blob(ESP_EFUSE_BLK_VERSION_MAJOR, &blk_ver_major, ESP_EFUSE_BLK_VERSION_MAJOR[0]->bit_count);
uint32_t cali_version = (blk_ver_major == 1) ? ESP_EFUSE_ADC_CALIB_VER : 0;
if (!cali_version) {
components/efuse/esp32s3/esp_efuse_rtc_calib.c
+1 -1
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@@ -15,7 +15,7 @@
int esp_efuse_rtc_calib_get_ver(void)
{
uint32_t blk_ver_major = 0;
ESP_ERROR_CHECK(esp_efuse_read_field_blob(ESP_EFUSE_BLK_VERSION_MAJOR, &blk_ver_major, ESP_EFUSE_BLK_VERSION_MAJOR[0]->bit_count)); // IDF-5366
ESP_ERROR_CHECK(esp_efuse_read_field_blob(ESP_EFUSE_BLK_VERSION_MAJOR, &blk_ver_major, ESP_EFUSE_BLK_VERSION_MAJOR[0]->bit_count));
uint32_t cali_version = (blk_ver_major == 1) ? ESP_EFUSE_ADC_CALIB_VER : 0;
if (!cali_version) {
components/esp_adc/sdkconfig.rename
+1
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@@ -1,6 +1,7 @@
# sdkconfig replacement configurations for deprecated options formatted as
# CONFIG_DEPRECATED_OPTION CONFIG_NEW_OPTION
CONFIG_ADC2_DISABLE_DAC CONFIG_ADC_DISABLE_DAC
CONFIG_ADC_DISABLE_DAC CONFIG_ADC_DISABLE_DAC_OUTPUT
CONFIG_ADC_CAL_EFUSE_TP_ENABLE CONFIG_ADC_CALI_EFUSE_TP_ENABLE
CONFIG_ADC_CAL_EFUSE_VREF_ENABLE CONFIG_ADC_CALI_EFUSE_VREF_ENABLE
components/esp_driver_mcpwm/sdkconfig.rename
+1
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@@ -1,4 +1,5 @@
# sdkconfig replacement configurations for deprecated options formatted as
# CONFIG_DEPRECATED_OPTION CONFIG_NEW_OPTION
CONFIG_MCPWM_ISR_IN_IRAM CONFIG_MCPWM_ISR_IRAM_SAFE
CONFIG_MCPWM_ISR_IRAM_SAFE CONFIG_MCPWM_ISR_CACHE_SAFE
components/esp_driver_spi/test_apps/components/spi_bench_mark/include/spi_performance.h
+2 -2
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@@ -10,7 +10,7 @@
#define IDF_TARGET_MAX_SPI_CLK_FREQ 16*1000*1000
#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA 15
#define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU 15
#if !CONFIG_FREERTOS_SMP // IDF-5223
#if !CONFIG_FREERTOS_SMP // IDF-5826
#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA 34 // TODO: IDF-5180
#define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU 30 // TODO: IDF-5180
#else
@@ -41,7 +41,7 @@
#elif CONFIG_IDF_TARGET_ESP32C3
#define IDF_TARGET_MAX_SPI_CLK_FREQ 40*1000*1000
#if !CONFIG_FREERTOS_SMP // IDF-5223
#if !CONFIG_FREERTOS_SMP // IDF-5826
#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA 15
#define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU 15
#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA 33
components/esp_hal_ana_conv/esp32s2/include/hal/adc_ll.h
-1
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@@ -208,7 +208,6 @@ static inline void adc_ll_digi_convert_limit_enable(bool enable)
* Set adc conversion mode for digital controller.
*
* @param mode Conversion mode select.
* TODO IDF-3610
*/
static inline void adc_ll_digi_set_convert_mode(adc_ll_digi_convert_mode_t mode)
{
components/esp_hw_support/modem_clock.c
+2 -2
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@@ -465,7 +465,7 @@ void modem_clock_select_lp_clock_source(shared_periph_module_t module, modem_clo
modem_clock_hal_deselect_all_coex_lpclk_source(MODEM_CLOCK_instance()->hal);
modem_clock_hal_select_coex_lpclk_source(MODEM_CLOCK_instance()->hal, src);
modem_lpcon_ll_set_coex_lpclk_divisor_value(MODEM_CLOCK_instance()->hal->lpcon_dev, divider);
// modem_lpcon_ll_enable_coex_clock(MODEM_CLOCK_instance()->hal->lpcon_dev, true); // TODO: IDF-5727
// modem_lpcon_ll_enable_coex_clock(MODEM_CLOCK_instance()->hal->lpcon_dev, true); // TODO: IDF-14964
break;
default:
break;
@@ -534,7 +534,7 @@ void modem_clock_deselect_lp_clock_source(shared_periph_module_t module)
#endif // SOC_BT_SUPPORTED
case PERIPH_COEX_MODULE:
modem_clock_hal_deselect_all_coex_lpclk_source(MODEM_CLOCK_instance()->hal);
// modem_lpcon_ll_enable_coex_clock(MODEM_CLOCK_instance()->hal->lpcon_dev, false); // TODO: IDF-5727
// modem_lpcon_ll_enable_coex_clock(MODEM_CLOCK_instance()->hal->lpcon_dev, false); // TODO: IDF-14964
break;
default:
break;
components/esp_hw_support/port/esp32c3/rtc_init.c
+1 -1
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@@ -64,7 +64,7 @@ void rtc_init(rtc_config_t cfg)
REG_SET_FIELD(RTC_CNTL_TIMER6_REG, RTC_CNTL_DG_PERI_WAIT_TIMER, rtc_init_cfg.dg_peri_wait_cycles);
if (cfg.cali_ocode) {
uint32_t rtc_calib_version = efuse_ll_get_blk_version_major(); // IDF-5366
uint32_t rtc_calib_version = efuse_ll_get_blk_version_major();
if (rtc_calib_version == 1) {
set_ocode_by_efuse(rtc_calib_version);
} else {
components/esp_hw_support/port/esp32s2/rtc_init.c
+1 -1
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@@ -164,7 +164,7 @@ void rtc_init(rtc_config_t cfg)
#if !CONFIG_IDF_ENV_FPGA
if (cfg.cali_ocode) {
uint32_t rtc_calib_version = efuse_ll_get_blk_version_minor(); // IDF-5366
uint32_t rtc_calib_version = efuse_ll_get_blk_version_minor();
if (rtc_calib_version == 2) {
set_ocode_by_efuse(rtc_calib_version);
} else {
components/esp_hw_support/port/esp32s3/esp_memprot.c
+1 -2
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@@ -997,7 +997,7 @@ esp_err_t esp_mprot_set_prot(const esp_memp_config_t *memp_config)
}
}
//reenable the protection
//re-enable the protection
if (use_iram0) {
for (size_t x = 0; x < core_count; x++) {
ESP_MEMPROT_ERR_CHECK(ret, esp_mprot_monitor_clear_intr(MEMPROT_TYPE_IRAM0_SRAM, memp_config->target_cpu[x]))
@@ -1043,7 +1043,6 @@ esp_err_t esp_mprot_set_prot(const esp_memp_config_t *memp_config)
}
}
//sanity check (RTC FAST tbd within IDF-5208)
if (use_iram0 || use_dram0) {
uint32_t check_val;
components/esp_hw_support/port/esp32s3/rtc_init.c
+1 -1
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@@ -94,7 +94,7 @@ void rtc_init(rtc_config_t cfg)
REG_SET_FIELD(RTC_CNTL_TIMER2_REG, RTC_CNTL_ULPCP_TOUCH_START_WAIT, RTC_CNTL_ULPCP_TOUCH_START_WAIT_DEFAULT);
if (cfg.cali_ocode) {
uint32_t blk_ver_major = efuse_ll_get_blk_version_major(); // IDF-5366
uint32_t blk_ver_major = efuse_ll_get_blk_version_major();
//default blk_ver_major will fallback to using the self-calibration way for OCode
bool ocode_efuse_cali = (blk_ver_major == 1);
if (ocode_efuse_cali) {
components/esp_mm/port/esp32c5/ext_mem_layout.c
-1
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@@ -39,7 +39,6 @@
* The start addresses in this list should always be sorted from low to high, as MMU driver will need to
* coalesce adjacent regions
*/
// TODO: [ESP32C5] IDF-8658
const mmu_mem_region_t g_mmu_mem_regions[SOC_MMU_LINEAR_ADDRESS_REGION_NUM] = {
[0] = {
.start = MMU_IRAM0_LINEAR_ADDRESS_LOW,
components/esp_partition/partition.c
-1
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@@ -13,7 +13,6 @@
/* interim to enable test_wl_host and test_fatfs_on_host compilation (both use IDF_TARGET_ESP32)
* should go back to #include "sys/queue.h" once the tests are switched to CMake
* see IDF-7000
*/
#if __has_include(<bsd/sys/queue.h>)
#include <bsd/sys/queue.h>
components/esp_psram/xip_impl/mmu_psram_flash.c
+1 -1
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@@ -42,7 +42,7 @@
//page_size - 1, where page_size on s2 and s3 is always 0x10000. To be refactored by MMU driver
#define INVALID_PHY_PAGE 0xffff
const static char *TAG = "mmu_psram";
//TODO IDF-4387
static uint32_t page0_mapped = 0;
static uint32_t page0_page = INVALID_PHY_PAGE;
components/esp_ringbuf/test_apps/main/test_ringbuf_target.c
+1 -1
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@@ -81,7 +81,7 @@ out:
return need_yield;
}
// IDF-6471 - test hangs up on QEMU
// test hangs up on QEMU
TEST_CASE("Test ring buffer ISR", "[esp_ringbuf][qemu-ignore]")
{
gptimer_handle_t gptimer;
components/esp_rom/esp32h21/include/esp32h21/rom/ecdsa.h
-2
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@@ -12,8 +12,6 @@
extern "C" {
#endif
//TODO: [ESP32H21] IDF-11496
#define ETS_DIGEST_LEN 32 /* SHA-256, bytes */
typedef enum {
components/esp_rom/esp32h21/include/esp32h21/rom/hmac.h
-2
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@@ -14,8 +14,6 @@ extern "C" {
#include <stdlib.h>
#include "efuse.h"
//TODO: [ESP32H21] IDF-11495
void ets_hmac_enable(void);
void ets_hmac_disable(void);
components/esp_rom/esp32h21/include/esp32h21/rom/rom_layout.h
-2
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@@ -8,8 +8,6 @@
#include <stdint.h>
//TODO: [ESP32H21] IDF-11555
#ifdef __cplusplus
extern "C" {
#endif
components/esp_rom/esp32h21/include/esp32h21/rom/rsa_pss.h
-2
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@@ -10,8 +10,6 @@
#include <stdbool.h>
#include <stddef.h>
//TODO: [ESP32H21] IDF-11498
#ifdef __cplusplus
extern "C" {
#endif
components/esp_rom/esp32h21/include/esp32h21/rom/secure_boot.h
-2
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@@ -13,8 +13,6 @@
#include "rsa_pss.h"
#include "esp_assert.h"
//TODO: [ESP32H21] IDF-11500
#ifdef __cplusplus
extern "C" {
#endif
components/esp_rom/esp32h21/include/esp32h21/rom/sha.h
-2
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@@ -9,8 +9,6 @@
#include <stdbool.h>
#include "ets_sys.h"
//TODO: [ESP32H21] IDF-11501
#ifdef __cplusplus
extern "C" {
#endif
components/esp_system/include/esp_debug_helpers.h
-1
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@@ -14,7 +14,6 @@ extern "C" {
#include <stdbool.h>
#include "sdkconfig.h"
#include "soc/soc.h" // [refactor-todo] IDF-2297
#include "esp_err.h"
#include "esp_cpu.h"
components/esp_system/port/soc/esp32c5/system_internal.c
-8
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@@ -41,7 +41,6 @@ void esp_system_reset_modules_on_exit(void)
}
}
// TODO: IDF-8845
#if SOC_MODEM_CLOCK_SUPPORTED
modem_syscon_ll_reset_all(&MODEM_SYSCON);
modem_lpcon_ll_reset_all(&MODEM_LPCON);
@@ -135,13 +134,6 @@ void esp_restart_noos(void)
// Disable cache
Cache_Disable_Cache();
// Reset wifi/bluetooth/ethernet/sdio (bb/mac)
// Moved to module internal
// SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG,
// SYSTEM_SDIO_RST | // SDIO_HINF_HINF_SDIO_RST?
// SYSTEM_EMAC_RST | SYSTEM_MACPWR_RST | // TODO: IDF-5325 (ethernet)
// REG_WRITE(SYSTEM_CORE_RST_EN_REG, 0);
esp_system_reset_modules_on_exit();
// Set CPU back to XTAL source, same as hard reset, but keep BBPLL on so that USB Serial JTAG can log at 1st stage bootloader.
components/esp_system/port/soc/esp32c6/system_internal.c
-7
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@@ -122,13 +122,6 @@ void esp_restart_noos(void)
// Disable cache
Cache_Disable_ICache();
// Reset wifi/bluetooth/ethernet/sdio (bb/mac)
// Moved to module internal
// SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG,
// SYSTEM_SDIO_RST | // SDIO_HINF_HINF_SDIO_RST?
// SYSTEM_EMAC_RST | SYSTEM_MACPWR_RST | // TODO: IDF-5325 (ethernet)
// REG_WRITE(SYSTEM_CORE_RST_EN_REG, 0);
esp_system_reset_modules_on_exit();
// Set CPU back to XTAL source, same as hard reset, but keep BBPLL on so that USB Serial JTAG can log at 1st stage bootloader.
components/esp_system/port/soc/esp32c61/reset_reason.c
-2
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@@ -9,8 +9,6 @@
#include "esp_private/system_internal.h"
#include "esp32c61/rom/rtc.h"
// TODO: [ESP32C61] IDF-9267
static void esp_reset_reason_clear_hint(void);
static esp_reset_reason_t s_reset_reason;
components/esp_system/port/soc/esp32c61/system_internal.c
-8
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@@ -134,14 +134,6 @@ void esp_restart_noos(void)
// Disable cache
Cache_Disable_Cache();
//TODO: [ESP32C61] IDF-9553, inherit from verify code
// Reset wifi/bluetooth/ethernet/sdio (bb/mac)
// Moved to module internal
// SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG,
// SYSTEM_SDIO_RST | // SDIO_HINF_HINF_SDIO_RST?
// SYSTEM_EMAC_RST | SYSTEM_MACPWR_RST | // TODO: IDF-5325 (ethernet)
// REG_WRITE(SYSTEM_CORE_RST_EN_REG, 0);
esp_system_reset_modules_on_exit();
// Set CPU back to XTAL source, same as hard reset, but keep BBPLL on so that USB Serial JTAG can log at 1st stage bootloader.
components/esp_system/port/soc/esp32p4/system_internal.c
-1
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@@ -202,7 +202,6 @@ void esp_restart_noos(void)
#endif
#if CONFIG_SPIRAM_INSTRUCTIONS_RODATA
//TODO: IDF-7556
// disable remap if enabled in menuconfig
REG_CLR_BIT(HP_SYS_HP_PSRAM_FLASH_ADDR_INTERCHANGE_REG, HP_SYS_HP_PSRAM_FLASH_ADDR_INTERCHANGE_DMA | HP_SYS_HP_PSRAM_FLASH_ADDR_INTERCHANGE_CPU);
#endif
components/esp_system/port/soc/esp32s31/system_internal.c
-1
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@@ -97,7 +97,6 @@ void esp_restart_noos(void)
#endif
#if CONFIG_SPIRAM_INSTRUCTIONS_RODATA
//TODO: IDF-7556
// disable remap if enabled in menuconfig
REG_CLR_BIT(HP_SYS_HP_PSRAM_FLASH_ADDR_INTERCHANGE_REG, HP_SYS_HP_PSRAM_FLASH_ADDR_INTERCHANGE_DMA | HP_SYS_HP_PSRAM_FLASH_ADDR_INTERCHANGE_CPU);
#endif
components/esp_system/test_apps/esp_system_unity_tests/main/test_reset_reason.c
-1
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@@ -23,7 +23,6 @@
#define CHECK_VALUE 0x89abcdef
// TODO: IDF-9564
#if (CONFIG_SOC_RTC_FAST_MEM_SUPPORTED || CONFIG_SOC_RTC_SLOW_MEM_SUPPORTED) && !CONFIG_IDF_TARGET_ESP32P4
#define CHECK_RTC_MEM 1
#endif //CONFIG_SOC_RTC_FAST_MEM_SUPPORTED || CONFIG_SOC_RTC_SLOW_MEM_SUPPORTED
components/freertos/FreeRTOS-Kernel-SMP/include/freertos/FreeRTOS.h
-2
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@@ -3353,8 +3353,6 @@ typedef StaticStreamBuffer_t StaticMessageBuffer_t;
* that FreeRTOS.h must be included first before calling any FreeRTOS API,
* any existing source code can continue using these relocated APIs without
* any additional header inclusions via this implicit inclusion.
*
* Todo: Deprecate this implicit inclusion by ESP-IDF v6.0 (IDF-8126)
*/
#include "freertos/idf_additions.h"
components/freertos/FreeRTOS-Kernel/include/freertos/FreeRTOS.h
-2
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@@ -1527,8 +1527,6 @@ typedef StaticStreamBuffer_t StaticMessageBuffer_t;
* that FreeRTOS.h must be included first before calling any FreeRTOS API,
* any existing source code can continue using these relocated APIs without
* any additional header inclusions via this implicit inclusion.
*
* Todo: Deprecate this implicit inclusion by ESP-IDF v6.0 (IDF-8126)
*/
#include "freertos/idf_additions.h"
components/freertos/FreeRTOS-Kernel/include/freertos/projdefs.h
+1 -2
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@@ -49,8 +49,7 @@ typedef void (* TaskFunction_t)( void * );
/* Converts a time in ticks to milliseconds. This macro can be
* overridden by a macro of the same name defined in FreeRTOSConfig.h in case the
* definition here is not suitable for your application.
*
* Todo: Upstream this macro (IDF-8181) */
*/
#ifndef pdTICKS_TO_MS
#define pdTICKS_TO_MS( xTicks ) ( ( TickType_t ) ( ( uint64_t ) ( xTicks ) * 1000 / configTICK_RATE_HZ ) )
#endif
components/freertos/FreeRTOS-Kernel/include/freertos/task.h
-1
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@@ -204,7 +204,6 @@ typedef enum
* \ingroup Tasks
*/
#define tskNO_AFFINITY ( ( BaseType_t ) 0x7FFFFFFF )
/* Todo: Update tskNO_AFFINITY value to -1 (IDF-7908) */
/**
* Macro to check if an xCoreID value is valid
components/freertos/esp_additions/freertos_tasks_c_additions.h
-1
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@@ -424,7 +424,6 @@ BaseType_t xTaskGetCoreID( TaskHandle_t xTask )
#else /* CONFIG_FREERTOS_SMP */
TCB_t * pxTCB;
/* Todo: Remove xCoreID for single core builds (IDF-7894) */
pxTCB = prvGetTCBFromHandle( xTask );
xReturn = pxTCB->xCoreID;
components/freertos/esp_additions/include/freertos/idf_additions.h
+1 -1
View File
@@ -120,7 +120,7 @@
*
* If CONFIG_FREERTOS_UNICORE is enabled, this function simply returns 0.
*
* [refactor-todo] See if this needs to be deprecated (IDF-8145)(IDF-8164)
* [refactor-todo] See if this needs to be deprecated (IDF-8145)
*
* @note If CONFIG_FREERTOS_SMP is enabled, please call vTaskCoreAffinityGet()
* instead.
components/hal/esp32c5/include/hal/systimer_ll.h
-2
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@@ -16,8 +16,6 @@
extern "C" {
#endif
// TODO: [ESP32C5] IDF-8707
// All these functions get invoked either from ISR or HAL that linked to IRAM.
// Always inline these functions even no gcc optimization is applied.
components/hal/esp32c61/include/hal/mmu_ll.h
-2
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@@ -16,8 +16,6 @@
#include "hal/efuse_hal.h"
#include "esp_fault.h"
// TODO: [ESP32C61] IDF-9265, inherit from c6
#ifdef __cplusplus
extern "C" {
#endif
components/hal/esp32h21/include/hal/efuse_ll.h
+8 -8
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@@ -56,50 +56,50 @@ __attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en
// use efuse_hal_get_major_chip_version() to get major chip version
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_major(void)
{
//TODO: [ESP32H21] IDF-11507
//TODO: [ESP32H21] IDF-11556
return 0;
}
// use efuse_hal_get_minor_chip_version() to get minor chip version
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void)
{
//TODO: [ESP32H21] IDF-11507
//TODO: [ESP32H21] IDF-11556
return 0;
}
__attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_version_major(void)
{
//TODO: [ESP32H21] IDF-11507
//TODO: [ESP32H21] IDF-11556
return 0;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_major(void)
{
//TODO: [ESP32H21] IDF-11507
//TODO: [ESP32H21] IDF-11556
return 0;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_minor(void)
{
//TODO: [ESP32H21] IDF-11507
//TODO: [ESP32H21] IDF-11556
return 0;
}
__attribute__((always_inline)) static inline bool efuse_ll_get_disable_blk_version_major(void)
{
//TODO: [ESP32H21] IDF-11507
//TODO: [ESP32H21] IDF-11556
return 0;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void)
{
//TODO: [ESP32H21] IDF-11507
//TODO: [ESP32H21] IDF-11556
return 0;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_ecdsa_key_blk(void)
{
//TODO: [ESP32H21] IDF-11507
//TODO: [ESP32H21] IDF-11556
return 0;
}
components/idf_test/include/esp32/idf_performance_target.h
+2 -2
View File
@@ -12,7 +12,7 @@
#define IDF_PERFORMANCE_MIN_AES_CBC_THROUGHPUT_MBSEC 8.2
// SHA256 hardware throughput at 240MHz, threshold set lower than worst case
#if CONFIG_FREERTOS_SMP // IDF-5222
#if CONFIG_FREERTOS_SMP // IDF-5826
#define IDF_PERFORMANCE_MIN_SHA256_THROUGHPUT_MBSEC 6.0
#else
#define IDF_PERFORMANCE_MIN_SHA256_THROUGHPUT_MBSEC 8.0
@@ -40,7 +40,7 @@
#define IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_TOHOST_4BIT 12200
#endif
#if !CONFIG_FREERTOS_SMP // IDF-5224
#if !CONFIG_FREERTOS_SMP // IDF-5826
#ifndef IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_FRHOST_4BIT
#define IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_FRHOST_4BIT 11000
#endif
components/idf_test/include/idf_performance.h
+2 -2
View File
@@ -24,7 +24,7 @@
/* Due to code size & linker layout differences interacting with cache, VFS
microbenchmark currently runs slower with PSRAM enabled. */
#if !CONFIG_FREERTOS_SMP // IDF-5224
#if !CONFIG_FREERTOS_SMP // IDF-5826
#ifndef IDF_PERFORMANCE_MAX_VFS_OPEN_WRITE_CLOSE_TIME
#define IDF_PERFORMANCE_MAX_VFS_OPEN_WRITE_CLOSE_TIME 20000
#endif
@@ -83,7 +83,7 @@
// events dispatched per second by event loop library
#if !CONFIG_FREERTOS_SMP // IDF-5112
#if !CONFIG_FREERTOS_SMP // IDF-5826
#if CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ < 100 // Allowing lesser event dispatch performance for slower CPU frequency chips
#ifndef IDF_PERFORMANCE_MIN_EVENT_DISPATCH
#define IDF_PERFORMANCE_MIN_EVENT_DISPATCH 11000
components/mbedtls/test_apps/main/test_rsa.c
+4 -4
View File
@@ -432,7 +432,7 @@ static void print_rsa_details(mbedtls_rsa_context *rsa)
}
#endif
#if CONFIG_FREERTOS_SMP // IDF-5260
#if CONFIG_FREERTOS_SMP // IDF-5826
TEST_CASE("test performance RSA key operations", "[bignum][timeout=60]")
#else
TEST_CASE("test performance RSA key operations", "[bignum]")
@@ -455,7 +455,7 @@ TEST_CASE("test performance RSA key operations", "[bignum]")
}
}
#if CONFIG_FREERTOS_SMP // IDF-5260
#if CONFIG_FREERTOS_SMP // IDF-5826
TEST_CASE("test RSA-3072 calculations", "[bignum][timeout=60]")
#else
TEST_CASE("test RSA-3072 calculations", "[bignum]")
@@ -465,7 +465,7 @@ TEST_CASE("test RSA-3072 calculations", "[bignum]")
rsa_key_operations(3072, false, false);
}
#if CONFIG_FREERTOS_SMP // IDF-5260
#if CONFIG_FREERTOS_SMP // IDF-5826
TEST_CASE("test RSA-2048 calculations", "[bignum][timeout=60]")
#else
TEST_CASE("test RSA-2048 calculations", "[bignum]")
@@ -475,7 +475,7 @@ TEST_CASE("test RSA-2048 calculations", "[bignum]")
rsa_key_operations(2048, false, false);
}
#if CONFIG_FREERTOS_SMP // IDF-5260
#if CONFIG_FREERTOS_SMP // IDF-5826
TEST_CASE("test RSA-4096 calculations", "[bignum][timeout=60]")
#else
TEST_CASE("test RSA-4096 calculations", "[bignum]")
components/soc/esp32c5/include/soc/clk_tree_defs.h
+2 -2
View File
@@ -161,7 +161,7 @@ typedef enum {
/**
* @brief Type of SYSTIMER clock source
*/
typedef enum { // TODO: [ESP32C5] IDF-8676 (inherit from C6)
typedef enum {
SYSTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< SYSTIMER source clock is XTAL */
SYSTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< SYSTIMER source clock is RC_FAST */
SYSTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< SYSTIMER source clock default choice is XTAL */
@@ -360,7 +360,7 @@ typedef enum {
/**
* @brief Type of LP_I2C clock source.
*/
typedef enum { // TODO: [ESP32C5] IDF-8695 (inherit from C6)
typedef enum {
LP_I2C_SCLK_LP_FAST = SOC_MOD_CLK_RC_FAST, /*!< LP_I2C source clock is RC_FAST */
LP_I2C_SCLK_XTAL_D2 = SOC_MOD_CLK_XTAL_D2, /*!< LP_I2C source clock is XTAL_D2 */
LP_I2C_SCLK_DEFAULT = SOC_MOD_CLK_RC_FAST, /*!< LP_I2C source clock default choice is RC_FAST */
components/soc/esp32c5/include/soc/soc_caps.h
+1 -2
View File
@@ -55,7 +55,7 @@
#define SOC_GPSPI_SUPPORTED 1
#define SOC_LEDC_SUPPORTED 1
#define SOC_I2C_SUPPORTED 1
#define SOC_SYSTIMER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8707
#define SOC_SYSTIMER_SUPPORTED 1
#define SOC_SUPPORT_COEXISTENCE 1
#define SOC_AES_SUPPORTED 1
#define SOC_MPI_SUPPORTED 1
@@ -438,7 +438,6 @@
#define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1
/*-------------------------- SYSTIMER CAPS ----------------------------------*/
// TODO: [ESP32C5] IDF-8707
#define SOC_SYSTIMER_COUNTER_NUM 2 // Number of counter units
#define SOC_SYSTIMER_ALARM_NUM 3 // Number of alarm units
#define SOC_SYSTIMER_BIT_WIDTH_LO 32 // Bit width of systimer low part
components/soc/esp32c6/include/soc/soc_caps.h
-6
View File
@@ -168,7 +168,6 @@
// DIG-694: misaligned access across PMP regions must be spaced at least by two instructions
#define SOC_CPU_MISALIGNED_ACCESS_ON_PMP_MISMATCH_ISSUE 1
// TODO: IDF-5360 (Copy from esp32c3, need check)
/*-------------------------- DIGITAL SIGNATURE CAPS ----------------------------------------*/
/** The maximum length of a Digital Signature in bits. */
#define SOC_DS_SIGNATURE_MAX_BIT_LEN (3072)
@@ -337,7 +336,6 @@
/*--------------------------- RSA CAPS ---------------------------------------*/
#define SOC_RSA_MAX_BIT_LEN (3072)
// TODO: IDF-5353 (Copy from esp32c3, need check)
/*--------------------------- SHA CAPS ---------------------------------------*/
/* Max amount of bytes in a single DMA operation is 4095,
@@ -465,8 +463,6 @@
/*--------------------------- UHCI CAPS -------------------------------------*/
#define SOC_UHCI_NUM (1UL)
// TODO: IDF-5679 (Copy from esp32c3, need check)
/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/
#define SOC_COEX_HW_PTI (1)
@@ -477,14 +473,12 @@
/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/
#define SOC_PHY_DIG_REGS_MEM_SIZE (21*4)
// TODO: IDF-5679 (Copy from esp32c3, need check)
/*--------------- WIFI LIGHT SLEEP CLOCK WIDTH CAPS --------------------------*/
#define SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH (12)
/*-------------------------- RTC MEM CAPS ----------------------------*/
#define SOC_RTC_MEM_SUPPORT_SPEED_MODE_SWITCH 1
// TODO: IDF-5351 (Copy from esp32c3, need check)
/*-------------------------- Power Management CAPS ----------------------------*/
#define SOC_PM_SUPPORT_WIFI_WAKEUP (1)
#define SOC_PM_SUPPORT_BEACON_WAKEUP (1)
components/soc/esp32c61/include/soc/soc_caps.h
-6
View File
@@ -60,7 +60,6 @@
#define SOC_ASSIST_DEBUG_SUPPORTED 1
#define SOC_WDT_SUPPORTED 1
#define SOC_SPI_FLASH_SUPPORTED 1
// \#define SOC_RNG_SUPPORTED 1 //TODO: [ESP32C61] IDF-9236
#define SOC_MODEM_CLOCK_SUPPORTED 1
#define SOC_REG_I2C_SUPPORTED 1
#define SOC_ETM_SUPPORTED 1
@@ -282,7 +281,6 @@
/*------------------------ USB SERIAL JTAG CAPS ------------------------------*/
// \#define SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP (1) /*!< Support to maintain minimum usb communication during light sleep */ // TODO: IDF-6395
// TODO: IDF-5353 (Copy from esp32c3, need check)
/*--------------------------- SHA CAPS ---------------------------------------*/
/* Max amount of bytes in a single DMA operation is 4095,
@@ -419,7 +417,6 @@
#define SOC_UART_WAKEUP_SUPPORT_START_BIT_MODE (1)
#define SOC_UART_WAKEUP_SUPPORT_CHAR_SEQ_MODE (1)
// TODO: IDF-5679 (Copy from esp32c3, need check)
/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/
#define SOC_COEX_HW_PTI (1)
@@ -430,11 +427,9 @@
/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/
#define SOC_PHY_DIG_REGS_MEM_SIZE (21*4)
// TODO: IDF-5679 (Copy from esp32c3, need check)
/*--------------- WIFI LIGHT SLEEP CLOCK WIDTH CAPS --------------------------*/
#define SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH (12)
// TODO: IDF-5351 (Copy from esp32c3, need check)
/*-------------------------- Power Management CAPS ----------------------------*/
#define SOC_PM_SUPPORT_WIFI_WAKEUP (1)
#define SOC_PM_SUPPORT_BEACON_WAKEUP (1)
@@ -490,7 +485,6 @@
#define SOC_TEMPERATURE_SENSOR_UNDER_PD_TOP_DOMAIN (1)
/*------------------------------------ WI-FI CAPS ------------------------------------*/
//TODO: IDF-13138, re-open on c61 eco3
#define SOC_WIFI_HW_TSF (1) /*!< Support hardware TSF */
#define SOC_WIFI_FTM_SUPPORT (1) /*!< Support FTM */
#define SOC_WIFI_GCMP_SUPPORT (1) /*!< Support GCMP(GCMP128 and GCMP256) */
components/soc/esp32h2/include/soc/soc_caps.h
-2
View File
@@ -487,7 +487,6 @@
/*--------------------------- UHCI CAPS -------------------------------------*/
#define SOC_UHCI_NUM (1UL)
// TODO: IDF-5679 (Copy from esp32c6, need check)
/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/
#define SOC_COEX_HW_PTI (1)
@@ -495,7 +494,6 @@
#define SOC_EXTERNAL_COEX_ADVANCE (1) /*!< HARDWARE ADVANCED EXTERNAL COEXISTENCE CAPS */
#define SOC_EXTERNAL_COEX_LEADER_TX_LINE (0) /*!< EXTERNAL COEXISTENCE TX LINE CAPS */
// TODO: IDF-6337
/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/
#define SOC_PHY_DIG_REGS_MEM_SIZE (21*4)
components/soc/esp32h21/include/soc/periph_defs.h
-1
View File
@@ -12,7 +12,6 @@
extern "C" {
#endif
// TODO: IDF-11855
typedef enum {
PERIPH_TIMG0_MODULE,
PERIPH_TIMG1_MODULE,
components/soc/esp32h21/include/soc/soc_caps.h
+1 -1
View File
@@ -39,7 +39,7 @@
// #define SOC_SUPPORTS_SECURE_DL_MODE 1
// #define SOC_ULP_SUPPORTED 1
#define SOC_EFUSE_KEY_PURPOSE_FIELD 1
#define SOC_EFUSE_SUPPORTED 1 //TODO: [ESP32H21] IDF-11507
#define SOC_EFUSE_SUPPORTED 1 //TODO: [ESP32H21] IDF-11556
#define SOC_RTC_FAST_MEM_SUPPORTED 1
#define SOC_RTC_MEM_SUPPORTED 1 //TODO: [ESP32H21] IDF-11548
#define SOC_I2S_SUPPORTED 1
components/soc/esp32h4/include/soc/soc_caps.h
-5
View File
@@ -54,8 +54,6 @@
#define SOC_USB_SERIAL_JTAG_SUPPORTED 1
// #define SOC_TEMP_SENSOR_SUPPORTED 1 // TODO: [ESP32H4] IDF-12404
// #define SOC_SUPPORTS_SECURE_DL_MODE 1
// #define SOC_ULP_SUPPORTED 0 // TODO: [ESP32H4] IDF-12396
// #define SOC_LP_CORE_SUPPORTED 0
#define SOC_EFUSE_KEY_PURPOSE_FIELD 1 // TODO: [ESP32H4] IDF-12268
#define SOC_EFUSE_SUPPORTED 1 // TODO: [ESP32H4] IDF-12268
// #define SOC_RTC_MEM_SUPPORTED 1 // TODO: [ESP32H4] IDF-12313
@@ -83,8 +81,6 @@
#define SOC_LP_AON_SUPPORTED 1
#define SOC_TOUCH_SENSOR_SUPPORTED 1
// #define SOC_LP_PERIPHERALS_SUPPORTED 1
// #define SOC_LP_I2C_SUPPORTED 1 // TODO: [ESP32H4] IDF-12449
// #define SOC_ULP_LP_UART_SUPPORTED 1 // TODO: [ESP32H4] IDF-12445 IDF-12451
#define SOC_REG_I2C_SUPPORTED 1
#define SOC_CLK_TREE_SUPPORTED 1
// #define SOC_ASSIST_DEBUG_SUPPORTED 1 // TODO: [ESP32H4] IDF-12310
@@ -401,7 +397,6 @@
#define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part
/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
// #define SOC_TIMER_SUPPORT_ETM (1) // TODO: [ESP32H4] IDF-12355
#define SOC_TIMER_SUPPORT_ETM (1)
#define SOC_TIMER_SUPPORT_SLEEP_RETENTION (1)
components/soc/esp32p4/include/soc/soc_caps.h
-4
View File
@@ -479,7 +479,6 @@
#define SOC_SDMMC_PSRAM_DMA_CAPABLE 1 ///< SDMMC peripheral can do DMA transfer to/from PSRAM
#define SOC_SDMMC_UHS_I_SUPPORTED 1
// TODO: IDF-5353 (Copy from esp32c3, need check)
/*--------------------------- SHA CAPS ---------------------------------------*/
/* Max amount of bytes in a single DMA operation is 4095,
@@ -658,18 +657,15 @@
/*--------------------------- UHCI CAPS -------------------------------------*/
#define SOC_UHCI_NUM (1UL)
// TODO: IDF-5679 (Copy from esp32c3, need check)
/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/
#define SOC_COEX_HW_PTI (1)
/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/
#define SOC_PHY_DIG_REGS_MEM_SIZE (21*4)
// TODO: IDF-5679 (Copy from esp32c3, need check)
/*--------------- WIFI LIGHT SLEEP CLOCK WIDTH CAPS --------------------------*/
#define SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH (12)
// TODO: IDF-5351 (Copy from esp32c3, need check)
/*-------------------------- Power Management CAPS ----------------------------*/
#define SOC_PM_SUPPORT_EXT1_WAKEUP (1)
#define SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN (1) /*!<Supports one bit per pin to configure the EXT1 trigger level */
components/soc/esp32p4/register/hw_ver3/soc/dw_gdma_struct.h
-2
View File
@@ -10,8 +10,6 @@
extern "C" {
#endif
// TODO: IDF-13429
/** Group: Version Register */
/** Type of id0 register
* NA
components/soc/esp32s31/include/soc/clk_tree_defs.h
+1 -2
View File
@@ -271,8 +271,7 @@ typedef enum {
SPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as SPI source clock */
SPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST_20M as SPI source clock */
SPI_CLK_SRC_SPLL = SOC_MOD_CLK_SPLL, /*!< Select SPLL as SPI source clock */
// TODO: IDF-8313, use PLL as default
SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as default source clock */
SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_SPLL, /*!< Select XTAL as default source clock */
} soc_periph_spi_clk_src_t;
/////////////////////////////////////////////////FLASH////////////////////////////////////////////////////////////////////
components/soc/esp32s31/include/soc/soc_caps.h
+3
View File
@@ -19,6 +19,9 @@
#if __has_include("soc/soc_caps_eval.h")
#include "soc/soc_caps_eval.h"
#endif
#define _SOC_CAPS_TARGET_IS_ESP32S31 1 // [gen_soc_caps:ignore]
/*-------------------------- COMMON CAPS ---------------------------------------*/
// #define SOC_ADC_SUPPORTED 1 // TODO: [ESP32S31] IDF-14741
// #define SOC_ANA_CMPR_SUPPORTED 1 // TODO: [ESP32S31] IDF-14787
components/spi_flash/test_apps/esp_flash/main/test_esp_flash_def.h
+1 -1
View File
@@ -142,7 +142,7 @@ typedef void (*flash_test_func_t)(const esp_partition_t *part);
#define TEST_CASE_MULTI_FLASH TEST_CASE_MULTI_FLASH_IGNORE
#define TEST_CASE_MULTI_FLASH_LONG TEST_CASE_MULTI_FLASH_IGNORE
#else
#if CONFIG_FREERTOS_SMP // IDF-5260
#if CONFIG_FREERTOS_SMP // IDF-5826
#define TEST_CASE_MULTI_FLASH(STR, FUNC_TO_RUN) \
TEST_CASE(STR", "TEST_CHIP_NUM_STR" chips", "[esp_flash_multi][test_env=UT_T1_ESP_FLASH][timeout=60]") {flash_test_func(FUNC_TO_RUN, TEST_CONFIG_NUM);}
#else
components/tcp_transport/test_apps/main/test_transport_fixtures.c
+3 -3
View File
@@ -259,17 +259,17 @@ void tcp_transport_test_connection_timeout(esp_transport_handle_t transport_unde
TEST_ASSERT_NOT_NULL(test);
// Roughly measure tick-time spent while trying to connect
#if !CONFIG_FREERTOS_SMP // IDF-5225 - timeout is several times shorter than expected, probably not measured correctly
#if !CONFIG_FREERTOS_SMP // IDF-5826 - timeout is several times shorter than expected, probably not measured correctly
TickType_t start = xTaskGetTickCount();
#endif
EventBits_t bits = xEventGroupWaitBits(test->tcp_connect_done, TCP_CONNECT_DONE, true, true, test->max_wait);
#if !CONFIG_FREERTOS_SMP // IDF-5225 - timeout is several times shorter than expected, probably not measured correctly
#if !CONFIG_FREERTOS_SMP // IDF-5826 - timeout is several times shorter than expected, probably not measured correctly
TickType_t end = xTaskGetTickCount();
#endif
TEST_ASSERT_EQUAL(TCP_CONNECT_DONE, TCP_CONNECT_DONE & bits); // Connection has finished
#if !CONFIG_FREERTOS_SMP // IDF-5225 - timeout is several times shorter than expected, probably not measured correctly
#if !CONFIG_FREERTOS_SMP // IDF-5826 - timeout is several times shorter than expected, probably not measured correctly
TEST_ASSERT_EQUAL(-1, test->connect_return_value); // Connection failed with -1
// Test connection attempt took expected timeout value
TEST_ASSERT_INT_WITHIN(pdMS_TO_TICKS(params.timeout_ms/5), pdMS_TO_TICKS(params.timeout_ms), end-start);
components/ulp/ulp_riscv/ulp_riscv.c
+2 -9
View File
@@ -103,7 +103,7 @@ esp_err_t ulp_riscv_config_and_run(ulp_riscv_cfg_t* cfg)
/* Reset COCPU when power on. */
SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
/* The coprocessor cpu trap signal doesnt have a stable reset value,
/* The coprocessor cpu trap signal doesn't have a stable reset value,
force ULP-RISC-V clock on to stop RTC_COCPU_TRAP_TRIG_EN from waking the CPU*/
SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_CLK_FO);
@@ -123,7 +123,7 @@ esp_err_t ulp_riscv_config_and_run(ulp_riscv_cfg_t* cfg)
/* Reset COCPU when power on. */
SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
/* The coprocessor cpu trap signal doesnt have a stable reset value,
/* The coprocessor cpu trap signal doesn't have a stable reset value,
force ULP-RISC-V clock on to stop RTC_COCPU_TRAP_TRIG_EN from waking the CPU*/
SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_CLK_FO);
@@ -132,13 +132,6 @@ esp_err_t ulp_riscv_config_and_run(ulp_riscv_cfg_t* cfg)
/* wait for at least 1 RTC_SLOW_CLK cycle */
esp_rom_delay_us(20);
/* We do not select RISC-V as the Coprocessor here as this could lead to a hang
* in the main CPU. Instead, we reset RTC_CNTL_COCPU_SEL after we have enabled the ULP timer.
*
* IDF-4510
*/
//CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SEL);
/* Select ULP-RISC-V to send the DONE signal */
SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_DONE_FORCE);
tools/ci/sg_rules/recommend_way_to_use_soc_caps.yml
-17
View File
@@ -1,17 +0,0 @@
# Refer to https://ast-grep.github.io/guide/rule-config.html for Rule Essentials
id: recommended-way-to-use-soc-caps
message: Don't expand SOC_CAPS macro manually
severity: error # error, warning, info, hint
note: Should use the macro functions offered by soc_caps_eval.h to compute the SOC_CAPS macro
language: C
files:
- "components/**/*"
- "examples/**/*"
ignores:
- "components/soc/**/soc_caps.h"
- "components/soc/**/soc_caps_full.h"
- "components/soc/**/soc_caps_eval.h"
rule:
kind: identifier
pattern: $A
regex: "^_SOC_CAPS_"