feat(dma): graduate the dma driver into a single component

components/esp_driver_uart/test_apps/uhci/main/test_uhci.c

@@ -10,6 +10,7 @@
 #include "test_utils.h"
 #include "driver/uart.h"
 #include "driver/uhci.h"
+#include "hal/gdma_periph.h"
 
 #define DATA_LENGTH 1024
 #define EX_UART_NUM 1
@@ -246,7 +247,7 @@ TEST_CASE("UHCI write and receive with length eof", "[uhci]")
 }
 
 #if CONFIG_SPIRAM
-#if SOC_AHB_GDMA_SUPPORT_PSRAM
+#if GDMA_LL_GET(AHB_PSRAM_CAPABLE)
 static void uhci_receive_test_in_psram(void *arg)
 {
     uhci_controller_handle_t uhci_ctrl = ((uhci_controller_handle_t *)arg)[0];

components/esp_hal_dma/CMakeLists.txt

@@ -0,0 +1,47 @@
+idf_build_get_property(target IDF_TARGET)
+if(${target} STREQUAL "linux")
+    return() # This component is not supported by the POSIX/Linux simulator
+endif()
+
+set(srcs)
+set(public_include "include")
+
+if(EXISTS "${CMAKE_CURRENT_LIST_DIR}/${target}/include")
+    list(APPEND public_include "${target}/include")
+endif()
+
+if(CONFIG_SOC_GDMA_SUPPORTED)
+    list(APPEND srcs "gdma_hal_top.c" "${target}/gdma_periph.c")
+
+    if(CONFIG_SOC_GDMA_SUPPORT_CRC)
+        list(APPEND srcs "gdma_hal_crc_gen.c")
+    endif()
+
+    if(CONFIG_SOC_AHB_GDMA_VERSION EQUAL 1)
+        list(APPEND srcs "gdma_hal_ahb_v1.c")
+    endif()
+
+    if(CONFIG_SOC_AHB_GDMA_VERSION EQUAL 2)
+        list(APPEND srcs "gdma_hal_ahb_v2.c")
+    endif()
+
+    if(CONFIG_SOC_AXI_GDMA_SUPPORTED)
+        list(APPEND srcs "gdma_hal_axi.c")
+    endif()
+endif()
+
+if(CONFIG_SOC_DW_GDMA_SUPPORTED)
+    list(APPEND srcs "dw_gdma_hal.c")
+endif()
+
+if(CONFIG_SOC_DMA2D_SUPPORTED)
+    list(APPEND srcs "dma2d_hal.c" "${target}/dma2d_periph.c")
+endif()
+
+if(CONFIG_SOC_CP_DMA_SUPPORTED)
+    list(APPEND srcs "cp_dma_hal.c")
+endif()
+
+idf_component_register(SRCS ${srcs}
+                       INCLUDE_DIRS ${public_include}
+                       REQUIRES soc hal)

components/esp_hal_dma/README.md

@@ -0,0 +1,48 @@
+# ESP Hardware Abstraction Layer for DMA Peripheral(s)
+
+> [!NOTE]
+> This component is currently in beta. Its API, behavior, and compatibility may change at any time and without notice; backward compatibility is not guaranteed. Use caution when integrating into production systems.
+
+## Overview
+
+The `esp_hal_dma` component provides a **Hardware Abstraction Layer** for Direct Memory Access (DMA) controllers across all ESP-IDF supported targets. DMA allows peripherals to access memory directly without CPU intervention, significantly improving data transfer efficiency and reducing CPU load.
+
+## Architecture
+
+The DMA HAL is structured in two main sub-layers:
+
+1. **HAL Layer (Upper)**: Defines the operational steps and data structures required to control DMA peripherals (e.g., initialization, channel configuration, transfer start/stop).
+
+2. **Low-Level Layer (Bottom)**: Serves as a translation layer between the HAL and the register files defined in the `soc` component, handling target-specific register configurations.
+
+## Supported DMA Controllers
+
+This HAL supports various DMA controller types depending on the ESP chip:
+
+- **GDMA (General DMA)**: Available in multiple versions:
+  - AHB GDMA (Version 1 & 2)
+  - AXI GDMA
+- **DW GDMA**: DesignWare DMA controller
+- **DMA2D**: 2D DMA controller for efficient image processing operations
+- **CP DMA**: A dedicated DMA controller designed for highly efficient memory copy
+
+## Features
+
+- Channel allocation and management
+- Transfer direction control (TX/RX)
+- Trigger peripheral selection (M2M, SPI, I2S, etc.)
+- Priority configuration for channels
+- DMA descriptor handling
+- CRC calculation support (on supported chips)
+- ETM (Event Task Matrix) event handling
+
+## Usage
+
+The HAL functions primarily serve ESP-IDF peripheral drivers such as `esp_private/gdma.h`.
+
+Advanced developers can use these interfaces directly when implementing custom drivers, with the understanding that API stability is not guaranteed.
+
+## Dependencies
+
+- `soc`: Provides chip-specific register definitions
+- `hal`: Core hardware abstraction utilities and macros

components/esp_hal_dma/cp_dma_hal.c

@@ -1,9 +1,10 @@
 /*
- * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <stdlib.h>
 #include "soc/soc_caps.h"
 #include "hal/cp_dma_hal.h"
 #include "hal/cp_dma_ll.h"
@@ -21,7 +22,7 @@ void cp_dma_hal_init(cp_dma_hal_context_t *hal, const cp_dma_hal_config_t *confi
     cp_dma_ll_enable_owner_check(hal->dev, true);
 }
 
-void cp_dma_hal_set_desc_base_addr(cp_dma_hal_context_t *hal, intptr_t outlink_base, intptr_t inlink_base)
+void cp_dma_hal_set_desc_base_addr(cp_dma_hal_context_t *hal, uint32_t outlink_base, uint32_t inlink_base)
 {
     /* set base address of the first descriptor */
     cp_dma_ll_tx_set_descriptor_base_addr(hal->dev, outlink_base);
@@ -62,13 +63,3 @@ void cp_dma_hal_clear_intr_status(cp_dma_hal_context_t *hal, uint32_t mask)
 {
     cp_dma_ll_clear_intr_status(hal->dev, mask);
 }
-
-void cp_dma_hal_restart_tx(cp_dma_hal_context_t *hal)
-{
-    cp_dma_ll_restart_tx(hal->dev);
-}
-
-void cp_dma_hal_restart_rx(cp_dma_hal_context_t *hal)
-{
-    cp_dma_ll_restart_rx(hal->dev);
-}

components/esp_hal_dma/esp32c2/gdma_periph.c

@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include "soc/gdma_periph.h"
+#include "hal/gdma_periph.h"
 
 const gdma_signal_conn_t gdma_periph_signals = {
     .groups = {

components/esp_hal_dma/esp32c2/include/hal/gdma_ll.h

@@ -13,6 +13,11 @@
 #include "soc/gdma_reg.h"
 #include "soc/system_struct.h"
 
+#define GDMA_LL_GET(_attr)          GDMA_LL_ ## _attr
+
+#define GDMA_LL_INST_NUM            1
+#define GDMA_LL_PAIRS_PER_INST      GDMA_LL_AHB_PAIRS_PER_GROUP
+
 #ifdef __cplusplus
 extern "C" {
 #endif

components/esp_hal_dma/esp32c3/gdma_periph.c

@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include "soc/gdma_periph.h"
+#include "hal/gdma_periph.h"
 
 const gdma_signal_conn_t gdma_periph_signals = {
     .groups = {

components/esp_hal_dma/esp32c3/include/hal/gdma_ll.h

@@ -13,6 +13,11 @@
 #include "soc/gdma_reg.h"
 #include "soc/system_struct.h"
 
+#define GDMA_LL_GET(_attr)          GDMA_LL_ ## _attr
+
+#define GDMA_LL_INST_NUM            1
+#define GDMA_LL_PAIRS_PER_INST      GDMA_LL_AHB_PAIRS_PER_GROUP
+
 #ifdef __cplusplus
 extern "C" {
 #endif

components/esp_hal_dma/esp32c5/gdma_periph.c

@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include "soc/gdma_periph.h"
+#include "hal/gdma_periph.h"
 #include "soc/ahb_dma_reg.h"
 
 const gdma_signal_conn_t gdma_periph_signals = {
@@ -144,7 +144,7 @@ static const regdma_entries_config_t gdma_g0p2_regs_retention[] = {
     },
 };
 
-const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[SOC_GDMA_NUM_GROUPS_MAX][SOC_GDMA_PAIRS_PER_GROUP_MAX] = {
+const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[1][3] = {
     [0] = {
         [0] = {
             gdma_g0p0_regs_retention,

components/esp_hal_dma/esp32c5/include/hal/gdma_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -7,7 +7,15 @@
 
 #include "soc/pcr_struct.h"
 #include "hal/ahb_dma_ll.h"
-#define GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE 1 // AHB GDMA supports adjustable burst size
+
+#define GDMA_LL_GET(_attr)          GDMA_LL_ ## _attr
+
+#define GDMA_LL_INST_NUM            1
+#define GDMA_LL_PAIRS_PER_INST      GDMA_LL_AHB_PAIRS_PER_GROUP
+
+#define GDMA_LL_AHB_PSRAM_CAPABLE         1
+
+#define GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE 1  // AHB GDMA supports adjustable burst size
 #define GDMA_LL_MAX_BURST_SIZE_PSRAM      32 // PSRAM controller doesn't support burst access with size > 32 bytes
 
 #ifdef __cplusplus

components/esp_hal_dma/esp32c6/gdma_periph.c

@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include "soc/gdma_periph.h"
+#include "hal/gdma_periph.h"
 #include "soc/gdma_reg.h"
 
 const gdma_signal_conn_t gdma_periph_signals = {
@@ -99,7 +99,7 @@ static const regdma_entries_config_t gdma_g0p2_regs_retention[] = {
     },
 };
 
-const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[SOC_GDMA_NUM_GROUPS_MAX][SOC_GDMA_PAIRS_PER_GROUP_MAX] = {
+const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[1][3] = {
     [0] = {
         [0] = {
             gdma_g0p0_regs_retention,

components/esp_hal_dma/esp32c6/include/hal/gdma_ll.h

@@ -14,6 +14,11 @@
 #include "soc/soc_etm_source.h"
 #include "soc/pcr_struct.h"
 
+#define GDMA_LL_GET(_attr)          GDMA_LL_ ## _attr
+
+#define GDMA_LL_INST_NUM            1
+#define GDMA_LL_PAIRS_PER_INST      GDMA_LL_AHB_PAIRS_PER_GROUP
+
 #ifdef __cplusplus
 extern "C" {
 #endif

components/esp_hal_dma/esp32c61/gdma_periph.c

@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include "soc/gdma_periph.h"
+#include "hal/gdma_periph.h"
 #include "soc/ahb_dma_reg.h"
 
 const gdma_signal_conn_t gdma_periph_signals = {
@@ -100,7 +100,7 @@ static const regdma_entries_config_t gdma_g0p1_regs_retention[] = {
     },
 };
 
-const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[SOC_GDMA_NUM_GROUPS_MAX][SOC_GDMA_PAIRS_PER_GROUP_MAX] = {
+const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[1][2] = {
     [0] = {
         [0] = {
             gdma_g0p0_regs_retention,

components/esp_hal_dma/esp32c61/include/hal/gdma_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -7,7 +7,15 @@
 
 #include "soc/pcr_struct.h"
 #include "hal/ahb_dma_ll.h"
-#define GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE 1 // AHB GDMA supports adjustable burst size
+
+#define GDMA_LL_GET(_attr)          GDMA_LL_ ## _attr
+
+#define GDMA_LL_INST_NUM            1
+#define GDMA_LL_PAIRS_PER_INST      GDMA_LL_AHB_PAIRS_PER_GROUP
+
+#define GDMA_LL_AHB_PSRAM_CAPABLE         1
+
+#define GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE 1  // AHB GDMA supports adjustable burst size
 #define GDMA_LL_MAX_BURST_SIZE_PSRAM      32 // PSRAM controller doesn't support burst access with size > 32 bytes
 
 #ifdef __cplusplus

components/esp_hal_dma/esp32h2/gdma_periph.c

@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include "soc/gdma_periph.h"
+#include "hal/gdma_periph.h"
 #include "soc/gdma_reg.h"
 
 const gdma_signal_conn_t gdma_periph_signals = {
@@ -99,7 +99,7 @@ static const regdma_entries_config_t gdma_g0p2_regs_retention[] = {
     },
 };
 
-const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[SOC_GDMA_NUM_GROUPS_MAX][SOC_GDMA_PAIRS_PER_GROUP_MAX] = {
+const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[1][3] = {
     [0] = {
         [0] = {
             gdma_g0p0_regs_retention,

components/esp_hal_dma/esp32h2/include/hal/gdma_ll.h

@@ -14,6 +14,11 @@
 #include "soc/soc_etm_source.h"
 #include "soc/pcr_struct.h"
 
+#define GDMA_LL_GET(_attr)          GDMA_LL_ ## _attr
+
+#define GDMA_LL_INST_NUM            1
+#define GDMA_LL_PAIRS_PER_INST      GDMA_LL_AHB_PAIRS_PER_GROUP
+
 #ifdef __cplusplus
 extern "C" {
 #endif

components/esp_hal_dma/esp32h21/gdma_periph.c

@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include "soc/gdma_periph.h"
+#include "hal/gdma_periph.h"
 #include "soc/gdma_reg.h"
 
 const gdma_signal_conn_t gdma_periph_signals = {
@@ -100,7 +100,7 @@ static const regdma_entries_config_t gdma_g0p2_regs_retention[] = {
     },
 };
 
-const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[SOC_GDMA_NUM_GROUPS_MAX][SOC_GDMA_PAIRS_PER_GROUP_MAX] = {
+const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[1][3] = {
     [0] = {
         [0] = {
             gdma_g0p0_regs_retention,

components/esp_hal_dma/esp32h21/include/hal/gdma_ll.h

@@ -14,6 +14,11 @@
 #include "soc/soc_etm_source.h"
 #include "soc/pcr_struct.h"
 
+#define GDMA_LL_GET(_attr)          GDMA_LL_ ## _attr
+
+#define GDMA_LL_INST_NUM            1
+#define GDMA_LL_PAIRS_PER_INST      GDMA_LL_AHB_PAIRS_PER_GROUP
+
 #ifdef __cplusplus
 extern "C" {
 #endif

components/esp_hal_dma/esp32h4/gdma_periph.c

@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include "soc/gdma_periph.h"
+#include "hal/gdma_periph.h"
 #include "soc/ahb_dma_reg.h"
 
 const gdma_signal_conn_t gdma_periph_signals = {
@@ -274,7 +274,7 @@ static const regdma_entries_config_t gdma_g0p4_regs_retention[] = {
     }, \
 };
 
-const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[SOC_GDMA_NUM_GROUPS_MAX][SOC_GDMA_PAIRS_PER_GROUP_MAX] = {
+const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[1][5] = {
     [0] = {
         [0] = {
             gdma_g0p0_regs_retention,

components/esp_hal_dma/esp32h4/include/hal/gdma_ll.h

@@ -7,7 +7,15 @@
 
 #include "soc/pcr_struct.h"
 #include "hal/ahb_dma_ll.h"
-#define GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE 1 // AHB GDMA supports adjustable burst size
+
+#define GDMA_LL_GET(_attr)          GDMA_LL_ ## _attr
+
+#define GDMA_LL_INST_NUM            1
+#define GDMA_LL_PAIRS_PER_INST      GDMA_LL_AHB_PAIRS_PER_GROUP
+
+#define GDMA_LL_AHB_PSRAM_CAPABLE         1
+
+#define GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE 1  // AHB GDMA supports adjustable burst size
 #define GDMA_LL_MAX_BURST_SIZE_PSRAM      64 // PSRAM support INCR16
 
 #ifdef __cplusplus

components/esp_hal_dma/esp32p4/dma2d_periph.c

@@ -1,10 +1,10 @@
 /*
- * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include "soc/dma2d_periph.h"
+#include "hal/dma2d_periph.h"
 #include "soc/interrupts.h"
 
 const dma2d_signal_conn_t dma2d_periph_signals = {
@@ -14,12 +14,16 @@ const dma2d_signal_conn_t dma2d_periph_signals = {
                 [0] = ETS_DMA2D_OUT_CH0_INTR_SOURCE,
                 [1] = ETS_DMA2D_OUT_CH1_INTR_SOURCE,
                 [2] = ETS_DMA2D_OUT_CH2_INTR_SOURCE,
-                [3] = ETS_DMA2D_OUT_CH3_INTR_SOURCE, // This channel only exists on P4 ver. >= 3.0
+#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
+                [3] = ETS_DMA2D_OUT_CH3_INTR_SOURCE,
+#endif
             },
             .rx_irq_id = {
                 [0] = ETS_DMA2D_IN_CH0_INTR_SOURCE,
                 [1] = ETS_DMA2D_IN_CH1_INTR_SOURCE,
-                [2] = ETS_DMA2D_IN_CH2_INTR_SOURCE, // This channel only exists on P4 ver. >= 3.0
+#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
+                [2] = ETS_DMA2D_IN_CH2_INTR_SOURCE,
+#endif
             }
         }
     }

components/esp_hal_dma/esp32p4/gdma_periph.c

@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include "soc/gdma_periph.h"
+#include "hal/gdma_periph.h"
 #include "soc/ahb_dma_reg.h"
 #include "soc/axi_dma_reg.h"
 
@@ -264,7 +264,7 @@ static const regdma_entries_config_t axi_dma_g1p2_regs_retention[] = {
     },
 };
 
-const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[SOC_GDMA_NUM_GROUPS_MAX][SOC_GDMA_PAIRS_PER_GROUP_MAX] = {
+const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[2][3] = {
     [0] = {
         [0] = {
             ahb_dma_g0p0_regs_retention,

components/esp_hal_dma/esp32p4/include/hal/ahb_dma_ll.h

@@ -10,9 +10,9 @@
 #include <stdbool.h>
 #include "hal/assert.h"
 #include "hal/misc.h"
+#include "hal/config.h"
 #include "hal/hal_utils.h"
 #include "hal/gdma_types.h"
-#include "hal/gdma_ll.h"
 #include "soc/ahb_dma_struct.h"
 #include "soc/ahb_dma_reg.h"
 
@@ -161,7 +161,7 @@ static inline void ahb_dma_ll_rx_enable_descriptor_burst(ahb_dma_dev_t *dev, uin
     dev->channel[channel].in.in_conf0.indscr_burst_en_chn = enable;
 }
 
-#if GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE
+#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
 /**
  * @brief Set RX channel burst size
  */
@@ -336,7 +336,7 @@ static inline void ahb_dma_ll_rx_connect_to_periph(ahb_dma_dev_t *dev, uint32_t
  */
 static inline void ahb_dma_ll_rx_disconnect_from_periph(ahb_dma_dev_t *dev, uint32_t channel)
 {
-    dev->channel[channel].in.in_peri_sel.peri_in_sel_chn = GDMA_LL_INVALID_PERIPH_ID;
+    dev->channel[channel].in.in_peri_sel.peri_in_sel_chn = 0x3F;
     dev->channel[channel].in.in_conf0.mem_trans_en_chn = false;
 }
 
@@ -443,7 +443,7 @@ static inline void ahb_dma_ll_tx_enable_descriptor_burst(ahb_dma_dev_t *dev, uin
     dev->channel[channel].out.out_conf0.outdscr_burst_en_chn = enable;
 }
 
-#if GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE
+#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
 /**
  * @brief Set TX channel burst size
  */
@@ -617,7 +617,7 @@ static inline void ahb_dma_ll_tx_connect_to_periph(ahb_dma_dev_t *dev, uint32_t
  */
 static inline void ahb_dma_ll_tx_disconnect_from_periph(ahb_dma_dev_t *dev, uint32_t channel)
 {
-    dev->channel[channel].out.out_peri_sel.peri_out_sel_chn = GDMA_LL_INVALID_PERIPH_ID;
+    dev->channel[channel].out.out_peri_sel.peri_out_sel_chn = 0x3F;
 }
 
 /**

components/esp_hal_dma/esp32p4/include/hal/axi_dma_ll.h

@@ -278,7 +278,7 @@ static inline void axi_dma_ll_rx_connect_to_periph(axi_dma_dev_t *dev, uint32_t
  */
 static inline void axi_dma_ll_rx_disconnect_from_periph(axi_dma_dev_t *dev, uint32_t channel)
 {
-    dev->in[channel].conf.in_peri_sel.peri_in_sel_chn = GDMA_LL_INVALID_PERIPH_ID;
+    dev->in[channel].conf.in_peri_sel.peri_in_sel_chn = 0x3F;
     dev->in[channel].conf.in_conf0.mem_trans_en_chn = false;
 }
 
@@ -513,7 +513,7 @@ static inline void axi_dma_ll_tx_connect_to_periph(axi_dma_dev_t *dev, uint32_t
  */
 static inline void axi_dma_ll_tx_disconnect_from_periph(axi_dma_dev_t *dev, uint32_t channel)
 {
-    dev->out[channel].conf.out_peri_sel.peri_out_sel_chn = GDMA_LL_INVALID_PERIPH_ID;
+    dev->out[channel].conf.out_peri_sel.peri_out_sel_chn = 0x3F;
 }
 
 /**

components/esp_hal_dma/esp32p4/include/hal/dma2d_ll.h

@@ -11,25 +11,32 @@
 #include "hal/dma2d_types.h"
 #include "soc/dma2d_channel.h"
 #include "soc/dma2d_struct.h"
-#include "soc/dma2d_periph.h"
 #include "hal/misc.h"
 #include "hal/assert.h"
 #include "hal/config.h"
 #include "soc/soc.h"
 #include "soc/hp_sys_clkrst_struct.h"
 
-#ifdef __cplusplus
-extern "C" {
-#endif
+// Number of 2D-DMA instances
+#define DMA2D_LL_INST_NUM       1
+#define DMA2D_LL_GET_HW(id)     (((id) == 0) ? (&DMA2D) : NULL)
 
-#define DMA2D_LL_GET_HW(id)                  (((id) == 0) ? (&DMA2D) : NULL)
+#define DMA2D_LL_GET(_attr)     DMA2D_LL_ ## _attr
 
 #if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
-#define DMA2D_LL_TX_CHANNELS_PER_GROUP             SOC_DMA2D_ATTR(TX_CHANS_PER_INST)  // Number of 2D-DMA TX (OUT) channels in each group
-#define DMA2D_LL_RX_CHANNELS_PER_GROUP             SOC_DMA2D_ATTR(RX_CHANS_PER_INST)  // Number of 2D-DMA RX (IN) channels in each group
+// Number of 2D-DMA TX (OUT) channels in each instance
+#define DMA2D_LL_TX_CHANS_PER_INST      4
+// Number of 2D-DMA RX (IN) channels in each instance
+#define DMA2D_LL_RX_CHANS_PER_INST      3
 #else
-#define DMA2D_LL_TX_CHANNELS_PER_GROUP             (3)  // Number of 2D-DMA TX (OUT) channels in each group
-#define DMA2D_LL_RX_CHANNELS_PER_GROUP             (2)  // Number of 2D-DMA RX (IN) channels in each group
+// Number of 2D-DMA TX (OUT) channels in each instance
+#define DMA2D_LL_TX_CHANS_PER_INST      3
+// Number of 2D-DMA RX (IN) channels in each instance
+#define DMA2D_LL_RX_CHANS_PER_INST      2
+#endif
+
+#ifdef __cplusplus
+extern "C" {
 #endif
 
 // 2D-DMA interrupts

components/esp_hal_dma/esp32p4/include/hal/gdma_ll.h

@@ -12,17 +12,23 @@
 
 #include <stdint.h>
 #include <stdbool.h>
+#include <sys/param.h>
 #include "soc/hp_sys_clkrst_struct.h"
 #include "soc/soc_etm_source.h"
 #include "hal/config.h"
 
+#define GDMA_LL_GET(_attr)          GDMA_LL_ ## _attr
+
+// 2 GDMA instances: AHB-DMA and AXI-DMA
+#define GDMA_LL_INST_NUM            2
+
+#define GDMA_LL_PAIRS_PER_INST      MAX(GDMA_LL_AHB_PAIRS_PER_GROUP, GDMA_LL_AXI_PAIRS_PER_GROUP)
+
 #define GDMA_LL_CHANNEL_MAX_PRIORITY 5 // supported priority levels: [0,5]
 
 #define GDMA_LL_RX_EVENT_MASK       (0x1F)
 #define GDMA_LL_TX_EVENT_MASK       (0x0F)
 
-#define GDMA_LL_INVALID_PERIPH_ID   (0x3F)
-
 #define GDMA_LL_EVENT_TX_TOTAL_EOF  (1<<3)
 #define GDMA_LL_EVENT_TX_DESC_ERROR (1<<2)
 #define GDMA_LL_EVENT_TX_EOF        (1<<1)
@@ -46,6 +52,9 @@
 #define GDMA_LL_AHB_MAX_CRC_BIT_WIDTH   32 // Max CRC bit width supported by AHB GDMA
 #define GDMA_LL_AXI_MAX_CRC_BIT_WIDTH   16 // Max CRC bit width supported by AXI GDMA
 
+#define GDMA_LL_AHB_PSRAM_CAPABLE       1
+#define GDMA_LL_AXI_PSRAM_CAPABLE       1
+
 #define GDMA_LL_AHB_DESC_ALIGNMENT      4
 #define GDMA_LL_AXI_DESC_ALIGNMENT      8
 #define GDMA_LL_MAX_BURST_SIZE_PSRAM    128 // PSRAM controller doesn't support burst access with size > 128 bytes

components/esp_hal_dma/esp32s2/include/hal/cp_dma_ll.h

@@ -1,19 +1,19 @@
 /*
- * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #pragma once
 
-#ifdef __cplusplus
-extern "C" {
-#endif
-
 #include <stdint.h>
 #include <stdbool.h>
 #include "soc/cp_dma_struct.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 #define CP_DMA_LL_EVENT_RX_DONE       (1 << 0)
 #define CP_DMA_LL_EVENT_RX_EOF        (1 << 1)
 #define CP_DMA_LL_EVENT_TX_DONE       (1 << 2)

components/esp_hal_dma/esp32s3/gdma_periph.c

@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include "soc/gdma_periph.h"
+#include "hal/gdma_periph.h"
 
 const gdma_signal_conn_t gdma_periph_signals = {
     .groups = {

components/esp_hal_dma/esp32s3/include/hal/gdma_ll.h

@@ -14,6 +14,11 @@
 #include "soc/gdma_reg.h"
 #include "soc/system_struct.h"
 
+#define GDMA_LL_GET(_attr)          GDMA_LL_ ## _attr
+
+#define GDMA_LL_INST_NUM            1
+#define GDMA_LL_PAIRS_PER_INST      GDMA_LL_AHB_PAIRS_PER_GROUP
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -60,6 +65,8 @@ extern "C" {
 #define GDMA_LL_AHB_NUM_GROUPS        1 // Number of AHB GDMA groups
 #define GDMA_LL_AHB_PAIRS_PER_GROUP   5 // Number of GDMA pairs in each AHB group
 
+#define GDMA_LL_AHB_PSRAM_CAPABLE     1
+
 #define GDMA_LL_AHB_DESC_ALIGNMENT    4
 
 #define GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE 1 // AHB GDMA supports adjustable burst size

components/esp_hal_dma/gdma_hal_ahb_v1.c

@@ -91,7 +91,7 @@ void gdma_ahb_hal_enable_burst(gdma_hal_context_t *hal, int chan_id, gdma_channe
     }
 }
 
-#if GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE
+#if GDMA_LL_GET(AHB_BURST_SIZE_ADJUSTABLE)
 void gdma_ahb_hal_set_burst_size(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t burst_sz)
 {
     if (dir == GDMA_CHANNEL_DIRECTION_RX) {
@@ -100,7 +100,7 @@ void gdma_ahb_hal_set_burst_size(gdma_hal_context_t *hal, int chan_id, gdma_chan
         gdma_ll_tx_set_burst_size(hal->dev, chan_id, burst_sz);
     }
 }
-#endif // GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE
+#endif // GDMA_LL_GET(AHB_BURST_SIZE_ADJUSTABLE)
 
 void gdma_ahb_hal_set_strategy(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_owner_check, bool en_desc_write_back, bool eof_till_popped)
 {
@@ -195,8 +195,8 @@ void gdma_ahb_hal_init(gdma_hal_context_t *hal, const gdma_hal_config_t *config)
 #if SOC_GDMA_SUPPORT_ETM
     hal->enable_etm_task = gdma_ahb_hal_enable_etm_task;
 #endif
-#if GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE
+#if GDMA_LL_GET(AHB_BURST_SIZE_ADJUSTABLE)
     hal->set_burst_size = gdma_ahb_hal_set_burst_size;
-#endif // GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE
+#endif // GDMA_LL_GET(AHB_BURST_SIZE_ADJUSTABLE)
     hal->priv_data = &gdma_ahb_hal_priv_data;
 }

components/esp_hal_dma/gdma_hal_ahb_v2.c

@@ -105,7 +105,7 @@ void gdma_ahb_hal_set_strategy(gdma_hal_context_t *hal, int chan_id, gdma_channe
     }
 }
 
-#if GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE
+#if GDMA_LL_GET(AHB_BURST_SIZE_ADJUSTABLE)
 void gdma_ahb_hal_set_burst_size(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t burst_sz)
 {
     if (dir == GDMA_CHANNEL_DIRECTION_RX) {
@@ -114,7 +114,7 @@ void gdma_ahb_hal_set_burst_size(gdma_hal_context_t *hal, int chan_id, gdma_chan
         ahb_dma_ll_tx_set_burst_size(hal->ahb_dma_dev, chan_id, burst_sz);
     }
 }
-#endif // GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE
+#endif // GDMA_LL_GET(AHB_BURST_SIZE_ADJUSTABLE)
 
 void gdma_ahb_hal_enable_intr(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t intr_event_mask, bool en_or_dis)
 {
@@ -269,15 +269,15 @@ void gdma_ahb_hal_init(gdma_hal_context_t *hal, const gdma_hal_config_t *config)
 #if SOC_GDMA_SUPPORT_ETM
     hal->enable_etm_task = gdma_ahb_hal_enable_etm_task;
 #endif // SOC_GDMA_SUPPORT_ETM
-#if GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE
+#if GDMA_LL_GET(AHB_BURST_SIZE_ADJUSTABLE)
     hal->set_burst_size = gdma_ahb_hal_set_burst_size;
-#endif // GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE
+#endif // GDMA_LL_GET(AHB_BURST_SIZE_ADJUSTABLE)
 #if SOC_GDMA_SUPPORT_WEIGHTED_ARBITRATION
     hal->set_weight = gdma_ahb_hal_set_weight;
     if (config->flags.enable_weighted_arbitration) {
         ahb_dma_ll_enable_weighted_arb(hal->ahb_dma_dev, true);
         // always enable weighted arbitration optimize
-        for (int i = 0; i < SOC_GDMA_PAIRS_PER_GROUP_MAX; i++) {
+        for (int i = 0; i < GDMA_LL_GET(PAIRS_PER_INST); i++) {
             ahb_dma_ll_tx_enable_weighted_arb_opt(hal->ahb_dma_dev, i, true);
             ahb_dma_ll_rx_enable_weighted_arb_opt(hal->ahb_dma_dev, i, true);
         }

components/esp_hal_dma/include/hal/cp_dma_hal.h

@@ -0,0 +1,67 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct cp_dma_dev_t *cp_dma_soc_handle_t; // CP DMA SOC layer handle
+
+/**
+ * @brief HAL context
+ */
+typedef struct {
+    cp_dma_soc_handle_t dev; // CP DMA SOC layer handle (i.e. register base address)
+} cp_dma_hal_context_t;
+
+typedef struct {
+} cp_dma_hal_config_t;
+
+/**
+ * @brief Initialize HAL layer context
+ *
+ * @param hal HAL layer context, whose memory should be allocated at driver layer
+ * @param config configuration for the HAL layer
+ */
+void cp_dma_hal_init(cp_dma_hal_context_t *hal, const cp_dma_hal_config_t *config);
+
+/**
+ * @brief Deinitialize HAL layer context
+ *
+ * @param hal HAL layer context
+ */
+void cp_dma_hal_deinit(cp_dma_hal_context_t *hal);
+
+/**
+ * @brief Set descriptor base address
+ *
+ * @param hal HAL layer context
+ * @param outlink_base Base address of the first outlink descriptor
+ * @param inlink_base Base address of the first inlink descriptor
+ */
+void cp_dma_hal_set_desc_base_addr(cp_dma_hal_context_t *hal, uint32_t outlink_base, uint32_t inlink_base);
+
+/**
+ * @brief Start mem2mem DMA state machine
+ *
+ * @param hal HAL layer context
+ */
+void cp_dma_hal_start(cp_dma_hal_context_t *hal);
+
+/**
+ * @brief Stop mem2mem DMA state machine
+ *
+ * @param hal HAL layer context
+ */
+void cp_dma_hal_stop(cp_dma_hal_context_t *hal);
+
+#ifdef __cplusplus
+}
+#endif

components/esp_hal_dma/include/hal/dma2d_periph.h

@@ -9,20 +9,20 @@
 #include <stdint.h>
 #include "soc/soc_caps_full.h"
 
+#if SOC_HAS(DMA2D)
+#include "hal/dma2d_ll.h"
+#endif
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
 #if SOC_HAS(DMA2D)
-
-// helper macros to access module attributes
-#define SOC_DMA2D_ATTR(_attr)    SOC_MODULE_ATTR(DMA2D, _attr)
-
 typedef struct {
     struct {
-        const int tx_irq_id[SOC_DMA2D_ATTR(TX_CHANS_PER_INST)];
-        const int rx_irq_id[SOC_DMA2D_ATTR(RX_CHANS_PER_INST)];
-    } groups[SOC_DMA2D_ATTR(INST_NUM)];
+        const int tx_irq_id[DMA2D_LL_GET(TX_CHANS_PER_INST)];
+        const int rx_irq_id[DMA2D_LL_GET(RX_CHANS_PER_INST)];
+    } groups[DMA2D_LL_GET(INST_NUM)];
 } dma2d_signal_conn_t;
 
 extern const dma2d_signal_conn_t dma2d_periph_signals;

components/esp_hal_dma/include/hal/gdma_hal.h

@@ -18,7 +18,7 @@
 #if SOC_AHB_GDMA_VERSION == 2
 #include "soc/ahb_dma_struct.h"
 #endif
-#if SOC_AXI_GDMA_SUPPORTED
+#if SOC_HAS(AXI_GDMA)
 #include "soc/axi_dma_struct.h"
 #endif
 
@@ -69,7 +69,7 @@ struct gdma_hal_context_t {
 #if SOC_AHB_GDMA_VERSION == 2
         ahb_dma_dev_t *ahb_dma_dev;
 #endif
-#if SOC_AXI_GDMA_SUPPORTED
+#if SOC_HAS(AXI_GDMA)
         axi_dma_dev_t *axi_dma_dev;
 #endif
         void *generic_dev;

components/esp_hal_dma/include/hal/gdma_periph.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -8,46 +8,49 @@
 
 #include "soc/soc_caps.h"
 #include "soc/periph_defs.h"
-#if SOC_PAU_SUPPORTED
 #include "soc/regdma.h"
+#if SOC_HAS(GDMA)
+#include "hal/gdma_ll.h"
+#endif
+#if SOC_HAS(PAU)
 #include "soc/retention_periph_defs.h"
 #endif
 
+#if CI_TEST_SW_RETENTION
+#define GDMA_RETENTION_ENTRY    REGDMA_SW_TRIGGER_ENTRY
+#else
+#if SOC_PHY_SUPPORTED
+#define GDMA_RETENTION_ENTRY    (ENTRY(0) | ENTRY(2))
+#else
+#define GDMA_RETENTION_ENTRY    (ENTRY(0))
+#endif
+#endif
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#if SOC_GDMA_SUPPORTED
+#if SOC_HAS(GDMA)
 typedef struct {
     struct {
         const shared_periph_module_t module;
         struct {
             const int rx_irq_id;
             const int tx_irq_id;
-        } pairs[SOC_GDMA_PAIRS_PER_GROUP_MAX];
-    } groups[SOC_GDMA_NUM_GROUPS_MAX];
+        } pairs[GDMA_LL_GET(PAIRS_PER_INST)];
+    } groups[GDMA_LL_GET(INST_NUM)];
 } gdma_signal_conn_t;
 
 extern const gdma_signal_conn_t gdma_periph_signals;
 
-#if SOC_GDMA_SUPPORT_SLEEP_RETENTION && SOC_PAU_SUPPORTED
-#if SOC_LIGHT_SLEEP_SUPPORTED && !CI_TEST_SW_RETENTION
-#if SOC_PHY_SUPPORTED
-#define GDMA_RETENTION_ENTRY    (ENTRY(0) | ENTRY(2))
-#else
-#define GDMA_RETENTION_ENTRY    (ENTRY(0))
-#endif
-#else // !SOC_LIGHT_SLEEP_SUPPORTED || CI_TEST_SW_RETENTION
-#define GDMA_RETENTION_ENTRY    REGDMA_SW_TRIGGER_ENTRY
-#endif
-
+#if SOC_GDMA_SUPPORT_SLEEP_RETENTION && SOC_LIGHT_SLEEP_SUPPORTED
 typedef struct {
     const regdma_entries_config_t *link_list;
     uint32_t link_num;
     const periph_retention_module_t module_id;
 } gdma_chx_reg_ctx_link_t;
 
-extern const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[SOC_GDMA_NUM_GROUPS_MAX][SOC_GDMA_PAIRS_PER_GROUP_MAX];
+extern const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[GDMA_LL_GET(INST_NUM)][GDMA_LL_GET(PAIRS_PER_INST)];
 #endif
 
 #endif

components/esp_hw_support/CMakeLists.txt

@@ -9,7 +9,7 @@ if(${target} STREQUAL "linux")
     return()
 endif()
 
-set(requires soc)
+set(requires esp_hal_dma)
 # only esp_hw_support/adc_share_hw_ctrl.c requires efuse component
 set(priv_requires efuse spi_flash bootloader_support esp_hal_wdt)
 

components/esp_hw_support/dma/async_memcpy_cp_dma.c

@@ -292,8 +292,8 @@ static void mcp_default_isr_handler(void *args)
     bool need_yield = false;
     async_memcpy_cpdma_context_t *mcp_dma = (async_memcpy_cpdma_context_t *)args;
     // get the interrupt status and clear it
-    uint32_t status = cp_dma_hal_get_intr_status(&mcp_dma->hal);
-    cp_dma_hal_clear_intr_status(&mcp_dma->hal, status);
+    uint32_t status = cp_dma_ll_get_intr_status(mcp_dma->hal.dev);
+    cp_dma_ll_clear_intr_status(mcp_dma->hal.dev, status);
 
     // End-Of-Frame on RX side
     if (status & CP_DMA_LL_EVENT_RX_EOF) {

components/esp_hw_support/dma/async_memcpy_gdma.c

@@ -199,25 +199,25 @@ err:
     return ret;
 }
 
-#if SOC_AHB_GDMA_SUPPORTED
+#if SOC_HAS(AHB_GDMA)
 esp_err_t esp_async_memcpy_install_gdma_ahb(const async_memcpy_config_t *config, async_memcpy_handle_t *mcp)
 {
     return esp_async_memcpy_install_gdma_template(config, mcp, gdma_new_ahb_channel, SOC_GDMA_BUS_AHB);
 }
-#endif // SOC_AHB_GDMA_SUPPORTED
+#endif // SOC_HAS(AHB_GDMA)
 
-#if SOC_AXI_GDMA_SUPPORTED
+#if SOC_HAS(AXI_GDMA)
 esp_err_t esp_async_memcpy_install_gdma_axi(const async_memcpy_config_t *config, async_memcpy_handle_t *mcp)
 {
     return esp_async_memcpy_install_gdma_template(config, mcp, gdma_new_axi_channel, SOC_GDMA_BUS_AXI);
 }
-#endif // SOC_AXI_GDMA_SUPPORTED
+#endif // SOC_HAS(AXI_GDMA)
 
-#if SOC_AHB_GDMA_SUPPORTED
+#if SOC_HAS(AHB_GDMA)
 /// default installation falls back to use the AHB GDMA
 esp_err_t esp_async_memcpy_install(const async_memcpy_config_t *config, async_memcpy_handle_t *asmcp)
 __attribute__((alias("esp_async_memcpy_install_gdma_ahb")));
-#elif SOC_AXI_GDMA_SUPPORTED
+#elif SOC_HAS(AXI_GDMA)
 /// default installation falls back to use the AXI GDMA
 esp_err_t esp_async_memcpy_install(const async_memcpy_config_t *config, async_memcpy_handle_t *asmcp)
 __attribute__((alias("esp_async_memcpy_install_gdma_axi")));
@@ -310,22 +310,22 @@ static esp_err_t mcp_gdma_memcpy(async_memcpy_context_t *ctx, void *dst, void *s
     async_memcpy_gdma_context_t *mcp_gdma = __containerof(ctx, async_memcpy_gdma_context_t, parent);
     size_t dma_link_item_alignment = 4;
     // buffer location check
-#if SOC_AHB_GDMA_SUPPORTED
+#if SOC_HAS(AHB_GDMA)
     if (mcp_gdma->gdma_bus_id == SOC_GDMA_BUS_AHB) {
-#if !SOC_AHB_GDMA_SUPPORT_PSRAM
+#if !GDMA_LL_GET(AHB_PSRAM_CAPABLE)
         ESP_RETURN_ON_FALSE(esp_ptr_internal(src) && esp_ptr_internal(dst), ESP_ERR_INVALID_ARG, TAG, "AHB GDMA can only access SRAM");
-#endif // !SOC_AHB_GDMA_SUPPORT_PSRAM
+#endif // !GDMA_LL_GET(AHB_PSRAM_CAPABLE)
         dma_link_item_alignment = GDMA_LL_AHB_DESC_ALIGNMENT;
     }
-#endif // SOC_AHB_GDMA_SUPPORTED
-#if SOC_AXI_GDMA_SUPPORTED
+#endif // SOC_HAS(AHB_GDMA)
+#if SOC_HAS(AXI_GDMA)
     if (mcp_gdma->gdma_bus_id == SOC_GDMA_BUS_AXI) {
-#if !SOC_AXI_GDMA_SUPPORT_PSRAM
+#if !GDMA_LL_GET(AXI_PSRAM_CAPABLE)
         ESP_RETURN_ON_FALSE(esp_ptr_internal(src) && esp_ptr_internal(dst), ESP_ERR_INVALID_ARG, TAG, "AXI GDMA can only access SRAM");
-#endif // !SOC_AXI_GDMA_SUPPORT_PSRAM
+#endif // !GDMA_LL_GET(AXI_PSRAM_CAPABLE)
         dma_link_item_alignment = GDMA_LL_AXI_DESC_ALIGNMENT;
     }
-#endif // SOC_AXI_GDMA_SUPPORTED
+#endif // SOC_HAS(AXI_GDMA)
     // alignment check
     ESP_RETURN_ON_FALSE(check_buffer_alignment(mcp_gdma, src, dst, n), ESP_ERR_INVALID_ARG, TAG, "address|size not aligned: %p -> %p, sz=%zu", src, dst, n);
 

components/esp_hw_support/dma/dma2d.c

@@ -23,7 +23,8 @@
 #include "hal/dma2d_hal.h"
 #include "hal/dma2d_ll.h"
 #include "soc/dma2d_channel.h"
-#include "soc/dma2d_periph.h"
+#include "hal/dma2d_periph.h"
+#include "soc/soc_caps.h"
 #include "esp_bit_defs.h"
 
 /**
@@ -42,9 +43,9 @@
 ESP_LOG_ATTR_TAG(TAG, "dma2d");
 
 typedef struct dma2d_platform_t {
-    _lock_t mutex;                                      // platform level mutex lock to protect the dma2d_acquire_pool/dma2d_release_pool process
-    dma2d_group_t *groups[SOC_DMA2D_ATTR(INST_NUM)];    // array of 2D-DMA group instances
-    int group_ref_counts[SOC_DMA2D_ATTR(INST_NUM)];     // reference count used to protect group install/uninstall
+    _lock_t mutex;                                 // platform level mutex lock to protect the dma2d_acquire_pool/dma2d_release_pool process
+    dma2d_group_t *groups[DMA2D_LL_GET(INST_NUM)]; // array of 2D-DMA group instances
+    int group_ref_counts[DMA2D_LL_GET(INST_NUM)];  // reference count used to protect group install/uninstall
 } dma2d_platform_t;
 
 // 2D-DMA driver platform
@@ -53,8 +54,8 @@ static dma2d_platform_t s_platform = {
 };
 
 // extern 2D-DMA channel reserved mask variables to be ORed in the constructors
-uint32_t dma2d_tx_channel_reserved_mask[SOC_DMA2D_ATTR(INST_NUM)] = { [0 ... SOC_DMA2D_ATTR(INST_NUM) - 1] = 0 };
-uint32_t dma2d_rx_channel_reserved_mask[SOC_DMA2D_ATTR(INST_NUM)] = { [0 ... SOC_DMA2D_ATTR(INST_NUM) - 1] = 0 };
+uint32_t dma2d_tx_channel_reserved_mask[DMA2D_LL_GET(INST_NUM)] = { [0 ... DMA2D_LL_GET(INST_NUM) - 1] = 0 };
+uint32_t dma2d_rx_channel_reserved_mask[DMA2D_LL_GET(INST_NUM)] = { [0 ... DMA2D_LL_GET(INST_NUM) - 1] = 0 };
 
 // The most number of channels required for a 2D-DMA transaction (a PPA Blend operation requires 2 TX + 1 RX)
 #define DMA2D_MAX_CHANNEL_NUM_PER_TRANSACTION   3
@@ -354,7 +355,7 @@ esp_err_t dma2d_acquire_pool(const dma2d_pool_config_t *config, dma2d_pool_handl
 {
     esp_err_t ret = ESP_OK;
     ESP_RETURN_ON_FALSE(config && ret_pool, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
-    ESP_RETURN_ON_FALSE(config->pool_id < SOC_DMA2D_ATTR(INST_NUM), ESP_ERR_INVALID_ARG, TAG, "invalid pool_id");
+    ESP_RETURN_ON_FALSE(config->pool_id < DMA2D_LL_GET(INST_NUM), ESP_ERR_INVALID_ARG, TAG, "invalid pool_id");
     if (config->intr_priority) {
         ESP_RETURN_ON_FALSE(1 << (config->intr_priority) & ESP_INTR_FLAG_LOWMED, ESP_ERR_INVALID_ARG, TAG,
                             "invalid interrupt priority: %" PRIu32, config->intr_priority);
@@ -365,20 +366,20 @@ esp_err_t dma2d_acquire_pool(const dma2d_pool_config_t *config, dma2d_pool_handl
     _lock_acquire(&s_platform.mutex);
     if (!s_platform.groups[group_id]) {
         dma2d_group_t *pre_alloc_group = heap_caps_calloc(1, sizeof(dma2d_group_t), DMA2D_MEM_ALLOC_CAPS);
-        dma2d_tx_channel_t *pre_alloc_tx_channels = heap_caps_calloc(DMA2D_LL_TX_CHANNELS_PER_GROUP, sizeof(dma2d_tx_channel_t), DMA2D_MEM_ALLOC_CAPS);
-        dma2d_rx_channel_t *pre_alloc_rx_channels = heap_caps_calloc(DMA2D_LL_RX_CHANNELS_PER_GROUP, sizeof(dma2d_rx_channel_t), DMA2D_MEM_ALLOC_CAPS);
+        dma2d_tx_channel_t *pre_alloc_tx_channels = heap_caps_calloc(DMA2D_LL_GET(TX_CHANS_PER_INST), sizeof(dma2d_tx_channel_t), DMA2D_MEM_ALLOC_CAPS);
+        dma2d_rx_channel_t *pre_alloc_rx_channels = heap_caps_calloc(DMA2D_LL_GET(RX_CHANS_PER_INST), sizeof(dma2d_rx_channel_t), DMA2D_MEM_ALLOC_CAPS);
         if (pre_alloc_group && pre_alloc_tx_channels && pre_alloc_rx_channels) {
             pre_alloc_group->group_id = group_id;
             pre_alloc_group->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED;
             TAILQ_INIT(&pre_alloc_group->pending_trans_tailq);
-            pre_alloc_group->tx_channel_free_mask = (1 << DMA2D_LL_TX_CHANNELS_PER_GROUP) - 1;
-            pre_alloc_group->rx_channel_free_mask = (1 << DMA2D_LL_RX_CHANNELS_PER_GROUP) - 1;
+            pre_alloc_group->tx_channel_free_mask = (1 << DMA2D_LL_GET(TX_CHANS_PER_INST)) - 1;
+            pre_alloc_group->rx_channel_free_mask = (1 << DMA2D_LL_GET(RX_CHANS_PER_INST)) - 1;
             pre_alloc_group->tx_channel_reserved_mask = dma2d_tx_channel_reserved_mask[group_id];
             pre_alloc_group->rx_channel_reserved_mask = dma2d_rx_channel_reserved_mask[group_id];
             pre_alloc_group->tx_periph_m2m_free_id_mask = DMA2D_LL_TX_CHANNEL_PERIPH_M2M_AVAILABLE_ID_MASK;
             pre_alloc_group->rx_periph_m2m_free_id_mask = DMA2D_LL_RX_CHANNEL_PERIPH_M2M_AVAILABLE_ID_MASK;
             pre_alloc_group->intr_priority = -1;
-            for (int i = 0; i < DMA2D_LL_TX_CHANNELS_PER_GROUP; i++) {
+            for (int i = 0; i < DMA2D_LL_GET(TX_CHANS_PER_INST); i++) {
                 pre_alloc_group->tx_chans[i] = &pre_alloc_tx_channels[i];
                 dma2d_tx_channel_t *tx_chan = pre_alloc_group->tx_chans[i];
                 tx_chan->base.group = pre_alloc_group;
@@ -386,7 +387,7 @@ esp_err_t dma2d_acquire_pool(const dma2d_pool_config_t *config, dma2d_pool_handl
                 tx_chan->base.direction = DMA2D_CHANNEL_DIRECTION_TX;
                 tx_chan->base.spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED;
             }
-            for (int i = 0; i < DMA2D_LL_RX_CHANNELS_PER_GROUP; i++) {
+            for (int i = 0; i < DMA2D_LL_GET(RX_CHANS_PER_INST); i++) {
                 pre_alloc_group->rx_chans[i] = &pre_alloc_rx_channels[i];
                 dma2d_rx_channel_t *rx_chan = pre_alloc_group->rx_chans[i];
                 rx_chan->base.group = pre_alloc_group;
@@ -435,7 +436,7 @@ esp_err_t dma2d_acquire_pool(const dma2d_pool_config_t *config, dma2d_pool_handl
 
     // Allocate TX and RX interrupts
     if (s_platform.groups[group_id]) {
-        for (int i = 0; i < DMA2D_LL_RX_CHANNELS_PER_GROUP; i++) {
+        for (int i = 0; i < DMA2D_LL_GET(RX_CHANS_PER_INST); i++) {
             dma2d_rx_channel_t *rx_chan = s_platform.groups[group_id]->rx_chans[i];
             if (rx_chan->base.intr == NULL) {
                 ret = esp_intr_alloc_intrstatus(dma2d_periph_signals.groups[group_id].rx_irq_id[i],
@@ -450,7 +451,7 @@ esp_err_t dma2d_acquire_pool(const dma2d_pool_config_t *config, dma2d_pool_handl
             }
         }
 
-        for (int i = 0; i < DMA2D_LL_TX_CHANNELS_PER_GROUP; i++) {
+        for (int i = 0; i < DMA2D_LL_GET(TX_CHANS_PER_INST); i++) {
             dma2d_tx_channel_t *tx_chan = s_platform.groups[group_id]->tx_chans[i];
             if (tx_chan->base.intr == NULL) {
                 ret = esp_intr_alloc_intrstatus(dma2d_periph_signals.groups[group_id].tx_irq_id[i],
@@ -510,12 +511,12 @@ esp_err_t dma2d_release_pool(dma2d_pool_handle_t dma2d_pool)
     }
 
     if (do_deinitialize) {
-        for (int i = 0; i < DMA2D_LL_RX_CHANNELS_PER_GROUP; i++) {
+        for (int i = 0; i < DMA2D_LL_GET(RX_CHANS_PER_INST); i++) {
             if (dma2d_group->rx_chans[i]->base.intr) {
                 esp_intr_free(dma2d_group->rx_chans[i]->base.intr);
             }
         }
-        for (int i = 0; i < DMA2D_LL_TX_CHANNELS_PER_GROUP; i++) {
+        for (int i = 0; i < DMA2D_LL_GET(TX_CHANS_PER_INST); i++) {
             if (dma2d_group->tx_chans[i]->base.intr) {
                 esp_intr_free(dma2d_group->tx_chans[i]->base.intr);
             }
@@ -983,7 +984,7 @@ esp_err_t dma2d_force_end(dma2d_trans_t *trans, bool *need_yield)
     // Stop the RX channel and its bundled TX channels first
     dma2d_stop(&rx_chan->base);
     uint32_t tx_chans = rx_chan->bundled_tx_channel_mask;
-    for (int i = 0; i < DMA2D_LL_TX_CHANNELS_PER_GROUP; i++) {
+    for (int i = 0; i < DMA2D_LL_GET(TX_CHANS_PER_INST); i++) {
         if (tx_chans & (1 << i)) {
             dma2d_stop(&group->tx_chans[i]->base);
         }

components/esp_hw_support/dma/dma2d_priv.h

@@ -57,8 +57,8 @@ struct dma2d_group_t {
     uint8_t rx_channel_reserved_mask;                               // Bit mask indicating the being reserved RX channels
     uint32_t tx_periph_m2m_free_id_mask;                            // Bit mask indicating the available TX M2M peripheral selelction IDs at the moment
     uint32_t rx_periph_m2m_free_id_mask;                            // Bit mask indicating the available RX M2M peripheral selelction IDs at the moment
-    dma2d_tx_channel_t *tx_chans[DMA2D_LL_TX_CHANNELS_PER_GROUP];  // Handles of 2D-DMA TX channels
-    dma2d_rx_channel_t *rx_chans[DMA2D_LL_RX_CHANNELS_PER_GROUP];  // Handles of 2D-DMA RX channels
+    dma2d_tx_channel_t *tx_chans[DMA2D_LL_GET(TX_CHANS_PER_INST)];  // Handles of 2D-DMA TX channels
+    dma2d_rx_channel_t *rx_chans[DMA2D_LL_GET(RX_CHANS_PER_INST)];  // Handles of 2D-DMA RX channels
     int intr_priority;                                              // All channels in the same group should share the same interrupt priority
 };
 

components/esp_hw_support/dma/gdma.c

@@ -48,8 +48,8 @@
 
 typedef struct gdma_platform_t {
     portMUX_TYPE spinlock;                         // platform level spinlock, protect the group handle slots and reference count of each group.
-    gdma_group_t *groups[SOC_GDMA_NUM_GROUPS_MAX]; // array of GDMA group instances
-    int group_ref_counts[SOC_GDMA_NUM_GROUPS_MAX]; // reference count used to protect group install/uninstall
+    gdma_group_t *groups[GDMA_LL_GET(INST_NUM)]; // array of GDMA group instances
+    int group_ref_counts[GDMA_LL_GET(INST_NUM)]; // reference count used to protect group install/uninstall
 } gdma_platform_t;
 
 static gdma_group_t *gdma_acquire_group_handle(int group_id, void (*hal_init)(gdma_hal_context_t *hal, const gdma_hal_config_t *config));
@@ -191,7 +191,7 @@ err:
     return ret;
 }
 
-#if SOC_AHB_GDMA_SUPPORTED
+#if SOC_HAS(AHB_GDMA)
 esp_err_t gdma_new_ahb_channel(const gdma_channel_alloc_config_t *config, gdma_channel_handle_t *ret_chan)
 {
     gdma_channel_search_info_t search_info = {
@@ -203,9 +203,9 @@ esp_err_t gdma_new_ahb_channel(const gdma_channel_alloc_config_t *config, gdma_c
     };
     return do_allocate_gdma_channel(&search_info, config, ret_chan);
 }
-#endif // SOC_AHB_GDMA_SUPPORTED
+#endif // SOC_HAS(AHB_GDMA)
 
-#if SOC_AXI_GDMA_SUPPORTED
+#if SOC_HAS(AXI_GDMA)
 esp_err_t gdma_new_axi_channel(const gdma_channel_alloc_config_t *config, gdma_channel_handle_t *ret_chan)
 {
     gdma_channel_search_info_t search_info = {
@@ -217,12 +217,12 @@ esp_err_t gdma_new_axi_channel(const gdma_channel_alloc_config_t *config, gdma_c
     };
     return do_allocate_gdma_channel(&search_info, config, ret_chan);
 }
-#endif // SOC_AXI_GDMA_SUPPORTED
+#endif // SOC_HAS(AXI_GDMA)
 
-#if SOC_AHB_GDMA_SUPPORTED
+#if SOC_HAS(AHB_GDMA)
 esp_err_t gdma_new_channel(const gdma_channel_alloc_config_t *config, gdma_channel_handle_t *ret_chan)
 __attribute__((alias("gdma_new_ahb_channel")));
-#elif SOC_AXI_GDMA_SUPPORTED
+#elif SOC_HAS(AXI_GDMA)
 esp_err_t gdma_new_channel(const gdma_channel_alloc_config_t *config, gdma_channel_handle_t *ret_chan)
 __attribute__((alias("gdma_new_axi_channel")));
 #endif
@@ -353,7 +353,7 @@ esp_err_t gdma_config_transfer(gdma_channel_handle_t dma_chan, const gdma_transf
         // burst size must be power of 2
         ESP_RETURN_ON_FALSE((max_data_burst_size & (max_data_burst_size - 1)) == 0, ESP_ERR_INVALID_ARG,
                             TAG, "invalid max_data_burst_size: %"PRIu32, max_data_burst_size);
-#if SOC_AHB_GDMA_SUPPORT_PSRAM || SOC_AXI_GDMA_SUPPORT_PSRAM
+#if GDMA_LL_GET(AHB_PSRAM_CAPABLE) || GDMA_LL_GET(AXI_PSRAM_CAPABLE)
         if (config->access_ext_mem) {
             ESP_RETURN_ON_FALSE(max_data_burst_size <= GDMA_LL_MAX_BURST_SIZE_PSRAM, ESP_ERR_INVALID_ARG,
                                 TAG, "max_data_burst_size must not exceed %d when accessing external memory", GDMA_LL_MAX_BURST_SIZE_PSRAM);

components/esp_hw_support/dma/gdma_crc.c

@@ -15,16 +15,16 @@ esp_err_t gdma_config_crc_calculator(gdma_channel_handle_t dma_chan, const gdma_
     gdma_group_t *group = pair->group;
     gdma_hal_context_t *hal = &group->hal;
     switch (group->bus_id) {
-#if SOC_AHB_GDMA_SUPPORTED
+#if SOC_HAS(AHB_GDMA)
     case SOC_GDMA_BUS_AHB:
         ESP_RETURN_ON_FALSE(config->crc_bit_width <= GDMA_LL_AHB_MAX_CRC_BIT_WIDTH, ESP_ERR_INVALID_ARG, TAG, "invalid crc bit width");
         break;
-#endif // SOC_AHB_GDMA_SUPPORTED
-#if SOC_AXI_GDMA_SUPPORTED
+#endif // SOC_HAS(AHB_GDMA)
+#if SOC_HAS(AXI_GDMA)
     case SOC_GDMA_BUS_AXI:
         ESP_RETURN_ON_FALSE(config->crc_bit_width <= GDMA_LL_AXI_MAX_CRC_BIT_WIDTH, ESP_ERR_INVALID_ARG, TAG, "invalid crc bit width");
         break;
-#endif // SOC_AXI_GDMA_SUPPORTED
+#endif // SOC_HAS(AXI_GDMA)
     default:
         ESP_LOGE(TAG, "invalid bus id: %d", group->bus_id);
         return ESP_ERR_INVALID_ARG;

components/esp_hw_support/dma/gdma_priv.h

@@ -29,7 +29,7 @@
 #include "hal/gdma_ll.h"
 #include "hal/gdma_hal_ahb.h"
 #include "hal/gdma_hal_axi.h"
-#include "soc/gdma_periph.h"
+#include "hal/gdma_periph.h"
 #include "soc/periph_defs.h"
 #include "esp_private/gdma.h"
 #include "esp_private/periph_ctrl.h"
@@ -58,8 +58,8 @@ typedef struct gdma_group_t {
     portMUX_TYPE spinlock;  // group level spinlock, protect group level stuffs, e.g. hal object, pair handle slots and reference count of each pair
     uint32_t tx_periph_in_use_mask; // each bit indicates which peripheral (TX direction) has been occupied
     uint32_t rx_periph_in_use_mask; // each bit indicates which peripheral (RX direction) has been occupied
-    gdma_pair_t *pairs[SOC_GDMA_PAIRS_PER_GROUP_MAX];  // handles of GDMA pairs
-    int pair_ref_counts[SOC_GDMA_PAIRS_PER_GROUP_MAX]; // reference count used to protect pair install/uninstall
+    gdma_pair_t *pairs[GDMA_LL_GET(PAIRS_PER_INST)];  // handles of GDMA pairs
+    int pair_ref_counts[GDMA_LL_GET(PAIRS_PER_INST)]; // reference count used to protect pair install/uninstall
 } gdma_group_t;
 
 struct gdma_pair_t {

components/esp_hw_support/dma/linker.lf

@@ -13,7 +13,7 @@ entries:
         gdma: gdma_reset (noflash)
 
 [mapping:gdma_hal]
-archive: libhal.a
+archive: libesp_hal_dma.a
 entries:
     # performance optimization, always put the DMA default interrupt handler in IRAM
     if SOC_GDMA_SUPPORTED = y:
@@ -116,7 +116,7 @@ entries:
         dma2d: dma2d_enqueue (noflash)
 
 [mapping:dma2d_hal]
-archive: libhal.a
+archive: libesp_hal_dma.a
 entries:
     if DMA2D_ISR_IRAM_SAFE = y || DMA2D_OPERATION_FUNC_IN_IRAM = y:
         dma2d_hal: dma2d_hal_tx_reset_channel (noflash)

components/esp_hw_support/include/esp_async_memcpy.h

@@ -66,7 +66,7 @@ typedef struct {
         .flags = 0,                   \
     }
 
-#if SOC_AHB_GDMA_SUPPORTED
+#if SOC_HAS(AHB_GDMA)
 /**
  * @brief Install async memcpy driver, with AHB-GDMA as the backend
  *
@@ -79,9 +79,9 @@ typedef struct {
  *      - ESP_FAIL: Install async memcpy driver failed because of other error
  */
 esp_err_t esp_async_memcpy_install_gdma_ahb(const async_memcpy_config_t *config, async_memcpy_handle_t *mcp);
-#endif // SOC_AHB_GDMA_SUPPORTED
+#endif // SOC_HAS(AHB_GDMA)
 
-#if SOC_AXI_GDMA_SUPPORTED
+#if SOC_HAS(AXI_GDMA)
 /**
  * @brief Install async memcpy driver, with AXI-GDMA as the backend
  *
@@ -94,7 +94,7 @@ esp_err_t esp_async_memcpy_install_gdma_ahb(const async_memcpy_config_t *config,
  *      - ESP_FAIL: Install async memcpy driver failed because of other error
  */
 esp_err_t esp_async_memcpy_install_gdma_axi(const async_memcpy_config_t *config, async_memcpy_handle_t *mcp);
-#endif // SOC_AXI_GDMA_SUPPORTED
+#endif // SOC_HAS(AXI_GDMA)
 
 #if SOC_CP_DMA_SUPPORTED
 /**

components/esp_hw_support/sleep_system_peripheral.c

@@ -16,7 +16,7 @@
 #include "esp_sleep.h"
 #include "esp_log.h"
 #include "esp_check.h"
-
+#include "hal/gdma_periph.h"
 #include "esp_private/startup_internal.h"
 #include "esp_private/sleep_retention.h"
 
@@ -221,20 +221,20 @@ bool peripheral_domain_pd_allowed(void)
 # if SOC_GDMA_SUPPORTED && !CONFIG_IDF_TARGET_ESP32P4 // TODO: IDF-11371
     mask.bitmap[SLEEP_RETENTION_MODULE_GDMA_CH0 >> 5] |= BIT(SLEEP_RETENTION_MODULE_GDMA_CH0 % 32);
     mask.bitmap[SLEEP_RETENTION_MODULE_GDMA_CH1 >> 5] |= BIT(SLEEP_RETENTION_MODULE_GDMA_CH1 % 32);
-#  if (SOC_GDMA_PAIRS_PER_GROUP_MAX > 2)
+#  if (GDMA_LL_GET(PAIRS_PER_INST) > 2)
     mask.bitmap[SLEEP_RETENTION_MODULE_GDMA_CH2 >> 5] |= BIT(SLEEP_RETENTION_MODULE_GDMA_CH2 % 32);
 #  endif
 # endif /* SOC_GDMA_SUPPORTED */
-# if SOC_AHB_GDMA_SUPPORTED && CONFIG_IDF_TARGET_ESP32P4 // TODO: IDF-11372
+# if SOC_HAS(AHB_GDMA) && CONFIG_IDF_TARGET_ESP32P4 // TODO: IDF-11372
     mask.bitmap[SLEEP_RETENTION_MODULE_AHB_DMA_CH0 >> 5] |= BIT(SLEEP_RETENTION_MODULE_AHB_DMA_CH0 % 32);
     mask.bitmap[SLEEP_RETENTION_MODULE_AHB_DMA_CH1 >> 5] |= BIT(SLEEP_RETENTION_MODULE_AHB_DMA_CH1 % 32);
     mask.bitmap[SLEEP_RETENTION_MODULE_AHB_DMA_CH2 >> 5] |= BIT(SLEEP_RETENTION_MODULE_AHB_DMA_CH2 % 32);
-# endif /* SOC_AHB_GDMA_SUPPORTED */
-# if SOC_AXI_GDMA_SUPPORTED
+# endif /* SOC_HAS(AHB_GDMA) */
+# if SOC_HAS(AXI_GDMA)
     mask.bitmap[SLEEP_RETENTION_MODULE_AXI_DMA_CH0 >> 5] |= BIT(SLEEP_RETENTION_MODULE_AXI_DMA_CH0 % 32);
     mask.bitmap[SLEEP_RETENTION_MODULE_AXI_DMA_CH1 >> 5] |= BIT(SLEEP_RETENTION_MODULE_AXI_DMA_CH1 % 32);
     mask.bitmap[SLEEP_RETENTION_MODULE_AXI_DMA_CH2 >> 5] |= BIT(SLEEP_RETENTION_MODULE_AXI_DMA_CH2 % 32);
-# endif /* SOC_AXI_GDMA_SUPPORTED */
+# endif /* SOC_HAS(AXI_GDMA) */
 #endif /* SOC_GDMA_SUPPORT_SLEEP_RETENTION */
 
 #if SOC_HAS(PAU)

components/esp_hw_support/test_apps/.build-test-rules.yml

@@ -7,12 +7,16 @@ components/esp_hw_support/test_apps/dma:
       reason: No general DMA controller on ESP32
   depends_filepatterns:
     - components/esp_hw_support/dma/**/*
+  depends_components:
+    - esp_hal_dma
 
 components/esp_hw_support/test_apps/dma2d:
   disable:
     - if: SOC_DMA2D_SUPPORTED != 1
   depends_filepatterns:
     - components/esp_hw_support/dma/**/*
+  depends_components:
+    - esp_hal_dma
 
 components/esp_hw_support/test_apps/host_test_linux:
   enable:

components/esp_hw_support/test_apps/dma/main/CMakeLists.txt

@@ -26,6 +26,6 @@ idf_component_register(SRCS ${srcs}
                        PRIV_REQUIRES unity esp_mm esp_driver_gpio
                        WHOLE_ARCHIVE)
 
-idf_component_get_property(lib_name soc COMPONENT_LIB)
+idf_component_get_property(lib_name esp_hal_dma COMPONENT_LIB)
 # Test GDMA retention correctness with software retention feature
 target_compile_definitions(${lib_name} PRIVATE "CI_TEST_SW_RETENTION=1")

components/esp_hw_support/test_apps/dma/main/test_async_memcpy.c

@@ -119,19 +119,19 @@ TEST_CASE("memory copy the same buffer with different content", "[async mcp]")
     async_memcpy_config_t config = ASYNC_MEMCPY_DEFAULT_CONFIG();
     async_memcpy_handle_t driver = NULL;
 
-#if SOC_AHB_GDMA_SUPPORTED
+#if SOC_HAS(AHB_GDMA)
     printf("Testing memcpy by AHB GDMA\r\n");
     TEST_ESP_OK(esp_async_memcpy_install_gdma_ahb(&config, &driver));
     test_memory_copy_with_same_buffer(driver, &config);
     TEST_ESP_OK(esp_async_memcpy_uninstall(driver));
-#endif // SOC_AHB_GDMA_SUPPORTED
+#endif // SOC_HAS(AHB_GDMA)
 
-#if SOC_AXI_GDMA_SUPPORTED
+#if SOC_HAS(AXI_GDMA)
     printf("Testing memcpy by AXI GDMA\r\n");
     TEST_ESP_OK(esp_async_memcpy_install_gdma_axi(&config, &driver));
     test_memory_copy_with_same_buffer(driver, &config);
     TEST_ESP_OK(esp_async_memcpy_uninstall(driver));
-#endif // SOC_AXI_GDMA_SUPPORTED
+#endif // SOC_HAS(AXI_GDMA)
 
 #if SOC_CP_DMA_SUPPORTED
     printf("Testing memcpy by CP DMA\r\n");
@@ -182,19 +182,19 @@ TEST_CASE("memory copy by DMA (blocking)", "[async mcp]")
     };
     async_memcpy_handle_t driver = NULL;
 
-#if SOC_AHB_GDMA_SUPPORTED
+#if SOC_HAS(AHB_GDMA)
     printf("Testing memcpy by AHB GDMA\r\n");
     TEST_ESP_OK(esp_async_memcpy_install_gdma_ahb(&config, &driver));
     test_memory_copy_blocking(driver);
     TEST_ESP_OK(esp_async_memcpy_uninstall(driver));
-#endif // SOC_AHB_GDMA_SUPPORTED
+#endif // SOC_HAS(AHB_GDMA)
 
-#if SOC_AXI_GDMA_SUPPORTED
+#if SOC_HAS(AXI_GDMA)
     printf("Testing memcpy by AXI GDMA\r\n");
     TEST_ESP_OK(esp_async_memcpy_install_gdma_axi(&config, &driver));
     test_memory_copy_blocking(driver);
     TEST_ESP_OK(esp_async_memcpy_uninstall(driver));
-#endif // SOC_AXI_GDMA_SUPPORTED
+#endif // SOC_HAS(AXI_GDMA)
 
 #if SOC_CP_DMA_SUPPORTED
     printf("Testing memcpy by CP DMA\r\n");
@@ -247,25 +247,25 @@ TEST_CASE("memory copy with dest address unaligned", "[async mcp]")
     TEST_ESP_OK(esp_async_memcpy_uninstall(driver));
 #endif // SOC_CP_DMA_SUPPORTED
 
-#if SOC_AHB_GDMA_SUPPORTED && !GDMA_LL_AHB_RX_BURST_NEEDS_ALIGNMENT && !CONFIG_GDMA_ENABLE_WEIGHTED_ARBITRATION
+#if SOC_HAS(AHB_GDMA) && !GDMA_LL_AHB_RX_BURST_NEEDS_ALIGNMENT && !CONFIG_GDMA_ENABLE_WEIGHTED_ARBITRATION
     printf("Testing memcpy by AHB GDMA\r\n");
     TEST_ESP_OK(esp_async_memcpy_install_gdma_ahb(&driver_config, &driver));
     test_memcpy_with_dest_addr_unaligned(driver, false, false);
-#if SOC_AHB_GDMA_SUPPORT_PSRAM && SOC_SPIRAM_SUPPORTED
+#if GDMA_LL_GET(AHB_PSRAM_CAPABLE)
     test_memcpy_with_dest_addr_unaligned(driver, true, true);
-#endif // SOC_AHB_GDMA_SUPPORT_PSRAM && SOC_SPIRAM_SUPPORTED
+#endif // GDMA_LL_GET(AHB_PSRAM_CAPABLE)
     TEST_ESP_OK(esp_async_memcpy_uninstall(driver));
-#endif // SOC_AHB_GDMA_SUPPORTED
+#endif // SOC_HAS(AHB_GDMA)
 
-#if SOC_AXI_GDMA_SUPPORTED && !CONFIG_GDMA_ENABLE_WEIGHTED_ARBITRATION
+#if SOC_HAS(AXI_GDMA) && !CONFIG_GDMA_ENABLE_WEIGHTED_ARBITRATION
     printf("Testing memcpy by AXI GDMA\r\n");
     TEST_ESP_OK(esp_async_memcpy_install_gdma_axi(&driver_config, &driver));
     test_memcpy_with_dest_addr_unaligned(driver, false, false);
-#if SOC_AXI_GDMA_SUPPORT_PSRAM && SOC_SPIRAM_SUPPORTED
+#if GDMA_LL_GET(AXI_PSRAM_CAPABLE)
     test_memcpy_with_dest_addr_unaligned(driver, true, true);
-#endif // SOC_AXI_GDMA_SUPPORT_PSRAM && SOC_SPIRAM_SUPPORTED
+#endif // GDMA_LL_GET(AXI_PSRAM_CAPABLE)
     TEST_ESP_OK(esp_async_memcpy_uninstall(driver));
-#endif // SOC_AXI_GDMA_SUPPORTED
+#endif // SOC_HAS(AXI_GDMA)
 }
 
 #define TEST_ASYNC_MEMCPY_BENCH_COUNTS 16
@@ -335,19 +335,19 @@ TEST_CASE("memory copy performance 40KB: SRAM->SRAM", "[async mcp]")
     };
     async_memcpy_handle_t driver = NULL;
 
-#if SOC_AHB_GDMA_SUPPORTED
+#if SOC_HAS(AHB_GDMA)
     printf("Testing memcpy by AHB GDMA\r\n");
     TEST_ESP_OK(esp_async_memcpy_install_gdma_ahb(&driver_config, &driver));
     test_memcpy_performance(driver, 40 * 1024, false, false);
     TEST_ESP_OK(esp_async_memcpy_uninstall(driver));
-#endif // SOC_AHB_GDMA_SUPPORTED
+#endif // SOC_HAS(AHB_GDMA)
 
-#if SOC_AXI_GDMA_SUPPORTED
+#if SOC_HAS(AXI_GDMA)
     printf("Testing memcpy by AXI GDMA\r\n");
     TEST_ESP_OK(esp_async_memcpy_install_gdma_axi(&driver_config, &driver));
     test_memcpy_performance(driver, 40 * 1024, false, false);
     TEST_ESP_OK(esp_async_memcpy_uninstall(driver));
-#endif // SOC_AXI_GDMA_SUPPORTED
+#endif // SOC_HAS(AXI_GDMA)
 
 #if SOC_CP_DMA_SUPPORTED
     printf("Testing memcpy by CP DMA\r\n");
@@ -366,19 +366,23 @@ TEST_CASE("memory copy performance 40KB: PSRAM->PSRAM", "[async mcp]")
     };
     [[maybe_unused]] async_memcpy_handle_t driver = NULL;
 
-#if SOC_AHB_GDMA_SUPPORTED && SOC_AHB_GDMA_SUPPORT_PSRAM
+#if SOC_HAS(AHB_GDMA)
+#if GDMA_LL_GET(AHB_PSRAM_CAPABLE)
     printf("Testing memcpy by AHB GDMA\r\n");
     TEST_ESP_OK(esp_async_memcpy_install_gdma_ahb(&driver_config, &driver));
     test_memcpy_performance(driver, 40 * 1024, true, true);
     TEST_ESP_OK(esp_async_memcpy_uninstall(driver));
-#endif // SOC_AHB_GDMA_SUPPORTED && SOC_AHB_GDMA_SUPPORT_PSRAM
+#endif
+#endif // SOC_HAS(AHB_GDMA)
 
-#if SOC_AXI_GDMA_SUPPORTED && SOC_AXI_GDMA_SUPPORT_PSRAM
+#if SOC_HAS(AXI_GDMA)
+#if GDMA_LL_GET(AXI_PSRAM_CAPABLE)
     printf("Testing memcpy by AXI GDMA\r\n");
     TEST_ESP_OK(esp_async_memcpy_install_gdma_axi(&driver_config, &driver));
     test_memcpy_performance(driver, 40 * 1024, true, true);
     TEST_ESP_OK(esp_async_memcpy_uninstall(driver));
-#endif // SOC_AXI_GDMA_SUPPORTED && SOC_AXI_GDMA_SUPPORT_PSRAM
+#endif
+#endif // SOC_HAS(AXI_GDMA)
 }
 #endif
 
@@ -461,7 +465,7 @@ TEST_CASE("GDMA M2M Weighted Arbitration Test SRAM->SRAM", "[GDMA][M2M][async mc
 
     async_memcpy_handle_t driver[2] = {NULL};
 
-#if SOC_AHB_GDMA_SUPPORTED
+#if SOC_HAS(AHB_GDMA)
     driver_config.weight = 1;
     TEST_ESP_OK(esp_async_memcpy_install_gdma_ahb(&driver_config, &driver[0]));
     driver_config.weight = 15;
@@ -469,7 +473,7 @@ TEST_CASE("GDMA M2M Weighted Arbitration Test SRAM->SRAM", "[GDMA][M2M][async mc
     memcpy_weighted_arb_test(driver, driver_config.dma_burst_size, 200 * 1024, false);
     TEST_ESP_OK(esp_async_memcpy_uninstall(driver[0]));
     TEST_ESP_OK(esp_async_memcpy_uninstall(driver[1]));
-#endif // SOC_AHB_GDMA_SUPPORTED
+#endif // SOC_HAS(AHB_GDMA)
 }
 
 #if SOC_SPIRAM_SUPPORTED
@@ -482,7 +486,8 @@ TEST_CASE("GDMA M2M Weighted Arbitration Test PSRAM->PSRAM", "[GDMA][M2M][async
 
     [[maybe_unused]] async_memcpy_handle_t driver[2] = {NULL};
 
-#if SOC_AHB_GDMA_SUPPORTED && SOC_AHB_GDMA_SUPPORT_PSRAM
+#if SOC_HAS(AHB_GDMA)
+#if GDMA_LL_GET(AHB_PSRAM_CAPABLE)
     driver_config.weight = 1;
     TEST_ESP_OK(esp_async_memcpy_install_gdma_ahb(&driver_config, &driver[0]));
     driver_config.weight = 15;
@@ -490,7 +495,8 @@ TEST_CASE("GDMA M2M Weighted Arbitration Test PSRAM->PSRAM", "[GDMA][M2M][async
     memcpy_weighted_arb_test(driver, driver_config.dma_burst_size, 200 * 1024, true);
     TEST_ESP_OK(esp_async_memcpy_uninstall(driver[0]));
     TEST_ESP_OK(esp_async_memcpy_uninstall(driver[1]));
-#endif // SOC_AHB_GDMA_SUPPORTED && SOC_AHB_GDMA_SUPPORT_PSRAM
+#endif
+#endif // SOC_HAS(AHB_GDMA)
 }
 #endif // SOC_SPIRAM_SUPPORTED
 

components/esp_hw_support/test_apps/dma/main/test_gdma.c

@@ -30,11 +30,11 @@
 TEST_CASE("GDMA channel allocation", "[GDMA]")
 {
     gdma_channel_alloc_config_t channel_config = {};
-    gdma_channel_handle_t tx_channels[SOC_GDMA_PAIRS_PER_GROUP_MAX] = {};
-    gdma_channel_handle_t rx_channels[SOC_GDMA_PAIRS_PER_GROUP_MAX] = {};
+    gdma_channel_handle_t tx_channels[GDMA_LL_GET(PAIRS_PER_INST)] = {};
+    gdma_channel_handle_t rx_channels[GDMA_LL_GET(PAIRS_PER_INST)] = {};
     channel_config.direction = GDMA_CHANNEL_DIRECTION_TX;
 
-#if SOC_AHB_GDMA_SUPPORTED
+#if SOC_HAS(AHB_GDMA)
     // install TX channels
     for (int i = 0; i < GDMA_LL_AHB_PAIRS_PER_GROUP; i++) {
         TEST_ESP_OK(gdma_new_ahb_channel(&channel_config, &tx_channels[i]));
@@ -56,7 +56,7 @@ TEST_CASE("GDMA channel allocation", "[GDMA]")
     for (int i = 0; i < GDMA_LL_AHB_PAIRS_PER_GROUP; i++) {
         TEST_ESP_OK(gdma_del_channel(rx_channels[i]));
     }
-#endif // SOC_AHB_GDMA_SUPPORTED
+#endif // SOC_HAS(AHB_GDMA)
 
     // install single and paired TX/RX channels
 #if GDMA_LL_AHB_PAIRS_PER_GROUP >= 2
@@ -102,7 +102,7 @@ TEST_CASE("GDMA channel allocation", "[GDMA]")
     }
 #endif // GDMA_LL_AHB_PAIRS_PER_GROUP >= 2
 
-#if SOC_AXI_GDMA_SUPPORTED
+#if SOC_HAS(AXI_GDMA)
     // install TX channels
     channel_config.direction = GDMA_CHANNEL_DIRECTION_TX;
     for (int i = 0; i < GDMA_LL_AXI_PAIRS_PER_GROUP; i++) {
@@ -125,7 +125,7 @@ TEST_CASE("GDMA channel allocation", "[GDMA]")
     for (int i = 0; i < GDMA_LL_AXI_PAIRS_PER_GROUP; i++) {
         TEST_ESP_OK(gdma_del_channel(rx_channels[i]));
     }
-#endif // SOC_AXI_GDMA_SUPPORTED
+#endif // SOC_HAS(AXI_GDMA)
 
     // install single and paired TX/RX channels
 #if GDMA_LL_AXI_PAIRS_PER_GROUP >= 2
@@ -347,7 +347,7 @@ static void test_gdma_m2m_mode(bool trig_retention_backup)
     gdma_channel_alloc_config_t tx_chan_alloc_config = {};
     gdma_channel_alloc_config_t rx_chan_alloc_config = {};
 
-#if SOC_AHB_GDMA_SUPPORTED
+#if SOC_HAS(AHB_GDMA)
     tx_chan_alloc_config = (gdma_channel_alloc_config_t) {
         .direction = GDMA_CHANNEL_DIRECTION_TX,
         .flags.reserve_sibling = true,
@@ -363,9 +363,9 @@ static void test_gdma_m2m_mode(bool trig_retention_backup)
 
     TEST_ESP_OK(gdma_del_channel(tx_chan));
     TEST_ESP_OK(gdma_del_channel(rx_chan));
-#endif // SOC_AHB_GDMA_SUPPORTED
+#endif // SOC_HAS(AHB_GDMA)
 
-#if SOC_AXI_GDMA_SUPPORTED
+#if SOC_HAS(AXI_GDMA)
     tx_chan_alloc_config = (gdma_channel_alloc_config_t) {
         .direction = GDMA_CHANNEL_DIRECTION_TX,
         .flags.reserve_sibling = true,
@@ -382,7 +382,7 @@ static void test_gdma_m2m_mode(bool trig_retention_backup)
 
     TEST_ESP_OK(gdma_del_channel(tx_chan));
     TEST_ESP_OK(gdma_del_channel(rx_chan));
-#endif // SOC_AXI_GDMA_SUPPORTED
+#endif // SOC_HAS(AXI_GDMA)
 }
 
 TEST_CASE("GDMA M2M Mode", "[GDMA][M2M]")
@@ -676,7 +676,8 @@ TEST_CASE("GDMA memory copy SRAM->PSRAM->SRAM", "[GDMA][M2M]")
     [[maybe_unused]] gdma_channel_alloc_config_t tx_chan_alloc_config = {};
     [[maybe_unused]] gdma_channel_alloc_config_t rx_chan_alloc_config = {};
 
-#if SOC_AHB_GDMA_SUPPORTED && SOC_AHB_GDMA_SUPPORT_PSRAM
+#if SOC_HAS(AHB_GDMA)
+#if GDMA_LL_GET(AHB_PSRAM_CAPABLE)
     printf("Testing AHB-GDMA memory copy SRAM->PSRAM->SRAM\n");
     tx_chan_alloc_config = (gdma_channel_alloc_config_t) {
         .direction = GDMA_CHANNEL_DIRECTION_TX,
@@ -694,8 +695,10 @@ TEST_CASE("GDMA memory copy SRAM->PSRAM->SRAM", "[GDMA][M2M]")
     TEST_ESP_OK(gdma_del_channel(tx_chan));
     TEST_ESP_OK(gdma_del_channel(rx_chan));
 #endif
+#endif // SOC_HAS(AHB_GDMA)
 
-#if SOC_AXI_GDMA_SUPPORTED && SOC_AXI_GDMA_SUPPORT_PSRAM
+#if SOC_HAS(AXI_GDMA)
+#if GDMA_LL_GET(AXI_PSRAM_CAPABLE)
     printf("Testing AXI-GDMA memory copy SRAM->PSRAM->SRAM\n");
     tx_chan_alloc_config = (gdma_channel_alloc_config_t) {
         .direction = GDMA_CHANNEL_DIRECTION_TX,
@@ -713,5 +716,6 @@ TEST_CASE("GDMA memory copy SRAM->PSRAM->SRAM", "[GDMA][M2M]")
     TEST_ESP_OK(gdma_del_channel(tx_chan));
     TEST_ESP_OK(gdma_del_channel(rx_chan));
 #endif
+#endif // SOC_HAS(AXI_GDMA)
 }
 #endif // SOC_SPIRAM_SUPPORTED

components/esp_hw_support/test_apps/dma/main/test_gdma_crc.c

@@ -118,17 +118,17 @@ TEST_CASE("GDMA CRC Calculation", "[GDMA][CRC]")
     gdma_channel_alloc_config_t tx_chan_alloc_config = {
         .direction = GDMA_CHANNEL_DIRECTION_TX,
     };
-#if SOC_AHB_GDMA_SUPPORTED
+#if SOC_HAS(AHB_GDMA)
     printf("Test CRC calculation for AHB GDMA\r\n");
     TEST_ESP_OK(gdma_new_ahb_channel(&tx_chan_alloc_config, &tx_chan));
     test_gdma_crc_calculation(tx_chan, 4);
     TEST_ESP_OK(gdma_del_channel(tx_chan));
-#endif // SOC_AHB_GDMA_SUPPORTED
+#endif // SOC_HAS(AHB_GDMA)
 
-#if SOC_AXI_GDMA_SUPPORTED
+#if SOC_HAS(AXI_GDMA)
     printf("Test CRC calculation for AXI GDMA\r\n");
     TEST_ESP_OK(gdma_new_axi_channel(&tx_chan_alloc_config, &tx_chan));
     test_gdma_crc_calculation(tx_chan, 3);
     TEST_ESP_OK(gdma_del_channel(tx_chan));
-#endif // SOC_AXI_GDMA_SUPPORTED
+#endif // SOC_HAS(AXI_GDMA)
 }

components/esp_mm/heap_align_hw.c

@@ -56,7 +56,7 @@ HEAP_IRAM_ATTR void esp_heap_adjust_alignment_to_hw(size_t *p_alignment, size_t
         return;
     }
 
-#if SOC_GDMA_SUPPORTED && SOC_AXI_GDMA_SUPPORTED
+#if SOC_HAS(AXI_GDMA)
     //Special case: AXI DMA descriptors need to be aligned to 8-byte boundaries.
     if ((caps & MALLOC_CAP_DMA_DESC_AXI) && (cache_alignment_bytes < GDMA_LL_AXI_DESC_ALIGNMENT)) {
         cache_alignment_bytes = GDMA_LL_AXI_DESC_ALIGNMENT;

components/esp_system/port/soc/esp32p4/system_internal.c

@@ -54,11 +54,11 @@ void esp_system_reset_modules_on_exit(void)
         }
     }
     if (dma2d_ll_is_bus_clock_enabled(0)) {
-        for (int i = 0; i < DMA2D_LL_RX_CHANNELS_PER_GROUP; i++) {
+        for (int i = 0; i < DMA2D_LL_GET(RX_CHANS_PER_INST); i++) {
             dma2d_ll_rx_abort(DMA2D_LL_GET_HW(0), i, true);
             while (!dma2d_ll_rx_is_reset_avail(DMA2D_LL_GET_HW(0), i));
         }
-        for (int i = 0; i < DMA2D_LL_TX_CHANNELS_PER_GROUP; i++) {
+        for (int i = 0; i < DMA2D_LL_GET(TX_CHANS_PER_INST); i++) {
             dma2d_ll_tx_abort(DMA2D_LL_GET_HW(0), i, true);
             while (!dma2d_ll_tx_is_reset_avail(DMA2D_LL_GET_HW(0), i));
         }

components/hal/CMakeLists.txt

@@ -116,34 +116,6 @@ elseif(NOT BOOTLOADER_BUILD)
         endif()
     endif()
 
-    if(CONFIG_SOC_GDMA_SUPPORTED)
-        list(APPEND srcs "gdma_hal_top.c")
-
-        if(CONFIG_SOC_GDMA_SUPPORT_CRC)
-            list(APPEND srcs "gdma_hal_crc_gen.c")
-        endif()
-
-        if(CONFIG_SOC_AHB_GDMA_VERSION EQUAL 1)
-            list(APPEND srcs "gdma_hal_ahb_v1.c")
-        endif()
-
-        if(CONFIG_SOC_AHB_GDMA_VERSION EQUAL 2)
-            list(APPEND srcs "gdma_hal_ahb_v2.c")
-        endif()
-
-        if(CONFIG_SOC_AXI_GDMA_SUPPORTED)
-            list(APPEND srcs "gdma_hal_axi.c")
-        endif()
-    endif()
-
-    if(CONFIG_SOC_DW_GDMA_SUPPORTED)
-        list(APPEND srcs "dw_gdma_hal.c")
-    endif()
-
-    if(CONFIG_SOC_DMA2D_SUPPORTED)
-        list(APPEND srcs "dma2d_hal.c")
-    endif()
-
     if(CONFIG_SOC_I2S_SUPPORTED)
         list(APPEND srcs "i2s_hal.c")
     endif()
@@ -299,11 +271,6 @@ elseif(NOT BOOTLOADER_BUILD)
         list(APPEND srcs "temperature_sensor_hal.c")
     endif()
 
-    if(${target} STREQUAL "esp32s2")
-        list(APPEND srcs
-                    "esp32s2/cp_dma_hal.c")
-    endif()
-
     if(EXISTS "${CMAKE_CURRENT_LIST_DIR}/${target}/rtc_cntl_hal.c")
         list(APPEND srcs "${target}/rtc_cntl_hal.c")
     endif()

components/hal/esp32s2/include/hal/cp_dma_hal.h

@@ -1,98 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/*******************************************************************************
- * NOTICE
- * The HAL is not public api, don't use in application code.
- * See readme.md in soc/README.md
- ******************************************************************************/
-
-// CP DMA HAL usages:
-// 1. Initialize HAL layer by cp_dma_hal_init, pass in the allocated descriptors for TX and RX
-// 2. Enable DMA and interrupt by cp_dma_hal_start
-// 3. Prepare descriptors used for TX and RX
-// 4. Restart the DMA engine in case it's not in working
-
-#pragma once
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stddef.h>
-#include <stdbool.h>
-#include "esp_attr.h"
-#include "hal/dma_types.h"
-#include "soc/cp_dma_struct.h"
-
-/**
- * @brief HAL context
- *
- */
-typedef struct {
-    cp_dma_dev_t *dev;
-} cp_dma_hal_context_t;
-
-typedef struct {
-} cp_dma_hal_config_t;
-
-/**
- * @brief Initialize HAL layer context
- *
- * @param hal HAL layer context, whose memroy should be allocated at driver layer
- * @param config configuration for the HAL layer
- */
-void cp_dma_hal_init(cp_dma_hal_context_t *hal, const cp_dma_hal_config_t *config);
-
-/**
- * @brief Deinitialize HAL layer context
- */
-void cp_dma_hal_deinit(cp_dma_hal_context_t *hal);
-
-/**
- * @brief Set descriptor base address
- */
-void cp_dma_hal_set_desc_base_addr(cp_dma_hal_context_t *hal, intptr_t outlink_base, intptr_t inlink_base);
-
-/**
- * @brief Start mem2mem DMA state machine
- */
-void cp_dma_hal_start(cp_dma_hal_context_t *hal);
-
-/**
- * @brief Stop mem2mem DMA state machine
- */
-void cp_dma_hal_stop(cp_dma_hal_context_t *hal);
-
-/**
- * @brief Get interrupt status word
- *
- * @return uint32_t Interrupt status
- */
-uint32_t cp_dma_hal_get_intr_status(cp_dma_hal_context_t *hal) IRAM_ATTR;
-
-/**
- * @brief Clear interrupt mask
- *
- * @param mask interrupt mask
- */
-void cp_dma_hal_clear_intr_status(cp_dma_hal_context_t *hal, uint32_t mask) IRAM_ATTR;
-
-/**@{*/
-/**
- * @brief Give the owner of descriptors between [start_desc, end_desc] to DMA, and restart DMA HW engine
- *
- * @param hal HAL layer context
- * @param start_desc The first descriptor that carries one transaction
- * @param end_desc The last descriptor that carries one transaction
- */
-void cp_dma_hal_restart_tx(cp_dma_hal_context_t *hal);
-void cp_dma_hal_restart_rx(cp_dma_hal_context_t *hal);
-/**@}*/
-
-#ifdef __cplusplus
-}
-#endif

components/hal/include/hal/adc_hal.h

@@ -15,10 +15,6 @@
 #include "hal/adc_ll.h"
 #endif
 
-#if SOC_GDMA_SUPPORTED
-#include "hal/gdma_ll.h"
-#endif
-
 #if SOC_IS(ESP32S2)
 //ADC utilises SPI3 DMA on ESP32S2
 #include "hal/spi_ll.h"

components/soc/CMakeLists.txt

@@ -88,14 +88,6 @@ if(CONFIG_SOC_ETM_SUPPORTED)
     list(APPEND srcs "${target_folder}/etm_periph.c")
 endif()
 
-if(CONFIG_SOC_GDMA_SUPPORTED)
-    list(APPEND srcs "${target_folder}/gdma_periph.c")
-endif()
-
-if(CONFIG_SOC_DMA2D_SUPPORTED)
-    list(APPEND srcs "${target_folder}/dma2d_periph.c")
-endif()
-
 if(CONFIG_SOC_GPSPI_SUPPORTED)
     list(APPEND srcs "${target_folder}/spi_periph.c")
 endif()

components/soc/esp32c2/include/soc/Kconfig.soc_caps.in

@@ -271,14 +271,6 @@ config SOC_AHB_GDMA_VERSION
     int
     default 1
 
-config SOC_GDMA_NUM_GROUPS_MAX
-    int
-    default 1
-
-config SOC_GDMA_PAIRS_PER_GROUP_MAX
-    int
-    default 1
-
 config SOC_GPIO_PORT
     int
     default 1

components/soc/esp32c2/include/soc/soc_caps.h

@@ -118,8 +118,6 @@
 
 /*-------------------------- GDMA CAPS -------------------------------------*/
 #define SOC_AHB_GDMA_VERSION            1U
-#define SOC_GDMA_NUM_GROUPS_MAX         1U
-#define SOC_GDMA_PAIRS_PER_GROUP_MAX    1U
 
 /*-------------------------- GPIO CAPS ---------------------------------------*/
 // ESP32-C2 has 1 GPIO peripheral

components/soc/esp32c3/include/soc/Kconfig.soc_caps.in

@@ -367,14 +367,6 @@ config SOC_AHB_GDMA_VERSION
     int
     default 1
 
-config SOC_GDMA_NUM_GROUPS_MAX
-    int
-    default 1
-
-config SOC_GDMA_PAIRS_PER_GROUP_MAX
-    int
-    default 3
-
 config SOC_GPIO_PORT
     int
     default 1

components/soc/esp32c3/include/soc/soc_caps.h

@@ -157,8 +157,6 @@
 
 /*-------------------------- GDMA CAPS -------------------------------------*/
 #define SOC_AHB_GDMA_VERSION            1U
-#define SOC_GDMA_NUM_GROUPS_MAX         1U
-#define SOC_GDMA_PAIRS_PER_GROUP_MAX    3
 
 /*-------------------------- GPIO CAPS ---------------------------------------*/
 // ESP32-C3 has 1 GPIO peripheral

components/soc/esp32c5/include/soc/Kconfig.soc_caps.in

@@ -499,14 +499,6 @@ config SOC_AHB_GDMA_VERSION
     int
     default 2
 
-config SOC_GDMA_NUM_GROUPS_MAX
-    int
-    default 1
-
-config SOC_GDMA_PAIRS_PER_GROUP_MAX
-    int
-    default 3
-
 config SOC_GDMA_SUPPORT_ETM
     bool
     default y
@@ -515,10 +507,6 @@ config SOC_GDMA_SUPPORT_SLEEP_RETENTION
     bool
     default y
 
-config SOC_AHB_GDMA_SUPPORT_PSRAM
-    bool
-    default y
-
 config SOC_GDMA_SUPPORT_WEIGHTED_ARBITRATION
     bool
     default y

components/soc/esp32c5/include/soc/soc_caps.h

@@ -197,11 +197,8 @@
 
 /*-------------------------- GDMA CAPS -------------------------------------*/
 #define SOC_AHB_GDMA_VERSION            2
-#define SOC_GDMA_NUM_GROUPS_MAX         1U
-#define SOC_GDMA_PAIRS_PER_GROUP_MAX    3
 #define SOC_GDMA_SUPPORT_ETM            1
 #define SOC_GDMA_SUPPORT_SLEEP_RETENTION    1
-#define SOC_AHB_GDMA_SUPPORT_PSRAM 1
 #define SOC_GDMA_SUPPORT_WEIGHTED_ARBITRATION   1
 
 /*-------------------------- GPIO CAPS ---------------------------------------*/

components/soc/esp32c6/include/soc/Kconfig.soc_caps.in

@@ -447,14 +447,6 @@ config SOC_AHB_GDMA_VERSION
     int
     default 1
 
-config SOC_GDMA_NUM_GROUPS_MAX
-    int
-    default 1
-
-config SOC_GDMA_PAIRS_PER_GROUP_MAX
-    int
-    default 3
-
 config SOC_GDMA_SUPPORT_ETM
     bool
     default y

components/soc/esp32c6/include/soc/soc_caps.h

@@ -180,8 +180,6 @@
 
 /*-------------------------- GDMA CAPS -------------------------------------*/
 #define SOC_AHB_GDMA_VERSION                1U
-#define SOC_GDMA_NUM_GROUPS_MAX             1U
-#define SOC_GDMA_PAIRS_PER_GROUP_MAX        3
 #define SOC_GDMA_SUPPORT_ETM                1  // Support ETM submodule
 #define SOC_GDMA_SUPPORT_SLEEP_RETENTION    1
 

components/soc/esp32c61/include/soc/Kconfig.soc_caps.in

@@ -379,14 +379,6 @@ config SOC_AHB_GDMA_VERSION
     int
     default 2
 
-config SOC_GDMA_NUM_GROUPS_MAX
-    int
-    default 1
-
-config SOC_GDMA_PAIRS_PER_GROUP_MAX
-    int
-    default 2
-
 config SOC_GDMA_SUPPORT_ETM
     bool
     default y
@@ -395,10 +387,6 @@ config SOC_GDMA_SUPPORT_SLEEP_RETENTION
     bool
     default y
 
-config SOC_AHB_GDMA_SUPPORT_PSRAM
-    bool
-    default y
-
 config SOC_GDMA_SUPPORT_WEIGHTED_ARBITRATION
     bool
     default y

components/soc/esp32c61/include/soc/soc_caps.h

@@ -154,11 +154,8 @@
 
 /*-------------------------- GDMA CAPS -------------------------------------*/
 #define SOC_AHB_GDMA_VERSION            2U
-#define SOC_GDMA_NUM_GROUPS_MAX         1U
-#define SOC_GDMA_PAIRS_PER_GROUP_MAX    2
 #define SOC_GDMA_SUPPORT_ETM            1  // Support ETM submodule
 #define SOC_GDMA_SUPPORT_SLEEP_RETENTION    1
-#define SOC_AHB_GDMA_SUPPORT_PSRAM 1
 #define SOC_GDMA_SUPPORT_WEIGHTED_ARBITRATION   1
 
 /*-------------------------- ETM CAPS -----------------------------------*/

components/soc/esp32h2/include/soc/Kconfig.soc_caps.in

@@ -467,14 +467,6 @@ config SOC_AHB_GDMA_VERSION
     int
     default 1
 
-config SOC_GDMA_NUM_GROUPS_MAX
-    int
-    default 1
-
-config SOC_GDMA_PAIRS_PER_GROUP_MAX
-    int
-    default 3
-
 config SOC_GDMA_SUPPORT_ETM
     bool
     default y

components/soc/esp32h2/include/soc/soc_caps.h

@@ -203,8 +203,6 @@
 
 /*-------------------------- GDMA CAPS -------------------------------------*/
 #define SOC_AHB_GDMA_VERSION                1U
-#define SOC_GDMA_NUM_GROUPS_MAX             1U
-#define SOC_GDMA_PAIRS_PER_GROUP_MAX        3
 #define SOC_GDMA_SUPPORT_ETM                1  // Support ETM submodule
 #define SOC_GDMA_SUPPORT_SLEEP_RETENTION    1
 

components/soc/esp32h21/include/soc/Kconfig.soc_caps.in

@@ -347,14 +347,6 @@ config SOC_AHB_GDMA_VERSION
     int
     default 1
 
-config SOC_GDMA_NUM_GROUPS_MAX
-    int
-    default 1
-
-config SOC_GDMA_PAIRS_PER_GROUP_MAX
-    int
-    default 3
-
 config SOC_GDMA_SUPPORT_SLEEP_RETENTION
     bool
     default y

components/soc/esp32h21/include/soc/soc_caps.h

@@ -187,8 +187,6 @@
 
 /*-------------------------- GDMA CAPS -------------------------------------*/
 #define SOC_AHB_GDMA_VERSION                1U
-#define SOC_GDMA_NUM_GROUPS_MAX             1U
-#define SOC_GDMA_PAIRS_PER_GROUP_MAX        3
 // #define SOC_GDMA_SUPPORT_ETM                1  // Support ETM submodule TODO: IDF-11604
 #define SOC_GDMA_SUPPORT_SLEEP_RETENTION    1
 

components/soc/esp32h4/include/soc/Kconfig.soc_caps.in

@@ -247,14 +247,6 @@ config SOC_AHB_GDMA_VERSION
     int
     default 2
 
-config SOC_GDMA_NUM_GROUPS_MAX
-    int
-    default 1
-
-config SOC_GDMA_PAIRS_PER_GROUP_MAX
-    int
-    default 5
-
 config SOC_GDMA_SUPPORT_ETM
     bool
     default y
@@ -263,10 +255,6 @@ config SOC_GDMA_SUPPORT_SLEEP_RETENTION
     bool
     default y
 
-config SOC_AHB_GDMA_SUPPORT_PSRAM
-    bool
-    default y
-
 config SOC_ETM_GROUPS
     int
     default 1

components/soc/esp32h4/include/soc/soc_caps.h

@@ -180,11 +180,8 @@
 
 /*-------------------------- GDMA CAPS -------------------------------------*/
 #define SOC_AHB_GDMA_VERSION                2
-#define SOC_GDMA_NUM_GROUPS_MAX             1U
-#define SOC_GDMA_PAIRS_PER_GROUP_MAX        5
 #define SOC_GDMA_SUPPORT_ETM                1  // Support ETM submodule
 #define SOC_GDMA_SUPPORT_SLEEP_RETENTION    1
-#define SOC_AHB_GDMA_SUPPORT_PSRAM 1
 
 /*-------------------------- ETM CAPS --------------------------------------*/
 #define SOC_ETM_GROUPS                  1U  // Number of ETM groups

components/soc/esp32p4/include/soc/Kconfig.soc_caps.in

@@ -611,22 +611,6 @@ config SOC_GDMA_SUPPORT_CRC
     bool
     default y
 
-config SOC_GDMA_NUM_GROUPS_MAX
-    int
-    default 2
-
-config SOC_GDMA_PAIRS_PER_GROUP_MAX
-    int
-    default 3
-
-config SOC_AHB_GDMA_SUPPORT_PSRAM
-    bool
-    default y
-
-config SOC_AXI_GDMA_SUPPORT_PSRAM
-    bool
-    default y
-
 config SOC_GDMA_SUPPORT_ETM
     bool
     default y

components/soc/esp32p4/include/soc/soc_caps.h

@@ -226,10 +226,6 @@
 /*-------------------------- GDMA CAPS -------------------------------------*/
 #define SOC_AHB_GDMA_VERSION                2
 #define SOC_GDMA_SUPPORT_CRC                1
-#define SOC_GDMA_NUM_GROUPS_MAX             2
-#define SOC_GDMA_PAIRS_PER_GROUP_MAX        3
-#define SOC_AHB_GDMA_SUPPORT_PSRAM          1
-#define SOC_AXI_GDMA_SUPPORT_PSRAM          1
 #define SOC_GDMA_SUPPORT_ETM                1
 #define SOC_GDMA_SUPPORT_SLEEP_RETENTION    1
 #define SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT   (16)

components/soc/esp32p4/include/soc/soc_caps_full.h

@@ -23,11 +23,6 @@
 #define _SOC_CAPS_PCNT_CHANS_PER_UNIT             2  // Number of channels in each PCNT unit
 #define _SOC_CAPS_PCNT_THRES_POINT_PER_UNIT       2  // Number of threshold points in each PCNT unit
 
-/*--------------------------- 2D-DMA CAPS -------------------------------------*/
-#define _SOC_CAPS_DMA2D_INST_NUM                 1  // Number of 2D-DMA instances
-#define _SOC_CAPS_DMA2D_TX_CHANS_PER_INST        4  // Number of 2D-DMA TX (OUT) channels in each instance (4th channel only exists on P4 ver. >= 3.0)
-#define _SOC_CAPS_DMA2D_RX_CHANS_PER_INST        3  // Number of 2D-DMA RX (IN) channels in each instance (3rd channel only exists on P4 ver. >= 3.0)
-
 /*--------------------------- ETM (Event Task Matrix) ----------------------------*/
 #define _SOC_CAPS_ETM_INST_NUM                    1  // Number of ETM instances
 #define _SOC_CAPS_ETM_CHANS_PER_INST              50 // Number of channels in each ETM instance

components/soc/esp32s2/register/soc/cp_dma_struct.h

@@ -545,7 +545,7 @@ typedef union {
 } cp_dma_date_reg_t;
 
 
-typedef struct {
+typedef struct cp_dma_dev_t {
     volatile cp_dma_int_raw_reg_t dma_int_raw;
     volatile cp_dma_int_st_reg_t dma_int_st;
     volatile cp_dma_int_ena_reg_t dma_int_ena;

components/soc/esp32s3/include/soc/Kconfig.soc_caps.in

@@ -427,22 +427,6 @@ config SOC_AHB_GDMA_VERSION
     int
     default 1
 
-config SOC_GDMA_NUM_GROUPS_MAX
-    int
-    default 1
-
-config SOC_GDMA_PAIRS_PER_GROUP
-    int
-    default 5
-
-config SOC_GDMA_PAIRS_PER_GROUP_MAX
-    int
-    default 5
-
-config SOC_AHB_GDMA_SUPPORT_PSRAM
-    bool
-    default y
-
 config SOC_GPIO_PORT
     int
     default 1

components/soc/esp32s3/include/soc/soc_caps.h

@@ -172,10 +172,6 @@
 
 /*-------------------------- GDMA CAPS ---------------------------------------*/
 #define SOC_AHB_GDMA_VERSION           1U
-#define SOC_GDMA_NUM_GROUPS_MAX        1U
-#define SOC_GDMA_PAIRS_PER_GROUP       5 // esp32s3 has only one kind of GDMA, which is AHB GDMA, and it has 5 pairs in total.
-#define SOC_GDMA_PAIRS_PER_GROUP_MAX   5 // when there're multiple GDMA instances, this macro represents the maximum number of GDMA pairs in the same group.
-#define SOC_AHB_GDMA_SUPPORT_PSRAM     1
 
 /*-------------------------- GPIO CAPS ---------------------------------------*/
 // ESP32-S3 has 1 GPIO peripheral

docs/en/api-reference/system/async_memcpy.rst

@@ -12,14 +12,6 @@ The async memcpy API wraps all DMA configurations and operations. The signature
 
 The DMA allows multiple memory copy requests to be queued up before the first one is completed, which allows overlap of computation and memory copy. Moreover, it is still possible to know the exact time when a memory copy request is completed by registering an event callback.
 
-.. only:: SOC_AHB_GDMA_SUPPORT_PSRAM
-
-    If the async memcpy is constructed upon the AHB GDMA, it is also possible to copy data from/to PSRAM with a proper alignment.
-
-.. only:: SOC_AXI_GDMA_SUPPORT_PSRAM
-
-    If the async memcpy is constructed upon the AXI GDMA, it is also possible to copy data from/to PSRAM with a proper alignment.
-
 
 Configure and Install Driver
 ----------------------------

docs/zh_CN/api-reference/system/async_memcpy.rst

@@ -12,14 +12,6 @@
 
 DMA 允许多个内存复制请求在首个请求完成之前排队，即允许计算和内存复制的重叠。此外，通过注册事件回调函数，还可以知道内存复制请求完成的准确时间。
 
-.. only:: SOC_AHB_GDMA_SUPPORT_PSRAM
-
-    如果异步 memcpy 是基于 AHB GDMA 构建的，那么也可以用适合的对齐方式从 PSRAM 复制数据或向其中复制数据。
-
-.. only:: SOC_AXI_GDMA_SUPPORT_PSRAM
-
-    如果异步 memcpy 是基于 AXI GDMA 构建的，那么也可以用适合的对齐方式从 PSRAM 复制数据或向其中复制数据。
-
 
 配置并安装驱动
 ----------------------------