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fix(adc): fix ESP32 ADC continuous loss sample times

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This commit is contained in:
gaoxu
2025-10-22 10:11:18 +08:00
committed by Gao Xu
parent 53f1ef016e
commit 3086f8df50
7 changed files with 14 additions and 7 deletions
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components/esp_adc/adc_continuous.c
+4
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@@ -374,6 +374,10 @@ esp_err_t adc_continuous_start(adc_continuous_handle_t handle)
//start conversion //start conversion
adc_hal_digi_start(&handle->hal, handle->rx_dma_buf); adc_hal_digi_start(&handle->hal, handle->rx_dma_buf);
#if ADC_LL_DEFAULT_CONV_LIMIT_EN
adc_ll_digi_convert_limit_enable(false);
#endif
return ESP_OK; return ESP_OK;
} }
components/hal/esp32/include/hal/adc_ll.h
+5 -2
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -7,6 +7,7 @@
#pragma once #pragma once
#include <stdbool.h> #include <stdbool.h>
#include "esp_rom_sys.h"
#include "hal/adc_types.h" #include "hal/adc_types.h"
#include "hal/misc.h" #include "hal/misc.h"
#include "hal/assert.h" #include "hal/assert.h"
@@ -44,7 +45,7 @@ extern "C" {
//On esp32, ADC can only be continuously triggered when `ADC_LL_DEFAULT_CONV_LIMIT_EN == 1`, `ADC_LL_DEFAULT_CONV_LIMIT_NUM != 0` //On esp32, ADC can only be continuously triggered when `ADC_LL_DEFAULT_CONV_LIMIT_EN == 1`, `ADC_LL_DEFAULT_CONV_LIMIT_NUM != 0`
#define ADC_LL_DEFAULT_CONV_LIMIT_EN 1 #define ADC_LL_DEFAULT_CONV_LIMIT_EN 1
#define ADC_LL_DEFAULT_CONV_LIMIT_NUM 10 #define ADC_LL_DEFAULT_CONV_LIMIT_NUM 255
/*--------------------------------------------------------------- /*---------------------------------------------------------------
PWDET (Power Detect) PWDET (Power Detect)
@@ -154,6 +155,8 @@ static inline void adc_ll_digi_set_convert_limit_num(uint32_t meas_num)
*/ */
static inline void adc_ll_digi_convert_limit_enable(bool enable) static inline void adc_ll_digi_convert_limit_enable(bool enable)
{ {
//ESP32 has a hardware limitaton, meas_num_limit can only be cleared after ADC enters sample phase(10~15us after start)
esp_rom_delay_us(60);
SYSCON.saradc_ctrl2.meas_num_limit = enable; SYSCON.saradc_ctrl2.meas_num_limit = enable;
} }
components/hal/esp32c3/include/hal/adc_ll.h
+1 -1
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@@ -54,7 +54,7 @@ extern "C" {
#define ADC_LL_CLKM_DIV_B_DEFAULT 1 #define ADC_LL_CLKM_DIV_B_DEFAULT 1
#define ADC_LL_CLKM_DIV_A_DEFAULT 0 #define ADC_LL_CLKM_DIV_A_DEFAULT 0
#define ADC_LL_DEFAULT_CONV_LIMIT_EN 0 #define ADC_LL_DEFAULT_CONV_LIMIT_EN 0
#define ADC_LL_DEFAULT_CONV_LIMIT_NUM 10 #define ADC_LL_DEFAULT_CONV_LIMIT_NUM 255
/** /**
* Workaround: on ESP32C3, the internal hardware counter that counts ADC samples will not be automatically cleared, * Workaround: on ESP32C3, the internal hardware counter that counts ADC samples will not be automatically cleared,
components/hal/esp32c6/include/hal/adc_ll.h
+1 -1
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@@ -57,7 +57,7 @@ extern "C" {
#define ADC_LL_CLKM_DIV_B_DEFAULT 1 #define ADC_LL_CLKM_DIV_B_DEFAULT 1
#define ADC_LL_CLKM_DIV_A_DEFAULT 0 #define ADC_LL_CLKM_DIV_A_DEFAULT 0
#define ADC_LL_DEFAULT_CONV_LIMIT_EN 0 #define ADC_LL_DEFAULT_CONV_LIMIT_EN 0
#define ADC_LL_DEFAULT_CONV_LIMIT_NUM 10 #define ADC_LL_DEFAULT_CONV_LIMIT_NUM 255
/*--------------------------------------------------------------- /*---------------------------------------------------------------
PWDET (Power Detect) PWDET (Power Detect)
components/hal/esp32h2/include/hal/adc_ll.h
+1 -1
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@@ -57,7 +57,7 @@ extern "C" {
#define ADC_LL_CLKM_DIV_B_DEFAULT 1 #define ADC_LL_CLKM_DIV_B_DEFAULT 1
#define ADC_LL_CLKM_DIV_A_DEFAULT 0 #define ADC_LL_CLKM_DIV_A_DEFAULT 0
#define ADC_LL_DEFAULT_CONV_LIMIT_EN 0 #define ADC_LL_DEFAULT_CONV_LIMIT_EN 0
#define ADC_LL_DEFAULT_CONV_LIMIT_NUM 10 #define ADC_LL_DEFAULT_CONV_LIMIT_NUM 255
/*--------------------------------------------------------------- /*---------------------------------------------------------------
PWDET (Power Detect) PWDET (Power Detect)
components/hal/esp32s2/include/hal/adc_ll.h
+1 -1
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@@ -51,7 +51,7 @@ extern "C" {
#define ADC_LL_CLKM_DIV_B_DEFAULT 1 #define ADC_LL_CLKM_DIV_B_DEFAULT 1
#define ADC_LL_CLKM_DIV_A_DEFAULT 0 #define ADC_LL_CLKM_DIV_A_DEFAULT 0
#define ADC_LL_DEFAULT_CONV_LIMIT_EN 0 #define ADC_LL_DEFAULT_CONV_LIMIT_EN 0
#define ADC_LL_DEFAULT_CONV_LIMIT_NUM 10 #define ADC_LL_DEFAULT_CONV_LIMIT_NUM 255
/*--------------------------------------------------------------- /*---------------------------------------------------------------
PWDET (Power Detect) PWDET (Power Detect)
components/hal/esp32s3/include/hal/adc_ll.h
+1 -1
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@@ -51,7 +51,7 @@ extern "C" {
#define ADC_LL_CLKM_DIV_B_DEFAULT 1 #define ADC_LL_CLKM_DIV_B_DEFAULT 1
#define ADC_LL_CLKM_DIV_A_DEFAULT 0 #define ADC_LL_CLKM_DIV_A_DEFAULT 0
#define ADC_LL_DEFAULT_CONV_LIMIT_EN 0 #define ADC_LL_DEFAULT_CONV_LIMIT_EN 0
#define ADC_LL_DEFAULT_CONV_LIMIT_NUM 10 #define ADC_LL_DEFAULT_CONV_LIMIT_NUM 255
/*--------------------------------------------------------------- /*---------------------------------------------------------------
PWDET (Power Detect) PWDET (Power Detect)